Aristocrat USA MAV500/MKVI Service Manual page 293

Backplane Board
Pin Name, MAV/6
PIN
Main Board
C11 not used
A12 not used
B12 not used
C12 not used
A13 not used
B13 GND
C13 not used
A14 not used
B14 not used
C14 not used
A15 IRQDMON
B15 GND
C15 NC
A16 VBAT
B16 NC
C16 not used
A17 not used
B17 GND
C17 NC
A18 NEIF
B18 NEFHO
C18 NDACK
A19 NEFL
B19 GND
C19 NEIL0
A20 NERESET
B20 NEIOW
C20 NEIOR
A21 not used
B21 GND
C21 ECLK8M
A22 EA10
B22 EA11
C22 EA12
A23 EA8
B23 GND
C23 EA9
A24 EA5
B24 EA6
C24 EA7
A25 EA3
B25 GND
C25 EA4
A26 NC
B26 NC
C26 EA2
A27 NC
B27 GND
C27 NC
A28 ED5
B28 ED6
C28 ED7
A29 ED3
B29 GND
12-12
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and it may not be copied. All rights reserved. © Copyright (ATI) Aristocrat Technologies, Inc. 2002.
Connects
to ...
- Mechanical Security Switch 4 contact - NC
- Emitter 6 Drive signal, security 6
- Mechanical Security Switch 5 contact - NC
- Receiver 5 Sense signal, security 5
- Mechanical Security Switch 6 contact - NC
GND Gnd
- Receiver 6 Sense signal, security 6
- Mechanical Security Switch 7 contact - NC
- Receiver 7 Sense signal, security 7
- Emitter 7 Drive signal, security 7
J2-A6 Demon Interrupt Line
GND Gnd
- -
J2-B4 Battery Backup Voltage
- -
- Spare IO
- CPU, read not write signal
GND Gnd
- -
J3-C23 CPU, IF interrupt
J3-C21 CPU, FH0 interrupt
J2-B5 CPU, data acknowledge
J3-C22 CPU, FL interrupt
GND Gnd
J2-A5 CPU, IL0 interrupt
J2-B7 CPU, external reset output
J2-A7 CPU, IO write signal
J2-B6 CPU, IO read signal
- CPU, address bus 13
GND Gnd
J2-A8 CPU, clock signal
J2-B11 CPU, address bus
J2-A11 CPU, address bus 11
J2-B10 CPU, address bus 12
J2-B12 CPU, address bus
GND Gnd
J2-A12 CPU, address bus
J2-A14 CPU, address bus
J2-B13 CPU, address bus
J2-A13 CPU, address bus
J2-A15 CPU, address bus
GND Gnd
J2-B14 CPU, address bus
- -
- -
J2-B15 CPU, address bus
- -
GND Gnd
- -
J2-A19 CPU, data bus
J2-B18 CPU, data bus
J2-A18 CPU, data bus
J2-A20 CPU, data bus
GND Gnd
USA MAV500/MKVI Service Manual
Comment
28-00486-00