Microprocessor - Aristocrat USA MAV500/MKVI Service Manual

USA MAV500/MKVI Service Manual
10.4.1

Microprocessor

The Hitachi SH-4 (Model SH7750) is a high performance RISC microprocessor with
an architecture that is the leader in code density for this type of processor. The
device features up to 360 MIPS performance and a 128-bit graphic engine for
multimedia applications.
In addition to single- and double-precision floating-point operations, the on-chip FPU
(Floating Point Unit) has a 128-bit graphic engine that enables 32-bit floating-point
data to be processed 128 bits at a time. The unit also supports 4 x 4 array and
inner-product operations that enable performance of 1.4 GFLOPS to be achieved.
A superscalar architecture is employed that enables simultaneous execution of two
instructions (including FPU instructions) providing performance of up to twice that of
conventional architectures, at the same frequency.
On-chip peripheral modules include oscillator circuits, an interrupt controller, direct
memory access controller, timer unit, real-time clock, serial communication
interfaces, and a user-break controller.
Also provided are an 8-Kbyte-instruction cache and a 16-Kbyte data cache as well as
an on-chip memory management unit that handles translation from the 4-Gbyte
virtual address space to the physical address space. The bus-state controller
supporting external memory access can handle a 64-bit synchronous DRAM
(SDRAM) 4-bank system and a 64-bit data bus as well as ROM, SRAM, DRAM,
synchronous DRAM, and PCMCIA elements.
CPU Core
Processor features include:
Up to 200 MHz and 360 MIPS,
•
16 x 32-bit general purpose registers,
•
32 x 32-bit single-precision floating point registers, or 16 x 64-bit
•
double-precision floating point registers, or 4 x 128-bit single-precision vector
registers and a register matrix,
16-bit fixed instruction length for high code density,
•
A multiply-accumulate unit for special functions such as software modems (32- x
•
32 64-bits is transformed to become 64
±
MMU (Memory Management Unit) with 1
•
64 entry, fully associative UTLB (Unified Translation Lookaside Buffer),
−
Four-entry, fully associative µITLB (Instruction TLB),
•
Five-stage pipeline.
•
Memory
On-chip cache, 8
•
a. Write back or write through, selectable by page,
b. Low voltage cache to reduce power consumption.
28-00486-00
This document contains confidential information which is proprietary to ATI. It may not be disclosed to any unauthorized parties,
and it may not be copied. All rights reserved. © Copyright (ATI) Aristocrat Technologies, Inc. 2002.
Kbytes instruction and 16
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bits),
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, 4 , 64 Kbytes and 1
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Kbytes data lengths:
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Main Board
Mb page sizes,
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