Aristocrat USA MAV500/MKVI Service Manual page 234

USA MAV500/MKVI Service Manual
Data
bus
SH4_BLK_DIA.CDR
Figure 10-5 Hitachi SH-4 Microprocessor Block Diagram
I/O Data Bus
The SH-4 is designed to be interfaced to standard peripheral chips and all I/O
addresses in the processor are memory mapped.
The peripheral address bus is simply the latched address lines. These are buffered to
reduce loading and to avoid slowing down EPROM accesses.
Diagnostic LEDs
The SCIF communication channel is shared for LEDs on the Smart Card Interface.
These are connected to 2 easily visible diagnostic LEDs to indicate diagnostic
software status. The configuration of the circuit ensures that when the CPU is in
reset, or when the software does not run, all the LEDs will be turned on. Therefore,
faulty LEDs are easily detected and not interpreted as incorrect diagnostic code.
Interrupt System
The interrupt system of the SH-4 functions with four external interrupts. Specific
registers are provided in FPGA to enable the programmer to read the source of an
interrupt.
28-00486-00
This document contains confidential information which is proprietary to ATI. It may not be disclosed to any unauthorized parties,
and it may not be copied. All rights reserved. © Copyright (ATI) Aristocrat Technologies, Inc. 2002.
SH-4 CPU
* Two - way superscalar RISC
360 MIPs
Upward compatible with SH-1/2/3
Integer Unit Floating Point Unit
32 bit 64 bit
Cache
Data
16 Kbyte
Instruction
*WB/WT,
8 Kbyte
selectable
by page
Bus Unit
* Glueless interface to SDRAM,
EDO DRAM, fast page DRAM,
SRAM and ROM
* 65 / 32 / 16 / 8 / bits, 256-pin package
Memory Management Unit
* Full Windows CE support
* 1K/4K/64K/1MByte page sizes
Unified TLB Micro ITLB
64 entry 4 entry
Specialized Math Circuits
* Floating point
acceleration hardware
Peripheral Functions
* DMA controller
* Programmable power
management
* Interrupt controller
* Timers
* Real-time clock
* Serial interface
* User break controller
Main Board
10-11