Aristocrat USA MAV500/MKVI Service Manual page 260

USA MAV500/MKVI Service Manual
PIN No
A8 EMCS3
B8 MSSO2
C8 MSS2
A9 MSS3
B9 GNDD
C9 OPRIS3
A10 OPRIS4
B10 EMCS4
C10 MSSO3
A11 EMCS5
B11 GNDD
C11 MSS4
A12 EMCS6
B12 MSS5
C12 OPRIS5
A13 MSS6
B13 GNDD
C13 OPRIS6
A14 MSS7
B14 OPRIS7
C14 EMCS7
A15
B15 GNDD
C15
A16 VBAT0
B16
C16
A17 RNW
B17 GNDD
C17
A18 /EIF
B18 EFHO
C18 /DACK
A19 /EFL
B19 GNDD
C19 /EIL0
A20 /ERESET
B20 /EIOW
C20 /EIOR
A21 EA13
B21 GNDD
C21 ECLK8M
A22 EA10
B22 EA11
C22 EA12
A23 EA8
B23 GNDD
C23 EA9
A24 EA5
B24 EA6
28-00486-00
This document contains confidential information which is proprietary to ATI. It may not be disclosed to any unauthorized parties,
and it may not be copied. All rights reserved. © Copyright (ATI) Aristocrat Technologies, Inc. 2002.
Pin Name
Emitter 3 Drive signal, security 3
Mechanical Security Switch 2 contact - NO
Mechanical Security Switch 2 contact - NC
Mechanical Security Switch 3 contact - NC
Ground
Receiver 3 Sense signal, security 3
Receiver 4 Sense signal, security 4
Emitter 4 Drive signal, security 4
Mechanical Security Switch 3 contact - NO
Emitter 5 Drive signal, security 5
Ground
Mechanical Security Switch 4 contact - NC
Emitter 6 Drive signal, security 6
Mechanical Security Switch 5 contact - NC
Receiver 5 Sense signal, security 5
Mechanical Security Switch 6 contact - NC
Ground
Receiver 6 Sense signal, security 6
Mechanical Security Switch 7 contact - NC
Receiver 7 Sense signal, security 7
Emitter 7 Drive signal, security 7
---
Ground
---
Backup battery 0
---
---
CPU, read not write signal
Ground
---
CPU, IF interrupt
CPU, FH0 interrupt
CPU, data acknowledge
CPU, FL interrupt
Ground
CPU, IL0 interrupt
CPU, external reset output
CPU, IO write signal
CPU, IO read signal
CPU, address bus
Ground
CPU, clock signal
CPU, address bus
CPU, address bus
CPU, address bus
CPU, address bus
Ground
CPU, address bus
CPU, address bus
CPU, address bus
Comment
Main Board
10-37