Technical Description - Aristocrat USA MAV500/MKVI Service Manual

USA MAV500/MKVI Service Manual

10.4 Technical Description

The Technical Description begins with two diagrams: a block diagram introducing
the various functional subsystems of the Main Board and a layout diagram indicating
the location of components on the Main Board. A description of the various
functions and components of the Main Board follow these diagrams.
SDRAM
(16-Mbyte)
A(25:0)
SH-4
AD(63:0)
CPU
Address
Buffers
MPX
Data
Buffers
16
Memory
Expansion
Board
Interface
SH-4: Hitachi SuperH SH-4 Series RISC Microprocessor
FPGA: Field Programmable Gate Array
SRAM: Static Ramdom Access Memory
PCI: Peripheral Component Interconnection
EPROM: Erasable Programmable Read Only Memory
UART: Universal Asynchronous Receiver Transmitter
28-00486-00
This document contains confidential information which is proprietary to ATI. It may not be disclosed to any unauthorized parties,
and it may not be copied. All rights reserved. © Copyright (ATI) Aristocrat Technologies, Inc. 2002.
FPGA
FA(4:0)
MPX
Address
Buffers
ADDR(25:0)
DATA(63:0)
32 64
System
Game
EPROM
EPROM
Figure 10-3 Main Board Block Diagram
PLX9054
Local Bus
PCI Bridge
DATA(7:0)
ADDR(25:0)
SRAM
UART
I0150
Main Board
PCI
SDRAM
Mezzanine
(32-Mbyte)
Connector
PowerVR
PCI Bus
Graphics
MVP
Peripheral
Interface
MVP
Backplane
Interface
10-7