Processor 4/7 - EUROCOM M770CU Service Manual

Processor 4/7

P ROCESSOR CORE POWE R
V C O R E
I C CM AX Ma xi m um Pr oc e ss or S V 52
C o re I C C X E 65
V C O R E
C 6 3 1 C 6 3 3 C 6 3 2 C 6 2 7
C 6 3 7 C 6 4 1 C 6 4 0 C 6 4 5
C 6 5 1 C 6 5 4 C 6 5 9 C 6 4 8
V C O R E
C 2 0 1 C 2 0 7 C 2 0 8 C 2 0 9
C 4 1 7 C 4 3 0 C 4 3 6 C 4 1 6
C 4 8 7 C 4 6 4 C 4 3 7 C 4 3 8
PROCESSOR 4/7 ( POWER )
U 2 8 F
PROCE SSOR UNCO RE POWER
52A
A G3 5 A H 1 4
V C C 1 V T T 0 _ 1
A G3 4 A H 1 2
V C C 2 V T T 0 _ 2
A G3 3 A H 1 1 C 2 0 0
V C C 3 V T T 0 _ 3
A G3 2 A H 1 0
V C C 4 V T T 0 _ 4
A G3 1 J 1 4 1 0 U _ 6. 3V _ 06
V C C 5 V T T 0 _ 5
A G3 0 J 1 3
V C C 6 V T T 0 _ 6
A G2 9 H 1 4
A G2 8 V C C 7 V T T 0 _ 7 H 1 2
V C C 8 V T T 0 _ 8
A G2 7 G 1 4
V C C 9 V T T 0 _ 9
A G2 6 G 1 3
V C C 1 0 V T T 0 _ 1 0
A F 3 5 G 1 2
V C C 1 1 V T T 0 _ 1 1
A F 3 4 G 1 1
V C C 1 2 V T T 0 _ 1 2
A F 3 3 F 1 4 C 1 9 4
V C C 1 3 V T T 0 _ 1 3
A F 3 2 F 1 3
V C C 1 4 V T T 0 _ 1 4
A F 3 1 F 1 2 1 0 U _ 6. 3V _ 06
V C C 1 5 V T T 0 _ 1 5
A F 3 0 F 1 1
A F 2 9 V C C 1 6 V T T 0 _ 1 6 E 1 4
V C C 1 7 V T T 0 _ 1 7
A F 2 8 E 1 2
V C C 1 8 V T T 0 _ 1 8
A F 2 7 D 1 4
A F 2 6 V C C 1 9 V T T 0 _ 1 9 D 1 3
V C C 2 0 V T T 0 _ 2 0
A D 3 5 D 1 2
V C C 2 1 V T T 0 _ 2 1
A D 3 4 D 1 1
A D 3 3 V C C 2 2 V T T 0 _ 2 2 C 1 4
V C C 2 3 V T T 0 _ 2 3
A D 3 2 C 1 3
V C C 2 4 V T T 0 _ 2 4
A D 3 1 C 1 2
V C C 2 5 V T T 0 _ 2 5
A D 3 0 C 1 1
V C C 2 6 V T T 0 _ 2 6
A D 2 9 B 1 4
V C C 2 7 V T T 0 _ 2 7
A D 2 8 B 1 2
V C C 2 8 V T T 0 _ 2 8
A D 2 7 A 1 4
V C C 2 9 V T T 0 _ 2 9
A D 2 6 A 1 3
V C C 3 0 V T T 0 _ 3 0
A C 3 5 A 1 2
V C C 3 1 V T T 0 _ 3 1
A C 3 4 A 1 1
V C C 3 2 V T T 0 _ 3 2
A C 3 3
V C C 3 3
A C 3 2
V C C 3 4
A C 3 1
V C C 3 5
A C 3 0 A F 10
V C C 3 6 V T T 0 _ 3 3
A C 2 9 A E 10
V C C 3 7 V T T 0 _ 3 4
A C 2 8 A C 1 0 C 2 1 4
V C C 3 8 V T T 0 _ 3 5
A C 2 7 A B 10
V C C 3 9 V T T 0 _ 3 6
A C 2 6 Y 1 0 2 2 U _ 6. 3V _ X5 R _ 0 8
V C C 4 0 V T T 0 _ 3 7
A A 3 5 W 10
V C C 4 1 V T T 0 _ 3 8
A A 3 4 U 1 0
V C C 4 2 V T T 0 _ 3 9
A A 3 3 T 1 0
V C C 4 3 V T T 0 _ 4 0
A A 3 2 J 1 2
V C C 4 4 V T T 0 _ 4 1
A A 3 1 J 1 1
A A 3 0 V C C 4 5 V T T 0 _ 4 2 J 1 6 + V T T _4 3
V C C 4 6 V T T 0 _ 4 3
A A 2 9 J 1 5 + V T T _4 4
V C C 4 7 V T T 0 _ 4 4
A A 2 8
V C C 4 8
A A 2 7
V C C 4 9
A A 2 6
V C C 5 0
Y 3 5
V C C 5 1
Y 3 4
V C C 5 2
Y 3 3
V C C 5 3
Y 3 2
Y 3 1 V C C 5 4
V C C 5 5
Y 3 0 1K PU to V T T a nd 1 K P D t o G ND
V C C 5 6
Y 2 9
fo r P O C
V C C 5 7
Y 2 8
V C C 5 8
Y 2 7 VC ORE
V C C 5 9
Y 2 6
V C C 6 0
V 3 5 A N 3 3 P S I #
V C C 6 1 P S I #
V 3 4
V C C 6 2
V 3 3
V C C 6 3
V 3 2 A K 35
V C C 6 4 V I D [ 0 ] H _V I D 0 43
V 3 1 A K 33
V C C 6 5 V I D [ 1 ] H _V I D 1 43
V 3 0 A K 34
V C C 6 6 V I D [ 2 ] H _V I D 2 43
V 2 9 A L 3 5
V C C 6 7 V I D [ 3 ] H _V I D 3 43
V 2 8 A L 3 3
V 2 7 V C C 6 8 V I D [ 4 ] A M 3 3 H _V I D 4 43
H _V I D 5 43
V C C 6 9 V I D [ 5 ]
V 2 6 A M 3 5
V C C 7 0 V I D [ 6 ] H _V I D 6 43
U 3 5 A M 3 4
V C C 7 1 P R OC _ D P R S L P V R
U 3 4
V C C 7 2
U 3 3
V C C 7 3
U 3 2
V C C 7 4
U 3 1 G 1 5
H _ V T T V I D 1 4 1
V C C 7 5 V T T _ S E L E C T
U 3 0
V C C 7 6
U 2 9
U 2 8 V C C 7 7
V C C 7 8
U 2 7
V C C 7 9
U 2 6
R 3 5 V C C 8 0
V C C 8 1
R 3 4 TO V CORE POW ER CONT ROL
V C C 8 2
R 3 3
R 3 2 V C C 8 3 A N 3 5
8 2 9 2 _ I MO N 4 3
V C C 8 4 I S E N S E
R 3 1
V C C 8 5
R 3 0
V C C 8 6
R 2 9
V C C 8 7
R 2 8 A J 3 4
V C C _ S E N S E 4 3
V C C 8 8 V C C _ S E N S E
R 2 7 A J 3 5
V C C 8 9 V S S _ S E N S E V S S _ S E N S E 43
R 2 6
V C C 9 0
P 3 5
V C C 9 1
P 3 4 B 1 5
V T T _ S E N S E 4 1
V C C 9 2 V T T _ S E N S E
P 3 3 A 1 5
V C C 9 3 V S S _ S E N S E _ V T T
P 3 2
V C C 9 4
P 3 1
V C C 9 5
P 3 0
V C C 9 6
P 2 9
V C C 9 7
P 2 8
V C C 9 8
P 2 7
V C C 9 9
P 2 6
V C C 1 0 0
G9 8 9 P I N U P GA
1 . 1 V S _ V T T
VTT T OTAL 21A
C 2 0 5 C 1 9 5 C 2 2 0 C 1 93 C 2 1 3 C 5 5 3
10 U _ 6 . 3 V _ 0 6 1 0U _ 6 . 3 V _ 0 6 *1 0 U _ 6. 3V _ 06 * 10 U _ 6 . 3 V _ 0 6 2 2 U _ 6. 3V _ X5 R _ 0 8 2 2U _ 6 . 3 V _ X 5 R _ 0 8
C 1 9 6 C 1 9 7 C 2 2 1 I CC MAX _VT T Max C urr ent
f or VT T R ai l
10 U _ 6 . 3 V _ 0 6 1 0U _ 6 . 3 V _ 0 6 1 0 U _ 6 . 3 V _ 0 6
SV 18
XE 21
The decoupling capacitors, filter
recommendations and sense resistors on the
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
1 . 1 V S _ V T T
Design Guide
C 2 1 1 C 1 9 1
2 2U _ 6 . 3 V _ X 5 R _ 0 8 2 2 U _ 6. 3 V _X 5 R _ 0 8
1.1VS_VTT
Please note that the
R 4 1 9 0 _ 0 4
VTT Rail Values are
R 4 2 2 0 _ 0 4
Auburndale VTT=1.05V
Clarksfield VTT=1.1V
1. 1V S _ V T T
R 7 3
*1 K _ 0 4
1 . 1 V S _ V T T
R 1 5 2
*1 K _ 0 4
R 1 4 9
1 K _ 0 4
P M _D P R S L P V R 4 3
V C O R E 4 3
1 . 1 V S _ V T T 2 , 4 , 7 , 1 9, 20 , 2 1 , 2 2 , 2 5 , 2 6 , 2 7 , 4 1, 43
Schematic Diagrams
Sheet 6 of 55
Processor 4/7
Processor 4/7 B - 7