Processor 2/7 - EUROCOM M770CU Service Manual

Processor 2/7

Processor Compensation
Signals
R 8 7 4 9 . 9 _ 1% _ 0 4 H _C OM P 0
R 4 1 8 4 9 . 9 _ 1% _ 0 4 H _C OM P 1
R 9 1 2 0 _ 1 %_ 0 4 H _C OM P 2
R 9 5 2 0 _ 1 %_ 0 4 H _C OM P 3
T RACE WIDT H 10M IL, LENGT H <5 00MIL S
Processor Pullups
1 . 1 V S _ V T T
H _C A T E R R #
R 1 0 2 4 9 . 9 _ 1% _ 0 4
H _P R OC H O T #_ D
R 8 6 6 8 _ 0 4
R 8 3 * 6 8_ 0 4 H _C P U R S T #
43
I f PRO CHOT # is not used, the n it must be t ermi nated
w ith a 50- O pul l-up resi stor to V TT_1 .1 ra il.
2 2 , 4 3 D E L A Y _ P W R GD
2 5 H _ C P U P W R GD
2 2 P M _ D R A M_ P W R GD
2 2 H _ V T TP W R G D
Conne ct t o the Pro cesso r (V TTPW RGOOD ) VT T_1.1 VR power
good sign al to pro cesso r. S igna l vol tage leve l is 1.1 V.
2 4 , 2 9, 3 2 , 3 6 B U F _P L T _ R S T #
1 . 5 V S _ C P U
R 14 1
*1 . 1 K _ 1 % _0 4
V D D P W R G OO D _ R
R 13 7 R 1 6 9 1 . 5 K _ 1 %_ 0 4 D R A MP W R G D _ C P U
7 5 0_ 1 % _ 04
Int el ch ange
4.7 5K -- >1.1 K
12K -->3 K
PROCESSOR 2/7 ( CLK,MISC,JTAG )
DDR3 Compensation Signals
S M _R C O MP _ 0 R 4 3 1
S M _R C O MP _ 1 R 4 2 9
S M _R C O MP _ 2
R 4 2 8
U 28 B
H _ C O MP 3
A T 2 3
C O MP 3
H _ C O MP 2 A T 2 4
C O MP 2
H _ C O MP 1 G1 6
C O MP 1
H _ C O MP 0 A T 2 6
C O MP 0
A H 2 4
S K T OC C #
D P LL _ R E F _S S C L K
D P L L_ R E F _ S S C L K #
H _ C A TE R R # A K 1 4
C A TE R R #
S M_ D R A M R S T #
2 5 , 3 6 H _ P E C I A T 1 5
P E C I
S M_ R C O MP [ 0 ]
S M_ R C O MP [ 1 ]
S M_ R C O MP [ 2 ]
H _ P R OC H O T# _ D
R 8 8 0 _0 4 A N 2 6
H _ P R O C H OT #
P R OC H OT #
P M_ E X T _T S # [ 0 ]
P M_ E X T _T S # [ 1 ]
2 5 H _ TH R M T R I P # A K 1 5
T H E R MT R I P #
H _ C P U R S T# A P 2 6
R E S E T _O B S #
A L 1 5
2 2 H _ P M_ S Y N C
P M _S Y N C
R 10 7 *0 _ 0 4 S Y S _ A G E N T _ P W R OK A N 1 4
V C C P W R GO OD _ 1
R 10 3 * 1 0m i l _s h o rt
A N 2 7
V C C P W R GO OD _ 0
V D D P W R GO OD _R
R 14 0 * 1 0m i l _s h o rt A K 1 3
S M _D R A M P W R OK
A M1 5
V T T P W R G OO D
H _ P W R GD _ XD P A M2 6
T A P P W R GO OD
P L T_ R S T #_ R
R 14 7 1 . 5 K _ 1% _ 0 4 A L 1 4
R S TI N #
Si gnal from PCH to P roces sor
Co nnect to PCH ( PLT_ RST#) R 1 4 6
(n eeds to b e lev el t ransl ated
7 50 _ 1 % _0 4 G 98 9 P I N U P G A
fr om 3. 3 V to 1. 1 V) .
3 . 3 V
R 1 8 0 8 . 2 K _ 0 4
U 4 0
I N 3 . 3 V
1
4
2
1 . 1 V S _ V T T _P W R G D 2 2 , 4 0, 4 1
MC 7 4 V H C 1G 0 8D F T 1 G
1 . 5 V
R 14 4
1 K _ 0 4
R 1 55 * 0_ 0 4
BSS1 38 ( VGS 1.5V )
1 0 0 _ 1% _ 0 4 Q 3 6
R J U 0 0 3 N 0 3 T1 0 6
2 4 . 9 _ 1% _ 0 4 S M _D R A M R S T# S D
D D R 3 _ D R A MR S T # 1 0, 1 1
1 3 0 _ 1% _ 0 4
R 1 53
1 0 0 K _0 4
D R A MR S T _C T R L 9 , 2 5
C 7 0 7 ? ? I BEX CONTR OL
47 0 P _ 5 0V _ 0 4
A 1 6
B C L K B C L K _C P U _P 25
B 1 6
B C L K _C P U _N 2 5
B C L K #
A R 3 0
B C L K _ I T P
A T 3 0
B C LK _I T P #
E 1 6
C LK _E X P _ P 2 1
P E G _ C L K
D 1 6
P E G_ C L K # C LK _E X P _ N 2 1
A 1 8
C LK _D P _ P 2 1
A 1 7
C LK _D P _ N 2 1
F 6 S M_ D R A M R S T #
1 . 1 V S _ V T T
A L 1 S M_ R C O MP _ 0
A M 1 S M_ R C O MP _ 1 R 1 14 1 0 K _ 04
A N 1 S M_ R C O MP _ 2 R 1 22 1 0 K _ 04
A N 1 5 P M_ E X T T S #[ 0] R 1 23 * 0_ 0 4
P M_ E X T T S # _E C 3
A P 15 P M_ E X T T S #[ 1] R 1 18 * 0_ 0 4
T S #_ D I MM 0 _1 1 0 , 1 1
R 1 15 * 12 . 4 K _ 1 % _0 4
A T 2 8
P R D Y #
A P 27 XD P _ P R E Q#
P R E Q#
A N 2 8 XD P _ T C L K
TC K
A P 28 XD P _ T MS
TM S
A T 2 7 XD P _ T R S T #
T R S T #
XD P _ T D I _ R
A T 2 9
TD I
A R 2 7 XD P _ T D O _R
T D O
XD P _ T D I _ M 1 . 1 V S _ V T T
A R 2 9
T D I _ M A P 29 XD P _ T D O _M
T D O _ M
X D P _T M S
R 8 2 * 51 _ 0 4
A N 2 5 X D P _T D O_ M R 7 9 5 1 _ 04
D B R #
X D P _T D I _R R 8 1 * 51 _ 0 4
X D P _P R E Q # R 7 6 * 51 _ 0 4
A J 2 2 X D P _T D O_ R R 8 5 * 51 _ 0 4
B P M# [ 0 ]
A K 22
B P M# [ 1 ]
A K 24
B P M# [ 2 ]
A J 2 4
B P M# [ 3 ]
A J 2 5
B P M# [ 4 ]
A H 2 2
B P M# [ 5 ]
A K 23 X D P _T C LK R 8 0 * 51 _ 0 4
B P M# [ 6 ]
A H 2 3 X D P _T R S T # R 8 4 5 1 _ 04
B P M# [ 7 ]
X D P _T D O_ M R 1 48 *1 0 mi l _ sh o rt XD P _ T D I _ M
3 . 3 V 3, 12 , 1 3 , 2 0, 2 1 , 2 2 , 24 , 2 5 , 2 7, 2 9 , 3 0 , 31 , 3 2 , 3 3, 34 , 3 7 , 3 9, 4 0 , 4 1
1 . 5 V 9, 10 , 1 1 , 3 7, 4 0 , 4 2
1 . 5 V S _ C P U 7 , 3 7
1 . 1 V S _ V T T 2 , 6 , 7, 1 9 , 2 0 , 21 , 2 2 , 2 5, 26 , 2 7 , 4 1, 4 3
Schematic Diagrams
Sheet 4 of 55
Processor 2/7
Processor 2/7 B - 5