Panel, Inverter, Crt - EUROCOM M770CU Service Manual

Panel, Inverter, CRT

PAN EL
3 . 3 V S
R 315 2 . 2 K_ 04 R 3 39 *0 _0 4_+ U
R 309 2 . 2 K_ 04 R 3 38 *0 _0 4_+ U
R 2 0 _04 _-U
R 1 0 _04 _-U
J _LC D 1
1 2 D D C _D A TA
1 2
LV D S U C L K N 3 4 D D C _C LK L VD S LP 0
LV D S U C L K P 3 4 L VD S LN 0
5 6
7 5 6 8 LV D SU N 2 L VD S LN 1
7 8
LV D S U N 1 9 10 LV D SU P 2 L VD S LP 1
9 10
LV D S U P 1 11 12
11 12
13 14 LV D SU N 0
LV D S LC LK N 13 14 LV D SU P 0
15 16
15 16
LV D S LC LK P 17 18
19 17 18 20 LV D SL N 2 L VD S LC L KP
19 20
LV D S LN 1 21 22 LV D SL P 2 L VD S LC L KN
21 22
LV D S LP 1 23 24
23 24
25 26
LV D S LN 0 27 25 26 28 3. 3V S
27 28
LV D S LP 0 29 30
29 30
C 3
8 81 07-3 000 1 L VD S U N 1
L VD S U P 1
. 1 U _1 6V _04
2A
PL VD D
C 46 1 L VD S U C LK P
L VD S U C LK N
L VD S U P 2
. 1U _5 0V _0 6
L VD S U N 2
PL VD D _ EN
default: HYBRID Z1 40 3
19 VGA _E N A VD D R 331 * 0_0 4_ +U B Q37
R 330 0 _0 4_- U
23 N B_ EN A V D D D TC 1 14 EU A
R 332
100 K_ 04
CRT
FOR SINGLE GRAPHIC
V GA_ R R 94 *0_ 04 _+U Y R E D
D A C _R E D R 42 5 0_ 04_ - U
V GA_ G Y GR EE N
R 93 *0_ 04 _+U
D A C _GR E EN R 42 6 0_ 04_ - U
V GA_ B R 92 *0_ 04 _+U Y B LU E
D A C _B LU E R 42 7 0_ 04_ - U
V _H S Y R 42 1 *0_ 04 _+U H _S Y N C
D A C _H S Y N C R 42 4 0_ 04_ - U
V _V SY V _S Y N C
R 42 0 *0_ 04 _+U
D A C _V SY N C
R 42 3 0_ 04_ - U
P LACE NEA R PI 3V512 QE U NDER SID E
2 3 D AC _ D D C A D A TA
2 3 D AC _ D D C A C L K
1 4 VGA _D D C D A TA
1 4 VGA _D D C C L K
FOR SG
R 36 3 0_ 04 _- H
25 E D I D _S E LE C T#
R 36 2 *0 _04 _+H U 2 4
2 4, 46 d GPU _ S EL EC T #
1 1 6
SE L VC C
V GA_ D D C D AT A 2 4
1A 0 Y A
D A C _D D C A DA T A 3 7
V GA_ D D C C LK 5 1A 1 Y B 9
1B 0 Y C
D A C _D D C A CL K 6 1 2
1B 1 Y D
0 225 S D A 1 1 1 3
1C 0 1 D 1
P _D D C _D A TA 1 0 1 4
1C 1 1 D 0
1 5 8
E GN D
*TI 5V 33 0D B QR _+ H
3. 3V 3 . 3 V
FOR SG
U 6
4 VC C 1
1 0
VC C 2
1 8
VC C 3
2 7 48
VC C 4 0B 1 M9 2_L VD S -U 0N 19
3 8 47 M9 2_L VD S -U 0P 19
VC C 5 1B 1
5 0 43
VC C 6 2B 1 M9 2_L VD S -U 1N 19
5 6 VC C 7 3B 1 42 M9 2_L VD S -U 1P 19
S D A 37
S D A 14 4B 1 M9 2_L VD S -U 2N 19
S C L 36
S C L 14 5B 1 M9 2_L VD S -U 2P 19
32
M9 2_L VD S -U C LK N 19
6B 1
7B 1 31 M9 2_L VD S -U C LK P 1 9
LV D SU N 0 LV D S LC LK N
EDID Mod e 2 22
A0 8B 1 V GA_ EN A V D D 1 9
LV D SU P 0 3 23 LV D S LC LK P
A1 9B 1 V GA_ BK LT EN 19
P _D D C _D A TA LV D SU N 1 7 LV D S LN 1
P _D D C _ D AT A 23 A2
P _D D C _C L K P _D D C _ C LK 2 3 LV D SU P 1 8 LV D S LP 1
LV D SU N 2 A3 LV D S LN 2
1 1
A4
LV D SU P 2 LV D S LP 2
1 2 A5
LV D SU C L KN 1 4 LV D S LN 0
A6
LV D SU C L KP 1 5 46 LV D S LP 0
A7 0B 2 L VD S -U 0N 23
5 4 PL VD D _ EN 1 9 45 H _S Y N C
L VD S -U 0P 2 3
G P U _ BL ON A8 1B 2 V _S Y N C
6 3 C P 4 2 0 41
7 2 *1 0P _1 2_8 P4 C A9 2B 2 40 L VD S -U 1N 23
3B 2 L VD S -U 1P 2 3
8 1 35
4B 2 L VD S -U 2N 23
34
L VD S -U 2P 2 3
5B 2
30
LV D S LP 2 6B 2 L VD S -U C LK N 2 3
5 4 29
7B 2 L VD S -U C LK P 23
6 3 LV D S LN 2 25
7 2 C P 3 8B 2 26 N B _E N A VD D 23
9B 2 B L ON 23
8 1 *1 0P _1 2_8 P4 C 1
G N D 1
6
G N D 2
9
1 3 G N D 3
G N D 4
5 4 LV D S U P 0 1 6 17
G N D 5 S E L1
6 3 LV D S U N 0 2 1 54 d GPU _ SE LE C T#
G N D 6 S E L2
7 2 C P 2 2 4
G N D 7
8 1 *1 0P _1 2_8 P4 C 2 8 L : A -- >B 1 ( E XT E R N A L G R A P H I C )
G N D 8
3 3
3 9 G N D 9 H : A -- >B 2 ( I N T ER N A L G R A P H I C )
G N D 1 0
5 4 4 4
G N D 1 1
6 3 C P 1 4 9 51
G N D 1 2 N C 1
7 2 *1 0P _1 2_8 P4 C 5 3 52
8 1 5 5 G N D 1 3 N C 2 5
G N D 1 4 D N C
5 7
G N D 1 5
*T S3 D V5 20 ER H U R G4_ +H
3 . 3V S C O - L AY
NE AR PI N4 ,5 U 3 2A
4 1
V I N VOU T IN VER TER CO NNE CTOR
5
V I N
C 488
3 2
E N GN D
*1U _1 0V _0 6
*G52 43 A
R 3 47
36 B KL _E N
S Y S 15V S Y S 15V R 34 5
19 VGA _B K LTE N
R 34 6
2 3 B LON
default: HYBRID
R 335 R 337 U 2 5 C 4
1 6
D D
1M_0 4 100 K _04 . 1U _ 16 V_ 04
P L VD D
2 5 R 7
D D
2A
Z 1 404 3 4 R 344
G S
Q39 S I 34 56 BD V -T1- E 3
2 5 S B_ B LON
R 33 3 R 3 34 C 6 C 46 2 R 3 36
G C 45 8
MTN 70 02 ZH S 3 33 0_0 4 *200 _0 4 . 1 U _ 16 V_ 04 10 U _10 V_ 08 * 100 K_ 04
. 1U _ 25V _X 7R _ 06
22 , 36 A LL_ S Y S_ PW R GD
Z 14 05
Q3 8
G
MTN 70 02Z H S 3
3. 3V S
5V S
C 550 *. 1 U _1 6V _0 4_+ H
FOR SG
D 1 9 D 18
U 39 B A V9 9 B AV 99
dGP U _S E LE C T#
1 16
SE L VC C
2 4 Y R E D
14 VGA _R 1A 0 YA
3 7 Y GR E EN
23 D AC _ R ED 1A 1 YB
5 9 Y B LU E
14 VGA _G 1B 0 Y C
6 12
23 D AC _ GRE E N 1B 1 Y D
14 VGA _B 1 1 1C 0 1 D 1 13
1 0 14
23 D AC _ BL U E 1C 1 1 D 0
1 5 8
E GN D
R 3 49 R 36 6 R 35 4 C 4 70 C 48 5
*TI 5V 33 0D B QR _+ H
1 50 _1% _04 15 0_ 1%_ 04 15 0_1 %_0 4 2 2P _50 V _04 22 P_ 50 V_ 04
S E L :
PLE ASE CL OSE T O C ONN ECT OR
1 : Y A =1 A 1 I N T E R N A L G R A P H I C
0 : Y A =1 A 0 EX T E R N A L G R A P H I C
5V S
3. 3 VS
R 30 4 . 7 K_ 04
R 31 2. 2K _0 4
D A C _D D C A D AT A R 348 0_0 4_ - U R 16 4 . 7 K_ 04
R 9 2. 2K _0 4
D A C _D D C A C LK
R 25 0_0 4_ - U
Q3
V GA_ D D C D AT A R 357 *0_ 04_ +U D D C A D A TA - C S D MT N 700 2Z H S3 Z 141 4 L 5 F C M10 05K F -121 T0 3_0 4
Q7 .
V GA_ D D C C LK D D C A C LK -C Z 141 5
R 17 *0_ 04_ +U S D MTN 70 02 ZH S 3 L 10 F C M10 05K F -121 T0 3_0 4
.
FO R EXT -V GA ON LY Z 141 6 L 7 F C M10 05K F -121 T0 3_0 4
.
Z 141 7 L 9 F C M10 05K F -121 T0 3_0 4
5V S .
C 5 60 * . 1 U _1 6V _04 _+ H H _S Y N C 2 4
U 3 5
74A H C T1 G125 GW
5 VS
D D C A D AT A-C
D D C A C LK - C C 67 2 0. 1 U _16 V_ 04
D D C _D A TA
D D C _C L K
P _D D C _C L K
S C L
V_ SY N C 2 4
S E L : U 3 6
1 : Y A =1 A 1 I N T E R N A L G R A P H I C 74A H C T1 G125 GW
5 VS
0 : Y A =1 A 0 EX T E R N A L G R A P H I C
C 67 3 0. 1 U _16 V_ 04
FOR SG FOR INTEGRAPHIC
L VD S LN 0 2 3 R N 27 L VD S -L0 N
U 5 L VD S LP 0 1 4 4P 2 R X 0_ 04_ -U L VD S -L0 P
4 V C C 1 L VD S LN 1 2 3 R N 23 L VD S -L1 N
L VD S LP 1 L VD S -L1 P
1 0 1 4 4P 2 R X 0_ 04_ -U
V C C 2
1 8
V C C 3
2 7 48 L VD S LN 2 1 4 R N 25 L VD S -L2 N
V C C 4 0B 1 M92 _LV D S - L C LK N 19
3 8 47 M92 _LV D S - L C LK P 1 9 L VD S LP 2 2 3 4P 2 R X 0_ 04_ -U L VD S -L2 P
V C C 5 1B 1
5 0 43
V C C 6 2B 1 M92 _LV D S - L 1N 19
L VD S LC L KN L VD S -LC LK N
5 6 V C C 7 3B 1 42 M92 _LV D S - L 1P 19 1 4 R N 21
37 L VD S LC L KP 2 3 4P 2 R X 0_ 04_ -U L VD S -LC LK P
4B 1 M92 _LV D S - L 2N 19
36
5B 1 M92 _LV D S - L 2P 19
32 L VD S U N 0 2 3 R N 13 L VD S -U 0N
M92 _LV D S - L 0N 19
6B 1 L VD S U P 0 L VD S -U 0P
7B 1 31 M92 _LV D S - L 0P 19 1 4 4P 2 R X 0_ 04_ -U
2 22
A 0 8B 1 V_ H SY 1 4
3 23 L VD S U N 1 2 3 R N 15 L VD S -U 1N
A 1 9B 1 V_ V SY 1 4
7 L VD S U P 1 1 4 4P 2 R X 0_ 04_ -U L VD S -U 1P
A 2
8
A 3 L VD S U N 2 L VD S -U 2N
1 1 1 4 R N 17
A 4
L VD S U P 2 L VD S -U 2P
1 2 A 5 2 3 4P 2 R X 0_ 04_ -U
1 4
A 6
1 5 46 L VD S U C LK N 2 3 R N 19 L VD S -U C LK N
A 7 0B 2 LV D S- L C LK N 2 3
1 9 45 L VD S U C LK P 1 4 4P 2 R X 0_ 04_ -U L VD S -U C LK P
LV D S- L C LK P 2 3
A 8 1B 2
2 0 41
A 9 2B 2 40 LV D S- L 1N 23
FOR EXT GRAPHIC
3B 2 LV D S- L 1P 2 3
35
4B 2 LV D S- L 2N 23
34
LV D S- L 2P 2 3
5B 2
30 L VD S LN 0 1 4 R N 26 M9 2_ LV D S-L0 N
6B 2 LV D S- L 0N 23 L VD S LP 0 M9 2_L VD S -L0 P
29 2 3 *4 P2 R X0_ 04 _+U
7B 2 LV D S- L 0P 2 3
25
8B 2 26 DA C _H S Y N C 23 L VD S LN 1 1 4 R N 22 M9 2_L VD S -L1 N
9B 2 DA C _V S Y N C 2 3
1 L VD S LP 1 2 3 *4 P2 R X0_ 04 _+U M9 2_L VD S -L1 P
GN D 1
6
GN D 2 L VD S LN 2 M9 2_L VD S -L2 N
9 2 3 R N 24
1 3 GN D 3 L VD S LP 2 1 4 *4 P2 R X0_ 04 _+U M9 2_L VD S -L2 P
GN D 4
1 6 17
GN D 5 S EL 1
2 1 54 L VD S LC L KN 2 3 R N 20 M9 2_L VD S -LC L KN
d GPU _ SE L EC T # 24, 4 6
GN D 6 S EL 2
2 4 L VD S LC L KP 1 4 *4 P2 R X0_ 04 _+U M9 2_L VD S -LC L KP
GN D 7
2 8 L : A --> B 1 (E X T E RN A L G R A P H I C )
GN D 8
3 3 L VD S U N 0 1 4 R N 12 M9 2_L VD S -U 0N
3 9 GN D 9 H : A --> B 2 (I N T E R N A L G R A P H I C ) L VD S U P 0 2 3 *4 P2 R X0_ 04 _+U M9 2_L VD S -U 0P
GN D 1 0
4 4
GN D 1 1 L VD S U N 1 M9 2_L VD S -U 1N
4 9 51 1 4 R N 14
GN D 1 2 N C 1
L VD S U P 1 M9 2_L VD S -U 1P
5 3 52 2 3 *4 P2 R X0_ 04 _+U
5 5 GN D 1 3 N C 2 5
GN D 1 4 D N C
5 7 L VD S U N 2 2 3 R N 16 M9 2_L VD S -U 2N
GN D 1 5 L VD S U P 2 1 4 *4 P2 R X0_ 04 _+U M9 2_L VD S -U 2P
L VD S U C LK N M9 2_L VD S -U C LK N
*TS 3D V 5 20E R H U R G4_ +H 1 4 R N 18
L VD S U C LK P 2 3 *4 P2 R X0_ 04 _+U M9 2_L VD S -U C LK P
PLAC E NE AR P I2PCI E412 -D U NDER SIDE
3. 3V
V I N L 1 V I N _I N V
H C B 16 08 KF -12 1T2 5
*1 00K _0 4 U 26 A .
3. 3V
74 LV C 08 PW
1 C 4 57 C 1
3 U 2 6B 40 m il
*0_ 04_ +U GP U _B L O N 2 7 4LV C 08 P W . 1 U _50 V _06 . 1U _5 0V _0 6
3. 3V
0_ 04_ -U Z 14 06 4
6
5
U 26 C L ED PA NE L ? ? ? ? ? ? ? ? J_ I N V 1
7 4LV C 08 PW
1
1 00 K_ 04 Z 14 07 9 R 3
2
8 Z 140 9 4. 7 K_ 04 I N V _B LON
3
*1 00 K_ 04 3. 3V Z 14 08 10
4
5
U 2 6D C 2
6
7 4LV C 08 P W R 4
12 1 U _6. 3 V_ X5 R _ 04 87 21 3-06
3 3, 36 LI D _S W #
11 *1M_ 04
13
6-20-41A10-1 06
J_ IN V1
1
36 B R I G H T N ES S
3. 3V
D 29 6
D0 3A
*B AV 99
C 1 3
*. 1 U _10 V_ X7 R _04
J _C R T1
D 20 C 105 09 -915 05 - L
BA V 99
FR E D
L 4 F C M100 5K F - 1 21 T03 _0 4 1
.
9
L 6 F C M100 5K F - 1 21 T03 _0 4 FGR N 2 24 mil
.
10
L 8 F C M100 5K F - 1 21 T03 _0 4 FB LU E 3
.
11
4
C 46 6 C 46 8 C 471 12 D D C D A TA
C 481 5
22 P _50 V_ 04 22 P_ 50V _ 04 22P _5 0V _0 4 13 H SY N C
22 P_ 50V _0 4 6
14 VS Y N C
7
15 D D C L K
8
R 20 *1K _0 4
5 VS
R 24 *1K _0 4
D D C D A TA
D D C L K
H S Y N C
V S Y N C
D 21 D 2 D 22 D 1
B A V9 9 B A V9 9 *B A V9 9 *B A V9 9
1. 8V 1 9, 37 , 3 9
3. 3V 3 , 4 , 13, 2 0, 21 , 2 2, 2 4, 25 , 2 7, 29 , 30, 3 1, 32 , 33, 3 4, 37 , 3 9, 40 , 41
3. 3V S 2 , 1 0, 11 , 13, 1 4, 20 , 21, 2 2, 23 , 2 4, 25 , 26, 2 7, 29 , 30, 3 1, 32 , 3 3, 3 5, 36 , 3 7, 42 , 43, 4 4, 46
5V 2 7, 31 , 3 5, 37 , 39, 4 0, 41 , 44
5V S 2 0, 23 , 2 7, 31 , 33, 3 5, 37 , 42, 4 3, 46
SY S 15 V 1 9, 37 , 3 8
5 VS 5 VS 5 VS 5 VS
VI N 3 3, 37 , 3 8, 39 , 40, 4 1, 42 , 43, 4 4, 45
Schematic Diagrams
Sheet 12 of 55
Panel, Inverter,
CRT
Panel, Inverter, CRT B - 13