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The SHI interrupt vector table is shown in
shown in
Table
7-2.
Program Address
VBA:$0040
VBA:$0042
VBA:$0044
VBA:$0048
VBA:$004A
VBA:$004C
Priority
Highest
Lowest
7.4.1
SHI Input/Output Shift Register (IOSR)—Host Side
The variable length Input/Output Shift Register (IOSR) can be viewed as a serial-to-parallel and
parallel-to-serial buffer in the SHI. The IOSR is involved with every data transfer in both directions (read
and write). In compliance with the I
data transfer modes, the most significant byte of the IOSR is used as the shift register. In 16-bit data
transfer modes, the two most significant bytes become the shift register. In 24-bit transfer modes, the shift
register uses all three bytes of the IOSR (see
The IOSR cannot be accessed directly either by the host processor or by the
DSP. It is fully controlled by the SHI controller logic.
Freescale Semiconductor
Table 7-1
Table 7-1 SHI Interrupt Vectors
SHI Transmit Data
SHI Transmit Underrun Error
SHI Receive FIFO Not Empty
SHI Receive FIFO Full
SHI Receive Overrun Error
SHI Bus Error
Table 7-2 SHI Internal Interrupt Priorities
SHI Bus Error
SHI Receive Overrun Error
SHI Transmit Underrun Error
SHI Receive FIFO Full
SHI Transmit Data
SHI Receive FIFO Not Empty
2
C and SPI bus protocols, data is shifted in and out MSB first. In 8-bit
Figure
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Serial Host Interface Programming Model
and the exception priorities generated by the SHI are
Interrupt Source
Interrupt
7-5).
NOTE
7-5
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