Errata - Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification

Errata

AW1. EFLAGS Discrepancy on Page Faults after a Translation Change
This erratum is regarding the case where paging structures are modified to
Problem:
change a linear address from writable to non-writable without software
performing an appropriate TLB invalidation. When a subsequent access to
that address by a specific instruction (ADD, AND, BTC, BTR, BTS, CMPXCHG,
DEC, INC, NEG, NOT, OR, ROL/ROR, SAL/SAR/SHL/SHR, SHLD, SHRD, SUB,
XOR, and XADD) causes a page fault, the value saved for EFLAGS may
incorrectly contain the arithmetic flag values that the EFLAGS register would
have held had the instruction completed without fault. This can occur even if
the fault causes a VM exit or if its delivery causes a nested fault.
Implication: None identified. Although the EFLAGS value saved may contain incorrect
arithmetic flag values, Intel has not identified software that is affected by this
erratum. This erratum will have no further effects once the original instruction
is restarted because the instruction will produce the same results as if it had
initially completed without a page fault.
Workaround: If the page fault handler inspects the arithmetic portion of the saved EFLAGS
value, then system software should perform a synchronized paging structure
modification and TLB invalidation.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW2.
INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain
Conditions
The INVLPG instruction may not completely invalidate Translation Look-aside
Problem:
Buffer (TLB) entries for large pages (2M/4M) when both of the following
conditions exist:
• Address range of the page being invalidated spans several Memory
Type Range Registers (MTRRs) with different memory types specified
•
INVLPG operation is preceded by a Page Assist Event (Page Fault (#PF) or an
access that results in either A or D bits being set in a Page Table Entry (PTE))
Implication: Stale translations may remain valid in TLB after a PTE update resulting in
unpredictable system behavior. Intel has not observed this erratum with any
commercially available software.
Workaround: Software should ensure that the memory type specified in the MTRRs is the
same for the entire address range of the large page.
For the steppings affected, see the Summary Tables of Changes.
Status:
18
Errata
® ™
Intel Core 2 Duo Processor
Specification Update