Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 40

AW60. VM Entry May Fail When Attempting to Set
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN
If bit 14 (FREEZE_WHILE_SMM_EN) is set in the IA32_DEBUGCTL field in the
Problem:
guest-state area of the VMCS, VM entry may fail as described in Section "VM-
Entry Failures During or After Loading Guest State" of Intel
Architectures Software Developer's Manual Volume 3B: System Programming
Guide, Part 2. (The exit reason will be 80000021H and the exit qualification
will be zero.) Note that the FREEZE_WHILE_SMM_EN bit in the guest
IA32_DEBUGCTL field may be set due to a VMWRITE to that field or due to a
VM exit that occurs while IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN=1.
Implication: A VMM will not be able to properly virtualize a guest using the
FREEZE_WHILE_SMM feature.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Alternatively, the following software workaround may be used. If a VMM
wants to use the FREEZE_WHILE_SMM feature, it can configure an entry in
the VM-entry MSR-load area for the IA32_DEBUGCTL MSR (1D9H); the value
in the entry should set the FREEZE_WHILE_SMM_EN bit. In addition, the
VMM should use VMWRITE to clear the FREEZE_WHILE_SMM_EN bit in the
guest IA32_DEBUGCTL field before every VM entry. (It is necessary to do this
before every VM entry because each VM exit will save that bit as 1.) This
workaround prevents the VM-entry failure and sets the
FREEZE_WHILE_SMM_EN bit in the IA32_DEBUGCTL MSR.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW61. Processor May Hold-off / Delay a PECI Transaction Longer than
Specified by the PECI Protocol
PECI (Platform Environment Control Interface) transactions may be held off
Problem:
longer than the PECI protocol hold-off limit while the processor is exiting C-
states. This may occur if STPCLK# has been asserted by the system, the
beginning of a PECI message coincides with a C-state transition, and the
processor is executing a long instruction flow. Note that the processor can still
complete the PECI transaction if the host chooses to process the remainder of
the message.
Implication: Due to this erratum, the processor may violate the PECI hold-off protocol.
Workaround: PECI hosts can choose to either complete or not complete PECI transactions
when the processor goes beyond the hold-off limit. The processor generates
the PECI hold-off indication by keeping the PECI bus high when the PECI host
sends the first bit of the address timing negotiation phase. If the PECI host
does not choose to complete the transaction, it should consider the
transaction a failure and retry 1ms after the processor deactivates the hold-
off indication.
For the steppings affected, see the Summary Tables of Changes.
Status:
40
Errata
®
64 and IA-32
® ™
Intel Core 2 Duo Processor
Specification Update