Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 32

this practice as it may lead to undefined results. Software that needs to
implement memory aliasing should manage the memory type consistency.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW40. A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
Under certain conditions, as described in the Software Developers Manual
Problem:
section "Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon,
and P6 Family Processors", the processor may perform REP MOVS or REP
STOS as write combining stores (referred to as "fast strings") for optimal
performance. FXSAVE may also be internally implemented using write
combining stores. Due to this erratum, stores of a WB (write back) memory
type to a cache line previously written by a preceding fast string/FXSAVE
instruction may be observed before string/FXSAVE stores.
Implication: A write-back store may be observed before a previous string or FXSAVE
related store. Intel has not observed this erratum with any commercially
available software.
Workaround: Software desiring strict ordering of string/FXSAVE operations relative to
subsequent write-back stores should add an MFENCE or SFENCE instruction
between the string/FXSAVE operation and following store-order sensitive code
such as that used for synchronization.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW41. VM Exit with Exit Reason "TPR Below Threshold" Can Cause the
Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the
Guest Interruptibility-State Field
As specified in Section, "VM Exits Induced by the TPR Shadow", in the Intel®
Problem:
64 and IA-32 Architectures Software Developer's Manual, Volume 3B, a VM
exit occurs immediately after any VM entry performed with the "use TPR
shadow", "activate secondary controls", and "virtualize APIC accesses" VM-
execution controls all set to 1 and with the value of the TPR shadow (bits 7:4
in byte 80H of the virtual-APIC page) less than the TPR-threshold VM-
execution control field. Due to this erratum, such a VM exit will clear bit 0
(blocking by STI) and bit 1 (blocking by MOV/POP SS) of the interruptibility-
state field of the guest-state area of the VMCS (bit 0 - blocking by STI and bit
1 - blocking by MOV/POP SS should be left unmodified).
Implication: Since the STI, MOV SS, and POP SS instructions cannot modify the TPR
shadow, bits 1:0 of the interruptibility-state field will usually be zero before
any VM entry meeting the preconditions of this erratum; behavior is correct in
this case. However, if VMM software raises the value of the TPR-threshold VM-
execution control field above that of the TPR shadow while either of those bits
is 1, incorrect behavior may result. This may lead to VMM software
prematurely injecting an interrupt into a guest. Intel has not observed this
erratum with any commercially available software.
32
Errata
® ™
Intel Core 2 Duo Processor
Specification Update