Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 35

Errata
Implication: An instruction that should be overwritten by another instruction while in the
processor pipeline may not be detected/modified, and could retire without
detection. Alternatively the instruction may cause a Machine Check
Exception. Intel has not observed this erratum with any commercially
available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW47. Data TLB Eviction Condition in the Middle of a Cacheline Split Load
Operation May Cause the Processor to Hang
If the TLB translation gets evicted while completing a cacheline split load
Problem:
operation, under rare scenarios the processor may hang.
Implication: The cacheline split load operation may not be able to complete normally, and
the machine may hang and generate Machine Check Exception. Intel has not
observed this erratum with any commercially available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW48. Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P)
Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
Updating a page table entry by changing R/W, U/S or P bits, even when
Problem:
transitioning these bits from 0 to 1, without keeping the affected linear
address range coherent with all TLB (Translation Lookaside Buffers) and
paging-structures caches in the processor, in conjunction with a complex
sequence of internal processor micro-architectural events and store
operations, may lead to unexpected processor behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected processor
behavior. Intel has not observed this erratum with any commercially
available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW49. RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
RSM instruction execution, under certain conditions triggered by a complex
Problem:
sequence of internal processor micro-architectural events, may lead to
processor hang, or unexpected instruction execution results.
Implication: In the above sequence, the processor may live lock or hang, or RSM
instruction may restart the interrupted processor context through a
nondeterministic EIP offset in the code segment, resulting in unexpected
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Intel Core 2 Duo Processor
Specification Update 35