Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 12

NO
C0
AW61
AW62
AW63
AW64
AW65
AW66
AW67
AW68
AW69 X
AW70 X
AW71
AW72
AW73
AW74 X
AW75
AW76 X
AW77 X
AW78 X
AW79 X
AW80
Number
- There are no Specification Changes in this Specification Update revision.
12
M0 E0 R0 Plan
X X No Fix
X No Fix
X X No Fix
X X Plan Fix
X No Fix
X X No Fix
X X No Fix
X X No Fix
X X X No Fix
X X X No Fix
X X No Fix
X X No Fix
X X No Fix
X X X No Fix
X X Plan Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X No Fix
Summary Tables of Changes
ERRATA
Processor May Hold-off / Delay a PECI Transaction Longer
than Specified by the PECI Protocol
VM Entry May Use Wrong Address to Access Virtual-APIC
Page
XRSTOR Instruction May Cause Extra Memory Reads
CPUID Instruction May Return Incorrect Brand String
Global Instruction TLB Entries May Not be Invalidated on a
VM Exit or VM Entry
®
When Intel Deep Power-Down State is Being Used,
IA32_FIXED_CTR2 May Return Incorrect Cycle Counts
Enabling PECI via the PECI_CTL MSR incorrectly
writes CPUID_FEATURE_MASK1 MSR
INIT Incorrectly Resets IA32_LSTAR MSR
Corruption of CS Segment Register During RSM While
Transitioning From Real Mode to Protected Mode
LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
The XRSTOR Instruction May Fail to Cause a General-
Protection Exception
The XSAVE Instruction May Erroneously Set Reserved Bits
in the XSTATE_BV Field
Store Ordering Violation When Using XSAVE
Memory Ordering Violation With Stores/Loads Crossing a
Cacheline Boundary
Unsynchronized Cross-Modifying Code Operations Can
Cause Unexpected Instruction Execution Results
A Page Fault May Not be Generated When the PS bit is set
to "1" in a PML4E or PDPTE
Not-Present Page Faults May Set the RSVD Flag in the
Error Code
VM Exits Due to "NMI-Window Exiting" May Be Delayed by
One Instruction
FP Data Operand Pointer May Be Incorrectly Calculated
After an FP Access Which Wraps a 4-Gbyte Boundary in
Code That Uses 32-Bit Address Size in 64-bit Mode
VM Entry May Overwrite the Value for the IA32_DEBUGCTL
MSR Specified in the VM-Entry MSR-Load Area
SPECIFICATION CHANGES
® ™
Intel Core 2 Duo Processor
Specification Update