Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 43

Errata
For the steppings affected, see the Summary Tables of Changes.
Status:
AW69. Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
During the transition from real mode to protected mode, if an SMI (System
Problem:
Management Interrupt) occurs between the MOV to CR0 that sets
PE (Protection Enable, bit 0) and the first far JMP, the subsequent RSM
(Resume from System Management Mode) may cause the lower two bits of
CS segment register to be corrupted.
Implication: The corruption of the bottom two bits of the CS segment register will have no
impact unless software explicitly examines the CS segment register
between enabling protected mode and the first far JMP. Intel® 64 and IA-32
Architectures Software Developer's Manual Volume 3A: System Programming
Guide, Part 1, in the section titled "Switching to Protected Mode" recommends
the far JMP immediately follows the write to CR0 to enable protected
mode. Intel has not observed this erratum with any commercially available
software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW70. LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
An exception/interrupt event should be transparent to the LBR (Last Branch
Problem:
Record), BTS (Branch Trace Store) and BTM (Branch Trace Message)
mechanisms. However, during a specific boundary condition where the
exception/interrupt occurs right after the execution of an instruction at the
lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR
return registers will save a wrong return address with bits 63 to 48 incorrectly
sign extended to all 1's. Subsequent BTS and BTM operations which report
the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event of an
exception/interrupt.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW71. The XRSTOR Instruction May Fail to Cause a General-Protection
Exception
The XFEATURE_ENABLED_MASK register (XCR0) bits [63:9] are reserved and
Problem:
must be 0; consequently, the XRSTOR instruction should cause a general-
protection exception if any of the corresponding bits in the XSTATE_BV field
in the header of the XSAVE/XRSTOR area is set to 1. Due to this erratum, a
logical processor may fail to cause such an exception if one or more of these
reserved bits are set to 1.
® ™
Intel Core 2 Duo Processor
Specification Update 43