Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 24

For the steppings affected, see the Summary Tables of Changes.
Status:
AW18. Code Segment Limit/Canonical Faults on RSM May be Serviced before
Higher Priority Interrupts/Exceptions
Normally, when the processor encounters a Segment Limit or Canonical Fault
Problem:
due to code execution, a #GP (General Protection Exception) fault is
generated after all higher priority Interrupts and exceptions are serviced.
Due to this erratum, if RSM (Resume from System Management Mode)
returns to execution flow that results in a Code Segment Limit or Canonical
Fault, the #GP fault may be serviced before a higher priority Interrupt or
Exception (e.g. NMI (Non-Maskable Interrupt), Debug break(#DB), Machine
Check (#MC), etc.)
Implication: Operating systems may observe a #GP fault being serviced before higher
priority Interrupts and Exceptions. Intel has not observed this erratum on
any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW19. Store Ordering May be Incorrect between WC and WP Memory Types
According to Intel® 64 and IA-32 Intel Architecture Software Developer's
Problem:
Manual, Volume 3A "Methods of Caching Available", WP (Write Protected)
stores should drain the WC (Write Combining) buffers in the same way as UC
(Uncacheable) memory type stores do. Due to this erratum, WP stores may
not drain the WC buffers.
Implication: Memory ordering may be violated between WC and WP stores.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW20. EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown
When the processor is going into shutdown due to an RSM inconsistency
Problem:
failure, EFLAGS, CR0 and CR4 may be incorrect. In addition the EXF4 signal
may still be asserted. This may be observed if the processor is taken out of
shutdown by NMI#.
Implication: A processor that has been taken out of shutdown may have an incorrect
EFLAGS, CR0 and CR4. In addition the EXF4 signal may still be asserted.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
24
Errata
® ™
Intel Core 2 Duo Processor
Specification Update