Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 23

Errata
AW15. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
Under certain conditions as described in the Software Developers Manual
Problem:
section "Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon,
and P6 Family Processors" the processor performs REP MOVS or REP STOS as
fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions
that cross page boundaries from WB/WC memory types to UC/WP/WT
memory types, may start using an incorrect data size or may observe
memory ordering violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the
new page memory type:
• UC the data size of each write will now always be 8 bytes, as opposed to
the original data size.
• WP the data size of each write will now always be 8 bytes, as opposed to
the original data size and there may be a memory ordering violation.
• WT there may be a memory ordering violation.
Workaround: Software should avoid crossing page boundaries from WB or WC memory type
to UC, WP or WT memory type within a single REP MOVS or REP STOS
instruction that will execute with fast strings enabled.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW16. Upper 32 bits of 'From' Address Reported through BTMs or BTSs May
be Incorrect
When a far transfer switches the processor from 32-bit mode to IA-32e mode,
Problem:
the upper 32 bits of the 'From' (source) addresses reported through the BTMs
(Branch Trace Messages) or BTSs (Branch Trace Stores) may be incorrect.
Implication: The upper 32 bits of the 'From' address debug information reported through
BTMs or BTSs may be incorrect during this transition.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW17. Address Reported by Machine-Check Architecture (MCA) on Single-bit
L2 ECC Errors May be Incorrect
When correctable Single-bit ECC errors occur in the L2 cache, the address is
Problem:
logged in the MCA address register (MCi_ADDR). Under some scenarios, the
address reported may be incorrect.
Implication: Software should not rely on the value reported in MCi_ADDR, for Single-bit L2
ECC errors.
Workaround: None identified.
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Intel Core 2 Duo Processor
Specification Update 23