Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 9

Summary Tables of Changes
The Specification Updates for the Pentium
other Intel products do not use this convention.
NO
C0
AW1 X
AW2 X
AW3 X
AW4 X
AW5 X
AW6 X
AW7 X
AW8 X
AW9 X
AW10 X
AW11 X
AW12 X
AW13 X
AW14 X
AW15 X
AW16 X
AW17 X
AW18 X
AW19 X
® ™
Intel Core 2 Duo Processor
Specification Update
M0 E0 R0 Plan
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
X X X No Fix
®
processor, Pentium
ERRATA
EFLAGS Discrepancy on Page Faults after a Translation
Change
INVLPG Operation for Large (2M/4M) Pages May be
Incomplete under Certain Conditions
Store to WT Memory Data May be Seen in Wrong Order by
Two Subsequent Loads
Non-Temporal Data Store May be Observed in Wrong
Program Order
Page Access Bit May be Set Prior to Signaling a Code
Segment Limit Fault
Updating Code Page Directory Attributes without TLB
Invalidation May Result in Improper Handling of Code #PF
Storage of PEBS Record Delayed Following Execution of
MOV SS or STI
Performance Monitoring Event FP_MMX_TRANS_TO_MMX
May Not Count Some Transitions
A REP STOS/MOVS to a MONITOR/MWAIT Address Range
May Prevent Triggering of the Monitoring Hardware
Performance Monitoring Event MISALIGN_MEM_REF May
Over Count
The Processor May Report a #TS Instead of a #GP Fault
Code Segment limit violation may occur on 4 Gigabyte limit
check
A Write to an APIC Register Sometimes May Appear to
Have Not Occurred
Last Branch Records (LBR) Updates May be Incorrect after
a Task Switch
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types
may use an Incorrect Data Size or Lead to Memory-
Ordering Violations
Upper 32 bits of 'From' Address Reported through BTMs or
BTSs May be Incorrect
Address Reported by Machine-Check Architecture (MCA) on
Single-bit L2 ECC Errors May be Incorrect
Code Segment Limit/Canonical Faults on RSM May be
Serviced before Higher Priority Interrupts/Exceptions and
May Push the Wrong Address Onto the Stack
Store Ordering May be Incorrect between WC and WP
Memory Types
®
Pro processor, and
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