Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 44

Implication: Software may not operate correctly if it relies on the XRSTOR instruction to
cause a general-protection exception when any of the bits [63:9] in the
XSTATE_BV field in the header of the XSAVE/XRSTOR area is set to 1.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW72. The XSAVE Instruction May Erroneously Modify Reserved Bits in the
XSTATE_BV Field
Bits 63:2 of the HEADER.XSTATE_BV are reserved and must be 0. Due to this
Problem:
erratum, the XSAVE instruction may erroneously modify one or more of these
bits.
Implication: If one of bits 63:2 of the XSTATE_BV field in the header of the
XSAVE/XRSTOR area had been 1 and was then cleared by the XSAVE
instruction, a subsequent execution of XRSTOR may not generate the #GP
(general-protection exception) that would have occurred in the absence of
this erratum. Alternatively, if one of those bits had been 0 and was then set
by the XSAVE instruction, a subsequent execution of XRSTOR may generate a
#GP that would not have occurred in the absence of this erratum.
Workaround: It is possible for the BIOS to contain a partial workaround for this erratum
that prevents XSAVE from setting HEADER.XSTATE_BV reserved bits. To
ensure compatibility with future processors, software should not set any
XSTATE_BV reserved bits when configuring the header of the XSAVE/XRSTOR
save area.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW73. Store Ordering Violation When Using XSAVE
The store operations done as part of the XSAVE instruction may cause a store
Problem:
ordering violation with older store operations. The store operations done to
save the processor context in the XSAVE instruction flow , when XSAVE is
used to store only the SSE context, may appear to execute before the
completion of older store operations.
Implication: Execution of the stores in XSAVE, when XSAVE is used to store SSE context
only, may not follow program order and may execute before older stores.
Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW74. Memory Ordering Violation With Stores/Loads Crossing a Cacheline
Boundary
When two logical processors are accessing the same data that is crossing a
Problem:
cacheline boundary without serialization, with a specific set of processor
44
Errata
® ™
Intel Core 2 Duo Processor
Specification Update