Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 11

Summary Tables of Changes
NO
C0
AW40 X
AW41 X
AW42 X
AW43 X
AW44 X
AW45 X
AW46 X
AW47 X
AW48 X
AW49 X
AW50 X
AW51 X
AW52 X
AW53 X
AW54 X
AW55 X
AW56 X
AW57 X
AW58 X
AW59 X
AW60 X
® ™
Intel Core 2 Duo Processor
Specification Update
M0 E0 R0 Plan
X X X No Fix
Fixed
X X X No Fix
X No Fix
X Fixed
X Fixed
X Fixed
X Fixed
X Fixed
X Fixed
X X X No Fix
X X X Plan Fix
X X X No Fix
X X X No Fix
X X X No Fix
X No Fix
X No Fix
X X X No Fix
X X X Plan Fix
X X X No Fix
X X X No Fix
ERRATA
A WB Store Following a REP STOS/MOVS or FXSAVE May
Lead to Memory-Ordering Violations
VM Exit with Exit Reason "TPR Below Threshold" Can Cause
the Blocking by MOV/POP SS and Blocking by STI Bits to be
Cleared in the Guest Interruptibility-State Field
Using Memory Type Aliasing with cacheable and WC
Memory Types May Lead to Memory Ordering Violations
VM Exit Caused by a SIPI Results in Zero to be Saved to
the Guest RIP Field in the VMCS
NMIs May Not Be Blocked by a VM-Entry Failure
Partial Streaming Load Instruction Sequence May Cause
the Processor to Hang
Self/Cross Modifying Code May Not be Detected or May
Cause a Machine Check Exception
Data TLB Eviction Condition in the Middle of a Cacheline
Split Load Operation May Cause the Processor to Hang
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without TLB Shootdown May Cause
Unexpected Processor Behavior
RSM Instruction Execution under Certain Conditions May
Cause Processor Hang or Unexpected Instruction Execution
Results
Benign Exception after a Double Fault May Not Cause a
Triple Fault Shutdown
Short Nested Loops That Span Multiple 16-Byte Boundaries
May Cause a Machine Check Exception or a System Hang
An Enabled Debug Breakpoint or Single Step Trap May Be
Taken after MOV SS/POP SS Instruction if it is Followed by
an Instruction That Signals a Floating Point Exception
LER MSRs May be Incorrectly Updated
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine
Check Error Reporting Enable Correctly
A VM Exit Due to a Fault While Delivering a Software
Interrupt May Save Incorrect Data into the VMCS
A VM Exit Occuring in IA-32e Mode May Not Produce a VMX
Abort When Expected
IRET under Certain Conditions May Cause an Unexpected
Alignment Check Exception
PSI# Signal Asserted During Reset
Thermal Interrupts are Dropped During and While Exiting
®
Intel Deep Power-Down State
VM Entry May Fail When Attempting to Set
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN
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