Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 45

Errata
internal conditions, it is possible to have an ordering violation between
memory store and load operations.
Implication: Due to this erratum, proper load/store ordering may not be followed when
multiple logical processors are accessing the same data that crosses a
cacheline boundary without serialization.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW75. Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
The act of one processor, or system bus master, writing data into a currently
Problem:
executing code segment of a second processor with the intent of having the
second processor execute that data as code is called cross-modifying code
(XMC). XMC that does not force the second processor to execute a
synchronizing instruction, prior to execution of the new code, is called
unsynchronized XMC.
Software using unsynchronized XMC to modify the instruction byte stream of
a processor can see unexpected or unpredictable execution behavior from the
processor that is executing the modified code.
Implication: In this case, the phrase "unexpected or unpredictable execution behavior"
encompasses the generation of most of the exceptions listed in the Intel
Architecture Software Developer's Manual Volume 3: System Programming
Guide, including a General Protection Fault (GPF) or other unexpected
behaviors. In the event that unpredictable execution causes a GPF the
application executing the unsynchronized XMC operation would be terminated
by the operating system.
Workaround: In order to avoid this erratum, programmers should use the XMC
synchronization algorithm as detailed in the Intel Architecture Software
Developer's Manual Volume 3: System Programming Guide, Section: Handling
Self- and Cross-Modifying Code.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW76. A Page Fault May Not be Generated When the PS bit is set to "1" in a
PML4E or PDPTE
On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7)
Problem:
is reserved in PML4Es and PDPTEs. If the translation of the linear address of a
memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault
should occur. Due to this erratum, PS of such an entry is ignored and no page
fault will occur due to its being set.
Implication: Software may not operate properly if it relies on the processor to deliver page
faults when reserved bits are set in paging-structure entries.
® ™
Intel Core 2 Duo Processor
Specification Update 45