Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 39

Errata
code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum can
occur if the EFLAGS value on the stack has the AC flag set, and the interrupt
handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte
boundary before pushing the stack frame.
Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC
even if alignment checks are disabled at the start of the IRET. This erratum
can only be observed with a software generated stack frame.
Workaround: Software should not generate misaligned stack frames for use with IRET.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW58. PSI# Signal Asserted During Reset
Power Status Indicator (PSI) is a feature that, when available, may be used to
Problem:
enable voltage regulator power savings while idle and in the Deeper Sleep
State (C4 state). Under proper operation the processor will assert the PSI#
signal to indicate that the voltage regulator can enter a higher efficiency
mode of operation. The processor will incorrectly assert the PSI# signal while
the RESET# signal is asserted. This PSI# assertion will extend beyond the
deassertion of the RESET# signal for a short duration (maximum of one
millisecond).
Implication: When this erratum occurs on a platform designed to support PSI, the voltage
regulator will transition to mode of operation that may not be capable of
supplying the necessary voltage and current required by the processor.
Workaround: Do not use PSI# signal without blocking the assertion during the error period
as specified from RESET# assertion to a maximum of 1ms from the
deasserted edge.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW59. Thermal Interrupts are Dropped During and While Exiting Intel
Power-Down State
Thermal interrupts are ignored while the processor is in Intel Deep Power-
Problem:
Down State as well as during a small window of time while exiting from Intel
Deep Power-Down State. During this window, if the PROCHOT signal is driven
or the internal value of the sensor reaches the programmed thermal trip
point, then the associated thermal interrupt may be lost.
Implication: In the event of a thermal event while a processor is waking up from
Intel Deep Power-Down State, the processor will initiate an appropriate
throttle response. However, the associated thermal interrupt generated may
be lost.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
® ™
Intel Core 2 Duo Processor
Specification Update
®
Deep
39