Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 22

AW12. Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check
Code Segment limit violation may occur on 4 Gigabyte limit check when the
Problem:
code streamwraps around in a way that one instruction ends at the last byte
of the segment and the next instruction begins at 0x0.
Implication: This is a rare condition that may result in a system hang. Intel has not
observed this erratum with any commercially available software, or system.
Workaround: Avoid code that wraps around segment limit.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW13. A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
With respect to the retirement of instructions, stores to the uncacheable
Problem:
memory-based APIC register space are handled in a non-synchronized way.
For example if an instruction that masks the interrupt flag, e.g. CLI, is
executed soon after an uncacheable write to the Task Priority Register (TPR)
that lowers the APIC priority, the interrupt masking operation may take effect
before the actual priority has been lowered. This may cause interrupts whose
priority is lower than the initial TPR, but higher than the final TPR, to not be
serviced until the interrupt enabled flag is finally set, i.e. by STI instruction.
Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may
delay their service.
Workaround: This non-synchronization can be avoided by issuing an APIC register read
after the APIC register write. This will force the store to the APIC register
before any subsequent instructions are executed. No commercial operating
system is known to be impacted by this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW14. Last Branch Records (LBR) Updates May be Incorrect after a Task
Switch
A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM
Problem:
value to the LBR_TO value.
Implication: The LBR_FROM will have the incorrect address of the Branch Instruction.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
22
Errata
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Intel Core 2 Duo Processor
Specification Update