Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 29

Errata
Exposure to this problem requires the use of a data write which spans a cache
line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has not
observed this erratum with any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying
shared data by multiple agents:
• The shared data is aligned
• Proper semaphores or barriers are used in order to prevent concurrent
data accesses.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW32. General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
In 32-bit mode, memory accesses to flat data segments (base = 00000000h)
Problem:
that occur above the 4G limit (0ffffffffh) may not signal a #GP fault.
Implication: When such memory accesses occur in 32-bit mode, the system may not issue
a #GP fault.
Workaround: Software should ensure that memory accesses in 32-bit mode do not occur
above the 4G limit (0ffffffffh).
For the steppings affected, see the Summary Tables of Changes.
Status:
AW33. An Asynchronous MCE During a Far Transfer May Corrupt ESP
If an asynchronous machine check occurs during an interrupt, call through
Problem:
gate, FAR RET or IRET and in the presence of certain internal
conditions, ESP may be corrupted.
Implication: If the MCE (Machine Check Exception) handler is called without a stack
switch, then a triple fault will occur due to the corrupted stack pointer,
resulting in a processor shutdown. If the MCE is called with a stack switch,
e.g. when the CPL (Current Privilege Level) was changed or when going
through an interrupt task gate, then the corrupted ESP will be saved on the
new stack or in the TSS (Task State Segment), and will not be used.
Workaround: Use an interrupt task gate for the machine check handler.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW34. CPUID Reports Architectural Performance Monitoring Version 2 is
Supported, When Only Version 1 Capabilities are Available
CPUID leaf 0Ah reports the architectural performance monitoring version that
Problem:
is available in EAX[7:0]. Due to this erratum CPUID reports the supported
version as 2 instead of 1.
® ™
Intel Core 2 Duo Processor
Specification Update 29