Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 37

Errata
Implication: This can result in incorrect signaling of a debug exception and possibly a
mismatched Stack Segment and Stack Pointer. If MOV SS/POP SS is not
followed by a MOV [r/e]SP, [r/e]BP, there may be a mismatched Stack
Segment and Stack Pointer on any exception. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: As recommended in the IA32 Intel® Architecture Software Developer's
Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP
will avoid the failure since the MOV [r/e]SP, [r/e]BP will not generate a
floating point exception. Developers of debug tools should be aware of the
potential incorrect debug event signaling created by this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW53. LER MSRs May be Incorrectly Updated
The LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and
Problem:
MSR_LER_TO_LIP (1DEH) may contain incorrect values after any of the
following:
• Either STPCLK#, NMI (NonMaskable Interrupt) or external interrupts
• CMP or TEST instructions with an uncacheable memory operand
followed by a conditional jump
• STI/POP SS/MOV SS instructions followed by CMP or TEST instructions
and then by a conditional jump
Implication: When the conditions for this erratum occur, the value of the LER MSRs may
be incorrectly updated.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW54. IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error
Reporting Enable Correctly
IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to
Problem:
indicate whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at
the time of the last update to the IA32_MC1_STATUS MSR. Due to this
erratum, IA32_MC1_STATUS MSR bit[60] instead reports the current value of
the IA32_MC1_CTL MSR enable bit.
Implication: IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the
enable bit in the IA32_MC1_CTL MSR at the time of the last update.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
® ™
Intel Core 2 Duo Processor
Specification Update 37