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IDE Connectors
The pin assignments for the primary and secondary IDE connectors are listed in
the following table. The signals in parentheses are for the secondary connector.
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
4-10 System Board
IDE Interface Pin Assignments
Signal Name
Reset IDE
Host Data 7
Host Data 6
Host Data 5
Host Data 4
Host Data 3
Host Data 2
Host Data 1
Host Data 0
Ground
DRQ0 (DRQ1)
I/O Write-
I/O Read-
IOCHRDY
DDACKO (DDACK1)
IRQ14 (IRQ15)
Addr 1
Addr 0
Chip Select 1
Activity-
Pin
Signal Assignment
2
Ground
4
Host Data 8
6
Host Data 9
8
Host Data 10
10
Host Data 11
12
Host Data 12
14
Host Data 13
16
Host Data 14
18
Host Data 15
20
Key
22
Ground
24
Ground
26
Ground
28
IDE_CSEL
30
Ground
32
No Connection
34
No Connection
36
Addr 2
38
Chip Select 3P (3S)
40
Ground
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