I/O Headers - Infineon EVAL PMG1 S3 DUALDR User Manual

EVAL_PMG1_S3_DUALDRP Evaluation Kit user guide
EVAL_PMG1_S3_DUALDRP kit system design
3.3

I/O headers

The EVK has four I/O headers; all GPIOs, PD-specific function signals, regulator output, and other power signals
are routed to these headers.
V3P3
VDDIO_IN
GND
CC1_P0
CC2_P0
P1.1
P1.2
RESET
P2.2
P2.3
P1.5
P2.0
P3.1
P4.0
P4.1
P3.5
P3.6
P3.3
P5.1
P3.0
P5.0
P3.7
P2.1
P3.4
P0.4
P0.5
P0.6
P0.7
P6.3
P6.2
P3.2
V5P0
NC
GND
Figure 11 EVK I/O headers
I/O header pinout at J6
EVK EVK pin name
pin J6
1 V3P3
2 VDDIO_IN
3 GND
4 CC1_P0
5 CC2_P0
6 P1.1/SWD_CLK
User guide
PMG1-S3 Primary function Secondary
MCU pin
- 3.3 V regulator
output
- VDDIO external
input
- -
N14, N15 Port 0 CC1 signal
J14, J15 Port 0 CC2 signal
P3 SWD clock
function
External 3.3 V
regulator
input to board
-
-
-
-
P1.1 (GPIO)
18
GND
GND
NC
VSYS
P2.6
P6.1
P6.0
P0.3
P5.2
P7.5
P5.5
P2.7
P2.5
P1.4
P0.0
P0.1
P7.0
P7.1
P7.2
P7.3
P7.4
P1.3
P1.0
P5.4
P7.6
P2.4
P1.6
P0.2
P5.3
CC2_P1
CC1_P1
GND
VDDA_IN
VDDD
Connection details
Connected to power and
CAPSENSE™ LEDs
Connected through the non-
populated resistor/diode
Connected to ground
Connected to Type-C Port 0
CC1 channel
Connected to Type-C Port 0
CC2 channel
Connected to KitProg3
002-38187 Rev. *B
2024-09-23