Infineon EVAL PMG1 S3 DUALDR User Manual page 19

EVAL_PMG1_S3_DUALDRP Evaluation Kit user guide
EVAL_PMG1_S3_DUALDRP kit system design
EVK EVK pin name
pin J6
7 P1.2/SWD_IO
8 RESET
9 P2.2/REG_I2C_SDA
10 P2.3/REG_I2C_SCL
11 P1.5/REG_EN_P0
12 P2.0/REG_INT_P0
13 P3.1
14 P4.0/I2C_SCL
15 P4.1/I2C_SDA
16 P3.5/UART_RX
17 P3.6/UART_TX
I/O header pinout at J13
EVK EVK pin name
pin
J13
1 P3.3
2 P5.1/CMOD
3 P3.0
4 P5.0/CTANK
5 P3.7
6 P2.1/
VBUS_C_CTRL_P0
7 P3.4
8 P0.4/DBG2_P0
9 P0.5/DBG1_P0
10 P0.6/LSTX_P0
User guide
PMG1-S3 Primary function Secondary
MCU pin
R3 SWD data
E14 Reset signal
A3 PD regulator I2C
data line
B5 PD regulator I2C
clock line
M12 Port 0 PD
regulator enable
signal
A2 Port 0 PD
regulator
interrupt signal
B3 User LED 1
E15 I2C clock signal
D12 I2C data signal
F4 UART RX
E2 UART TX
PMG1-S3 Primary function
MCU pin
B1 User switch signal
E1 CAPSENSE™
capacitor
A1 P3.0 (GPIO)
G2 CAPSENSE™
capacitor output
C1 P3.7 (GPIO)
B2 Port 0 VBUS
consumer FET
control signal
D4 P3.4 (GPIO)
P8 -
M8 -
R9 -
function
P1.2 (GPIO)
-
P2.2 (GPIO)
P2.3 (GPIO)
P1.5 (GPIO)
P2.0 (GPIO)
P3.1 (GPIO)
P4.0 (GPIO)
P4.1 (GPIO)
P3.5 (GPIO)
P3.6 (GPIO)
Secondary
function
P3.3 (GPIO)
P5.1 (GPIO)
-
P5.0 (GPIO)
-
P2.1 (GPIO)
-
P0.4 (GPIO)
P0.5 (GPIO)
P0.6 (GPIO)
19
Connection details
Connected to KitProg3
Connected to SW2 and
KitProg3 Reset
Connected to PD regulator
I2C data line
Connected to PD regulator
I2C clock line
Connected to Port 0 PD
regulator enable pin
Connected to Port 0 PD
regulator interrupt pin
Connected to LED3
Connected to KitProg3 for
USB to I2C bridge
Connected to KitProg3 for
USB to I2C bridge
Connected to KitProg3
UART by default
Connected to KitProg3
UART by default
Connection details
Connected to SW3
Connected to CAPSENSE™
capacitor
Connected to VREF bypass
capacitor for 12-bit SAR ADC
CTANK capacitor connected
through no-load resistor
-
Connected to Port 0
consumer path NFET gate
-
-
-
-
002-38187 Rev. *B
2024-09-23