Infineon EVAL PMG1 S3 DUALDR User Manual page 24

EVAL_PMG1_S3_DUALDRP Evaluation Kit user guide
EVAL_PMG1_S3_DUALDRP kit system design
Pin# Pin name
3 GND
4 I2C_SCL
5 RESET
6 I2C_SDA
7 SWDCLK
8 UART_RX
9 SWDIO
10 UART_TX
The EVK also has a 10-pin SWD/JTAG header (J8) for programming and debugging. The header is
pin-compatible with all the standard 10-pin SWD/JTAG interfaces and supports Infineon's MiniProg4 program
and debug kit.
RESET GND
NC GND
NC GND
SWDCLK GND
SWDIO
VTARG
Figure 13 SWD/JTAG header
SWD header (J8) pinout
Pin# Pin name
1 VTARG
2 SWDIO
3 GND
4 SWDCLK
User guide
Description
Ground
I2C SCL signal between KitProg3 and EZ-PD™ PMG1-S3 MCU
Reset signal for programming EZ-PD™ PMG1-S3 MCU
I2C SDA signal
SWD clock
UART Rx
SWD data
UART Tx
Description
Target (EZ-PD™ PMG1-S3 MCU) internal regulator output
SWD data
Ground
SWD clock
24 002-38187 Rev. *B
2024-09-23