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User manual for MERUS™ evaluation boards
EVAL_AUDIO_MA12070_B and EVAL_AUDIO_MA12070P_B
Setup guide
Table 3
I
2
C address decoding (ADD)
I
C device address
2
0x20
0x21
0x22
2.2
Notes to digital audio and analog audio headers
When using the "digital audio header" for digital I
appear as follows (from top to bottom, left side of the header):
SCK: Word clock; also known as bit clock
•
WS: Word select; also known as left right clock (LRCLK)
•
SD0: Multiplexed data line 0 containing two digital input stream channels
•
SD1: Multiplexed data line 1 containing two digital input stream channels
•
MCLK: Master clock (typically 256 x fs)
•
When using analog input, the board has been set up to initially evaluate with an unbalanced input source (see
"analog audio header", jumpers connected). However, for full system performance evaluation it is
recommended to apply a balanced analog input signal. This can be done by removing the four jumpers from
the "analog input header" and connecting the analog balanced input signal as follows (from top to bottom, left
side of the header):
CH0 input in0a (+)
•
CH0 input in0b (-)
•
CH1 input in1a (+)
•
CH1 input in1b (-)
•
User Manual
AD0
L
L
H
S input stream (MA12070P), the connection scheme should
2
AD1
L
H
L
8 of 23
7-bit I
C address
2
0b0100000
0b0100010
0b0100001
V 1.0
2023-03-02
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