NEC VRC4172 mPD31172 User Manual
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NEC VRC4172 mPD31172 User Manual

NEC VRC4172 mPD31172 User Manual

Companion chip for vr4121
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User's Manual
V
4172™
RC
Companion Chip for V
µ µ µ µ PD31172
Document No. U14386EJ3V0UM00 (3rd edition)
Date Published September 2000 N CP(K)
©
1999
2000
Printed in Japan
4121™
R

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Summary of Contents for NEC VRC4172 mPD31172

  • Page 1 User’s Manual 4172™ Companion Chip for V 4121™ µ µ µ µ PD31172 Document No. U14386EJ3V0UM00 (3rd edition) Date Published September 2000 N CP(K) © 1999 2000 Printed in Japan...
  • Page 2 [MEMO] User’s Manual U14386EJ3V0UM00...
  • Page 3 Reset operation must be executed immediately after power-on for devices having reset function. 4121 and V 4172 are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries.
  • Page 4 NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.
  • Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
  • Page 6 Major Revisions in This Edition Page Description µPD31172 Change of development status (under development → development Throughout completed) p. 48 Modification of description in 3.2.2 (4) Revision ID register (offset address: 0x08) p. 124 Modification of description in 11.2.2 Command register (offset address: 0x04) p.
  • Page 7 INTRODUCTION This manual is intended for users who wish to understand the functions of the Target Readers 4172 and develop application systems using this chip. Purpose This manual is intended to give users an understanding of the architecture of the 4172, using the following organization.
  • Page 8 4172) Data Sheet U14388E 4121 User’s Manual U13569E µ PD30121 (V 4121) Data Sheet U14691E • USB-related documents (These documents are not handled by NEC.) OPEN HCI Specification Release 1.0 • PCI Local bus Specification Revision 2.1 • User’s Manual U14386EJ3V0UM00...

  • Page 9: Table Of Contents

    CONTENTS CHAPTER 1 OVERVIEW ........................17 Features............................17 Ordering Information ........................ 17 4172 Processor........................18 1.3.1 Internal block configuration ......................19 1.3.2 Registers of each unit........................20 CHAPTER 2 PIN FUNCTIONS ......................25 Pin Configuration ........................25 List of Pin Functions......................... 29 2.2.1 System bus interface signals......................
  • Page 10 4.1.12 EXGPINTTYP1 (0x1500 10C8) .....................65 4.1.13 EXGPINTLV1L (0x1500 10CA) .....................66 CHAPTER 5 PCS (PROGRAMMABLE CHIP SELECT) ..............67 Register Set..........................67 5.1.1 EXCS compare address registers ....................68 5.1.2 EXCS address mask registers.......................70 CHAPTER 6 PWM CONTROLLER......................73 Register Set..........................73 6.1.1 LCDDUTYEN (0x1500 3880)......................74 6.1.2...
  • Page 11 10.1.1 RBR (0x1500 3810: LCR7 = 0, during read) ................106 10.1.2 THR (0x1500 3810: LCR7 = 0, during write) ................106 10.1.3 DLL (0x1500 3810: LCR7 = 1) ....................107 10.1.4 IER (0x1500 3812: LCR7 = 0) ..................... 108 10.1.5 DLM (0x1500 3812: LCR7 = 1) ....................
  • Page 12 12.1.1 PS2DATA (0x1500 3870) ......................166 12.1.2 PS2CTRL (0x1500 3872) ......................167 12.2 Transmit Procedure......................... 168 CHAPTER 13 CONNECTION WITH V 4121..................169 13.1 Load Reduction Buffer Control ....................169 13.2 Cautions When Connecting Load Reduction Buffer............170 CHAPTER 14 INTERRUPT SIGNALS ....................171 CHAPTER 15 RESET..........................
  • Page 13 LIST OF FIGURES Figure No. Title Page Internal Block Diagram and External Block Connection Example ..............18 Physical Address Space..........................39 11-1 USB Host Control Configuration Space....................... 122 12-1 Data Pattern ..............................166 13-1 Example of SYSDIR Signal (V 4121) Circuit When Using Load Reduction Buffer........169 User’s Manual U14386EJ3V0UM00...
  • Page 14 LIST OF TABLES (1/2) Table No. Title Page PCI Configuration Cycle Registers ........................20 PCI Host Control Registers..........................20 GPIO Registers .............................20 PCS Registers ...............................21 PWM Registers..............................21 PMU Registers ..............................22 ICU Registers ..............................22 Parallel Control Registers ..........................22 Serial Control Registers..........................23 1-10 USB Host Control Configuration Registers ....................23 1-11 Host Control Operational Registers .......................24 1-12...
  • Page 15 LIST OF TABLES (2/2) Table No. Title Page Parallel Control Registers..........................92 10-1 Serial Control Registers ..........................105 10-2 Relationship Between Baud Rate and Divisor ..................... 110 10-3 Interrupt Set/Reset ............................112 11-1 USB Host Control Configuration Registers....................123 11-2 Host Control Operational Registers......................
  • Page 16 [MEMO] User’s Manual U14386EJ3V0UM00...

  • Page 17: Chapter 1 Overview

    4172 ( µ PD31172). This chapter gives an overview of the V 1.1 Features The V 4172 is a companion chip for NEC’s V 4121 microprocessor. The V 4172 features on chip a USB host controller, IEEE1284 parallel controller, 16550 serial controller, PS/2 controller, general-purpose ports (GPIO), programmable chip select function (PCS), and PWM controller (duty modulation pulse generation function for LCD backlights).

  • Page 18: Vrc 4172 Processor

    CHAPTER 1 OVERVIEW 1.3 V 4172 Processor Figure 1-1 shows the internal block diagram of the V 4172 and an example of connection with external components. Figure 1-1. Internal Block Diagram and External Block Connection Example 4172 48 MHz DRAM controller USB host controller host controller...

  • Page 19: Internal Block Configuration

    CHAPTER 1 OVERVIEW 1.3.1 Internal block configuration (1) PCI host controller The PCI host controller controls access from the system bus to the USB host controller. Access to the USB host controller is done using the PCI bus. For this reason, the PCI host controller contains PCI configuration registers (PCI host control register).

  • Page 20: Registers Of Each Unit

    CHAPTER 1 OVERVIEW 1.3.2 Registers of each unit The registers of the various units are listed below. Table 1-1. PCI Configuration Cycle Registers Name Register Address PCI configuration address register 0x0AFF 0CF8 PCI configuration data register 0x0AFF 0CFC Table 1-2. PCI Host Control Registers Name Offset Address Vendor ID register...
  • Page 21 CHAPTER 1 OVERVIEW Table 1-4. PCS Registers Symbol Function Register Address EXCS0SELL EXCS0# compare address lower register 0x1500 1090 EXCS0SELH EXCS0# compare address higher register 0x1500 1092 EXCS0MSKL EXCS0# compare address mask lower & enable register 0x1500 1094 EXCS0MSKH EXCS0# compare address mask higher register 0x1500 1096 EXCS1SELL EXCS1# compare address lower register...
  • Page 22 CHAPTER 1 OVERVIEW Table 1-6. PMU Registers Symbol Function Register Address SYSCLKCTRL SYSCLK enable register 0x1500 3800 1284CTRL 1284 parallel clock/reset control register 0x1500 3802 16550CTRL 16550 serial clock/reset control register 0x1500 3804 USBCTRL USB clock control register 0x1500 380C PS2PWMCTRL PS/2, PWM clock/reset control register 0x1500 380E...
  • Page 23 CHAPTER 1 OVERVIEW Table 1-9. Serial Control Registers Symbol Function Register Address Receive buffer register 0x1500 3810 Transmit hold register Divide ratio lower register Interrupt enable register 0x1500 3812 Divide ratio higher register Interrupt display register 0x1500 3814 FIFO control register Line control register 0x1500 3816 Modem control register...
  • Page 24 CHAPTER 1 OVERVIEW Table 1-11. Host Control Operational Registers Symbol Function Offset Address HcRevision HC revision register 0x00 HcControl HC control register 0x04 HcCommandStatus HC command status register 0x08 HcInterruptStatus HC interrupt status register 0x0C HcInterruptEnable HC interrupt enable register 0x10 HcInterruptDisable HC interrupt disable register...

  • Page 25: Chapter 2 Pin Functions

    CHAPTER 2 PIN FUNCTIONS 2.1 Pin Configuration • 208-pin plastic FBGA (15 × 15) Top View Bottom View U T R P N M L K J H G F E D C B A A B C D E F G H J K L M N P R T U Index mark User’s Manual U14386EJ3V0UM00...
  • Page 26 CHAPTER 2 PIN FUNCTIONS Name Name Name Name STROBE# GPIO14 AUTOFEED# ACK# PPON1 GPIO10 ERROR# OCI2 GPIO7 INIT# USBRST# GPIO3 IOCHRDY GPIO22 EXCS3# AD19 GPIO18 EXCS0# AD20 SCAS# AD21 SRAS# AD22 AD10 SCLK GPIO13 AD23 AD11 PPON2 GPIO9 AD24 LCDBAK LCAS# GPIO6 Note 1...
  • Page 27 CHAPTER 2 PIN FUNCTIONS Name Name Name Name DATA31 DATA23 DATA30 DATA22 IOR# DATA29 DATA15 IOW# DATA28 DATA21 DATA14 DATA20 DATA7 DATA27 DATA13 DATA6 DATA26 DATA19 DATA12 DATA5 DATA25 DATA18 DATA11 DATA4 DATA24 DATA10 DATA3 CLKOUT48M DATA17 DATA2 DCD# DATA16 DATA9 DATA1 CTS#...
  • Page 28 CHAPTER 2 PIN FUNCTIONS Pin Names ACK#: Acknowledge MRAS (0:1)#: DRAM Row Address Strobe AD (0:24): Address Bus OCI (1:2): Over Current Interrupt ARBCLKSEL: Arbitration Clock Select Paper End AUTOFEED#: Autofeed PPON (1:2): Port Power ON BUSAK (0:1)#: Bus Acknowledge PS2CLK: PS2 Clock BUSCLK:...

  • Page 29: List Of Pin Functions

    CHAPTER 2 PIN FUNCTIONS 2.2 List of Pin Functions 2.2.1 System bus interface signals These signals are used when the V 4121 and SDRAM are connected. Table 2-1. System Bus Interface Signals (1/2) Signal Name Function SCLK SDRAM operation clock AD (0:24) 25-bit address bus DATA (0:31)

  • Page 30: Usb Interface Signals

    CHAPTER 2 PIN FUNCTIONS Table 2-1. System Bus Interface Signals (2/2) Signal Name Function INTRP Interrupt request signal from 16550 serial controller or IEEE1284 parallel controller Interrupt request signal from general-purpose port (GPIO (0:23)) or IEEE1284 parallel controller USBINT# Interrupt request signal from USB host controller PS2INT Interrupt request signal from PS/2 controller BUSCLK...

  • Page 31: Rs-232-C Interface Signals

    CHAPTER 2 PIN FUNCTIONS 2.2.4 RS-232-C interface signals These signals are used during data transmit/receive with the V 4172 and RS-232-C controller. Table 2-4. RS-232-C Interface Signals Signal Name Function Receive data signal CTS# Transmit enable signal DSR# Data set ready signal Transmit data signal RTS# Transmit request signal...

  • Page 32: Clock Signals

    CHAPTER 2 PIN FUNCTIONS 2.2.9 Clock signals These signals are used to supply clocks. Table 2-9. Clock Signals Signal Name Function XIN48M 48 MHz oscillator input pin. One side of a crystal resonator is connected. XOUT48M 48 MHz oscillator output pin. One side of a crystal resonator is connected. CLKOUT48M 48 MHz clock output for FIR of the V 4121...

  • Page 33: Pin Statuses

    CHAPTER 2 PIN FUNCTIONS 2.3 Pin Statuses 2.3.1 Status of pins under specific conditions Table 2-10 lists the statuses of pins after the V 4172 is reset and when HOLDAK# = 1. Table 2-10. Statuses of Pins Under Specific Conditions (1/2) Signal Name After Reset When HOLDAK# = 1...
  • Page 34 CHAPTER 2 PIN FUNCTIONS Table 2-10. Statuses of Pins Under Specific Conditions (2/2) Signal Name After Reset When HOLDAK# = 1 DN (1:2) Normal operation PPON (1:2) Normal operation OCI (1:2) — — — — WAKE Normal operation SMI# Normal operation USBRST# —...

  • Page 35: External Processing Of Pins And Drive Performance

    CHAPTER 2 PIN FUNCTIONS 2.3.2 External processing of pins and drive performance Table 2-11 lists the external processing of pins and their drive performance. Table 2-11. External Processing of Pins and Drive Performance (1/2) Signal Name External Processing Drive Performance Withstand Voltage SCLK —...
  • Page 36 CHAPTER 2 PIN FUNCTIONS Table 2-11. External Processing of Pins and Drive Performance (2/2) Signal Name External Processing Drive Performance Withstand Voltage ARBCLKSEL — — DP (1:2) — Note DN (1:2) — Note PPON (1:2) — 40 pF OCI (1:2) —...

  • Page 37: Recommended Connection Of Unused Pins

    CHAPTER 2 PIN FUNCTIONS 2.3.3 Recommended connection of unused pins Table 2-12 shows the recommended connection of unused pins. Table 2-12. Recommended Connection of Unused Pins Signal Name Recommended Signal Name Recommended Connection Connection SCLK Pull up PPON (1:2) Leave open AD (0:24) —...
  • Page 38 [MEMO] User’s Manual U14386EJ3V0UM00...

  • Page 39: Chapter 3 Address Map

    CHAPTER 3 ADDRESS MAP The V 4121 has a 4 GB physical address space. Access to the resources in the V 4172 is done via the LCD area and the ISA I/O area. The USB host controller in the V 4172 accesses the DRAM area via the internal PCI bus and the DRAM controller.

  • Page 40: Internal I/O Spaces

    CHAPTER 3 ADDRESS MAP 3.1 Internal I/O Spaces These spaces are used to access internal I/O resources of the V 4172 such as the IEEE1284 parallel controller, 16550 serial controller, PS/2 controller, PWM controller, GPIO (general-purpose I/O port), and PCS (programmable chip select).

  • Page 41: Pci Master Window (Memory)

    CHAPTER 3 ADDRESS MAP 3.2 PCI Master Window (Memory) This space is used to issue memory access and the PCI configuration cycle to the internal PCI bus in the V 4172. The address range can be changed, and the start address bits (23:16) are specified with the memory base address register bits (23:16) of the PCI configuration space.
  • Page 42 CHAPTER 3 ADDRESS MAP (1) PCI configuration address register (0x0AFF 0CF8) (1/2) Bit Position Bit name Config EN After reset Bit Position Bit name Number7 Number6 Number5 Number4 Number3 Number2 Number1 Number0 After reset Bit Position Bit name Device Device Device Device Device...
  • Page 43 CHAPTER 3 ADDRESS MAP (2/2) Bit Position Bit Name Function Register Number Specification of register to be accessed (5:0) Input the higher 6 bits excluding the lower 2 bits of the register address. For the register addresses, refer to Table 3-3 PCI Host Control Registers and Table 11-1 USB Host Control Configuration Registers.
  • Page 44 CHAPTER 3 ADDRESS MAP (2) PCI configuration data register (0x0AFF 0CFC) Bit Position Bit name Data31 Data30 Data29 Data28 Data27 Data26 Data25 Data24 After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name Data23 Data22 Data21 Data20 Data19 Data18...

  • Page 45: Pci Host Controller

    CHAPTER 3 ADDRESS MAP 3.2.2 PCI host controller The PCI host controller controls access from the system bus to the USB host controller. The internal PCI bus is used for access to the USB host controller. For this reason, this controller contains PCI configuration registers (PCI host control registers).
  • Page 46 Vender Vender ID15 ID14 ID13 ID12 ID11 ID10 After reset Bit Position Bit name Vender Vender Vender Vender Vender Vender Vender Vender After reset Bit Position Bit Name Function 15:0 Vender ID (15:0) Vendor ID 0x1033: NEC User’s Manual U14386EJ3V0UM00...
  • Page 47 CHAPTER 3 ADDRESS MAP (2) Command register (offset address: 0x04) Bit Position Bit name PCIRSTGO PCLKSTOP After reset Bit Position Bit name Memory I/OCycle CycleEN After reset Bit Position Bit Name Function PCIRSTGO A PCI reset pulse is issued at the rising edge of this bit. PCLKSTOP PCI clock 1: Disable...
  • Page 48 CHAPTER 3 ADDRESS MAP (3) Status register (offset address: 0x06) Bit Position Bit name Received Received Master Target Abort Abort After reset Bit Position Bit name After reset Bit Position Bit Name Function 15:14 Reserved. Write 0. 0 returned when read. ReceivedMaster When this bit is 1, this indicates that the PCI host controller has acknowledged that the Abort...
  • Page 49 CHAPTER 3 ADDRESS MAP (5) Memory base address register (offset address: 0x10 to 12) Bit Position Bit name MBAR31 MBAR30 MBAR29 MBAR28 MBAR27 MBAR26 MBAR25 MBAR24 After reset Bit Position Bit name MBAR23 MBAR22 MBAR21 MBAR20 MBAR19 MBAR18 MBAR17 MBAR16 After reset Bit Position Bit name...
  • Page 50 CHAPTER 3 ADDRESS MAP (6) Control register (offset address: 0x50) (1/2) Bit Position Bit name SIZE32 SIZE31 SIZE30 SIZE22 SIZE21 SIZE20 After reset Bit Position Bit name SIZE12 SIZE11 SIZE10 SIZE02 SIZE01 SIZE00 After reset Bit Position Bit name PCICLK PCICLK DIV1 DIV0...
  • Page 51 CHAPTER 3 ADDRESS MAP (2/2) Bit Position Bit Name Function PCICLKDIV (1:0) PCI clock divide ratio 11: RFU 10: 48 MHz/1.5 01: 48 MHz/2 00: 48 MHz/3 Reserved. Write 0. 0 returned when read. EXTM64 Same value as EXT_DRAM64 bit of BCUCNTREG3 register of V 4121.

  • Page 52: Pci Master Window (I/O)

    CHAPTER 3 ADDRESS MAP 3.3 PCI Master Window (I/O) This space is used to issue I/O access to the internal PCI bus in the V 4172. The address range is fixed to the 64 KB area from 0x0AFF0000 to 0x0AFF FFFF. When this space is accessed, an address consisting of the lower 16 bits of the system bus address padded with 0s to form a 32-bit address is generated and I/O access is issued to the internal PCI bus.

  • Page 53: Chapter 4 Gpio (General-Purpose I/O Port)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) GPIO controls the GPIO pins. The GPIO pins are 24 general-purpose ports that support both input and output. Interrupt request signal input functions can be allocated to these ports, and 5 triggers can be selected: input signal changes (rising edge, falling edge, both edges), low level, and high level.

  • Page 54: Exgpdata0 (0X1500 1080)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.1 EXGPDATA0 (0x1500 1080) Bit Position Bit name EXPD15 EXPD14 EXPD13 EXPD12 EXPD11 EXPD10 EXPD9 EXPD8 After reset Bit Position Bit name EXPD7 EXPD6 EXPD5 EXPD4 EXPD3 EXPD2 EXPD1 EXPD0 After reset Bit Position Bit Name Function 15:0...

  • Page 55: Exgpdir0 (0X1500 1082)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.2 EXGPDIR0 (0x1500 1082) Bit Position Bit name EXPDR15 EXPDR14 EXPDR13 EXPDR12 EXPDR11 EXPDR10 EXPDR9 EXPDR8 After reset Bit Position Bit name EXPDR7 EXPDR6 EXPDR5 EXPDR4 EXPDR3 EXPDR2 EXPDR1 EXPDR0 After reset Bit Position Bit Name Function 15:0...

  • Page 56: Exgpinten0 (0X1500 1084)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.3 EXGPINTEN0 (0x1500 1084) Bit Position Bit name EXPIE15 EXPIE14 EXPIE13 EXPIE12 EXPIE11 EXPIE10 EXPIE9 EXPIE8 After reset Bit Position Bit name EXPIE7 EXPIE6 EXPIE5 EXPIE4 EXPIE3 EXPIE2 EXPIE1 EXPIE0 After reset Bit Position Bit Name Function 15:0...

  • Page 57: Exgpintst0 (0X1500 1086)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.4 EXGPINTST0 (0x1500 1086) Bit Position Bit name EXPIS15 EXPIS14 EXPIS13 EXPIS12 EXPIS11 EXPIS10 EXPIS9 EXPIS8 After reset Bit Position Bit name EXPIS7 EXPIS6 EXPIS5 EXPIS4 EXPIS3 EXPIS2 EXPIS1 EXPIS0 After reset Bit Position Bit Name Function 15:0...

  • Page 58: Exgpinttyp0 (0X1500 1088)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.5 EXGPINTTYP0 (0x1500 1088) Bit Position Bit name EXPIT15 EXPIT14 EXPIT13 EXPIT12 EXPIT11 EXPIT10 EXPIT9 EXPIT8 After reset Bit Position Bit name EXPIT7 EXPIT6 EXPIT5 EXPIT4 EXPIT3 EXPIT2 EXPIT1 EXPIT0 After reset Bit Position Bit Name Function 15:0...

  • Page 59: Exgpintlv0L (0X1500 108A)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.6 EXGPINTLV0L (0x1500 108A) Bit Position Bit name EXPIB7 EXPIB6 EXPIB5 EXPIB4 EXPIB3 EXPIB2 EXPIB1 EXPIB0 After reset Bit Position Bit name EXPIL7 EXPIL6 EXPIL5 EXPIL4 EXPIL3 EXPIL2 EXPIL1 EXPIL0 After reset Bit Position Bit Name Function 15:8...

  • Page 60: Exgpintlv0H (0X1500 108C)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.7 EXGPINTLV0H (0x1500 108C) Bit Position Bit name EXPIB15 EXPIB14 EXPIB13 EXPIB12 EXPIB11 EXPIB10 EXPIB9 EXPIB8 After reset Bit Position Bit name EXPIL15 EXPIL14 EXPIL13 EXPIL12 EXPIL11 EXPIL10 EXPIL9 EXPIL8 After reset Bit Position Bit Name Function 15:8...

  • Page 61: Exgpdata1 (0X1500 10C0)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.8 EXGPDATA1 (0x1500 10C0) Bit Position Bit name After reset Bit Position Bit name EXPD23 EXPD22 EXPD21 EXPD20 EXPD19 EXPD18 EXPD17 EXPD16 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. EXPD (23:16) Specification of GPIO (23:16) pin output data 1: High level...

  • Page 62: Exgpdir1 (0X1500 10C2)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.9 EXGPDIR1 (0x1500 10C2) Bit Position Bit name After reset Bit Position Bit name EXPDR7 EXPDR6 EXPDR5 EXPDR4 EXPDR3 EXPDR2 EXPDR1 EXPDR0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. EXPDR (7:0) Selection of GPIO (23:16) pin input/output 1: Output...

  • Page 63: Exgpinten1 (0X1500 10C4)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.10 EXGPINTEN1 (0x1500 10C4) Bit Position Bit name After reset Bit Position Bit name EXPIE23 EXPIE22 EXPIE21 EXPIE20 EXPIE19 EXPIE18 EXPIE17 EXPIE16 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. EXPIE (23:16) Enable detection of interrupts to GPIO (23:16) pins 1: Enable...

  • Page 64: Exgpintst1 (0X1500 10C6)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.11 EXGPINTST1 (0x1500 10C6) Bit Position Bit name After reset Bit Position Bit name EXPIS23 EXPIS22 EXPIS21 EXPIS20 EXPIS19 EXPIS18 EXPIS17 EXPIS16 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. EXPIS (23:16) Interrupt request to GPIO (23:16) pins During read...

  • Page 65: Exgpinttyp1 (0X1500 10C8)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.12 EXGPINTTYP1 (0x1500 10C8) Bit Position Bit name After reset Bit Position Bit name EXPIT23 EXPIT22 EXPIT21 EXPIT20 EXPIT19 EXPIT18 EXPIT17 EXPIT16 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. EXPIT (23:16) Interrupt request detection trigger for GPIO (23:16) pins 1: Edge...

  • Page 66: Exgpintlv1L (0X1500 10Ca)

    CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT) 4.1.13 EXGPINTLV1L (0x1500 10CA) Bit Position Bit name EXPIB23 EXPIB22 EXPIB21 EXPIB20 EXPIB19 EXPIB18 EXPIB17 EXPIB16 After reset Bit Position Bit name EXPIL23 EXPIL22 EXPIL21 EXPIL20 EXPIL19 EXPIL18 EXPIL17 EXPIL16 After reset Bit Position Bit Name Function 15:8...

  • Page 67: Chapter 5 Pcs (Programmable Chip Select)

    CHAPTER 5 PCS (PROGRAMMABLE CHIP SELECT) PCS compares the addresses set to the register with the addresses on the system bus and generates the EXCS (5:0)# signals. The EXCS (5:0)# signals are low level when the addresses match. There are 6 EXCS (5:0)# signals, and the addresses to be compared can freely be set for each.

  • Page 68: Excs Compare Address Registers

    CHAPTER 5 PCS (PROGRAMMABLE CHIP SELECT) 5.1.1 EXCS compare address registers (1) EXCSnSELL (0x1500 1090, 1098, 10A0, 10A8, 10B0, 10B8) Bit Position Bit name CSnA15 CSnA14 CSnA13 CSnA12 CSnA11 CSnA10 CSnA9 CSnA8 After reset Bit Position Bit name CSnA7 CSnA6 CSnA5 CSnA4 CSnA3...
  • Page 69 CHAPTER 5 PCS (PROGRAMMABLE CHIP SELECT) Remarks 1. n = 0 to 5 2. The correspondence between the EXCS (5:0)# pins and their registers is shown in the following table. Pin Name EXCSnSELL EXCSnSELH EXCS0# EXCS0SELL (0x1500 1090) EXCS0SELH (0x1500 1092) EXCS1# EXCS1SELL (0x1500 1098) EXCS1SELH (0x1500 109A)

  • Page 70: Excs Address Mask Registers

    CHAPTER 5 PCS (PROGRAMMABLE CHIP SELECT) 5.1.2 EXCS address mask registers (1) EXCSnMSKL (0x1500 1094, 109C, 10A4, 10AC, 10B4, 10BC) Bit Position Bit name CSnM15 CSnM14 CSnM13 CSnM12 CSnM11 CSnM10 CSnM9 CSnM8 After reset Bit Position Bit name CSnM7 CSnM6 CSnM5 CSnM4 CSnM3...
  • Page 71 CHAPTER 5 PCS (PROGRAMMABLE CHIP SELECT) Remarks 1. n = 0 to 5 2. The correspondence between the EXCS (5:0)# pins and their registers is shown in the following table. Pin Name EXCSnMSKL EXCSnMSKH EXCS0# EXCS0MSKL (0x1500 1094) EXCS0MSKH (0x1500 1096) EXCS1# EXCS1MSKL (0x1500 109C) EXCS1MSKH (0x1500 109E)
  • Page 72 [MEMO] User’s Manual U14386EJV0UM00...

  • Page 73: Chapter 6 Pwm Controller

    CHAPTER 6 PWM CONTROLLER The PWM controller controls the frequency and duty of the LCD backlight modulation pulse. 6.1 Register Set Table 6-1 lists the PWM registers. Table 6-1. PWM Registers Address Symbol Function 0x1500 3880 LCDDUTYEN LCDBAK enable register 0x1500 3882 LCDFREQ LCDBAK frequency register...

  • Page 74: Lcddutyen (0X1500 3880)

    CHAPTER 6 PWM CONTROLLER 6.1.1 LCDDUTYEN (0x1500 3880) Bit Position Bit name After reset Bit Position Bit name LCDEN After reset Bit Position Bit Name Function 15:1 Reserved. Write 0. 0 returned when read. LCDEN LCDBAK signal control enable 1: Enable 0: Disable This register enables/disables duty control.

  • Page 75: Lcdfreq (0X1500 3882)

    CHAPTER 6 PWM CONTROLLER 6.1.2 LCDFREQ (0x1500 3882) Bit Position Bit name After reset Bit Position Bit name FREQD7 FREQD6 FREQD5 FREQD4 FREQD3 FREQD2 FREQD1 FREQD0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 1. 1 returned when read. FREQD (7:0) LCDBAK signal frequency setting This register sets the frequency of the LCDBAK signal.

  • Page 76: Lcdduty (0X1500 3884)

    CHAPTER 6 PWM CONTROLLER 6.1.3 LCDDUTY (0x1500 3884) Bit Position Bit name After reset Bit Position Bit name DUTY5 DUTY4 DUTY3 DUTY2 DUTY1 DUTY0 After reset Bit Position Bit Name Function 15:6 Reserved. Write 0. 0 returned when read. DUTY (5:0) LCDBAK signal duty setting (high-level width) This register sets the LCDBAK signal duty (high-level width).

  • Page 77: Chapter 7 Pmu (Power Management Unit)

    CHAPTER 7 PMU (POWER MANAGEMENT UNIT) The PMU controls the clock supply and reset for the IEEE1284 parallel controller, 16550 serial controller, PS/2 controller, PWM controller, and USB host controller. It also performs enable/disable settings for the internal oscillator (48 MHz). 7.1 Register Set Table 7-1 lists the PMU registers.

  • Page 78: Sysclkctrl (0X1500 3800)

    CHAPTER 7 PMU (POWER MANAGEMENT UNIT) 7.1.1 SYSCLKCTRL (0x1500 3800) Bit Position Bit name After reset Bit Position Bit name IRST OSCEN CKO48 After reset Bit Position Bit Name Function 15:6 Reserved. Write 0. 0 returned when read. IRST Internal reset control 1: Reset start 0: Reset cancel OSCEN...

  • Page 79: 1284Ctrl (0X1500 3802)

    CHAPTER 7 PMU (POWER MANAGEMENT UNIT) 7.1.2 1284CTRL (0x1500 3802) Bit Position Bit name After reset Bit Position Bit name 1284USE 1284RST 1284CLK After reset Bit Position Bit Name Function 15:3 Reserved. Write 0. 0 returned when read. 1284USE Use of IEEE1284 parallel controller 1: Use 0: Do not use 1284RST...

  • Page 80: 16550Ctrl (0X1500 3804)

    CHAPTER 7 PMU (POWER MANAGEMENT UNIT) 7.1.3 16550CTRL (0x1500 3804) Bit Position Bit name After reset Bit Position Bit name SIORST SIOCLK After reset Bit Position Bit Name Function 15:2 Reserved. Write 0. 0 returned when read. SIORST Reset of 16550 serial controller 1: Reset start 0: Reset cancel SIOCLK...

  • Page 81: Usbctrl (0X1500 380C)

    CHAPTER 7 PMU (POWER MANAGEMENT UNIT) 7.1.4 USBCTRL (0x1500 380C) Bit Position Bit name After reset Bit Position Bit name USBCLK After reset Bit Position Bit Name Function 15:1 Reserved. Write 0. 0 returned when read. USBCLK Control of clock to USB host controller 1.

  • Page 82: Ps2Pwmctrl (0X1500 380E)

    CHAPTER 7 PMU (POWER MANAGEMENT UNIT) 7.1.5 PS2PWMCTRL (0x1500 380E) Bit Position Bit name After reset Bit Position Bit name PWMCLK PS2RST PS2CLK After reset Bit Position Bit Name Function 15:5 Reserved. Write 0. 0 returned when read. PWMCLK PWM clock control 1.

  • Page 83: Clock Supply

    CHAPTER 7 PMU (POWER MANAGEMENT UNIT) 7.2 Clock Supply Next, the clock supply procedure is described. (1) At power-on 1. Input 0 to the RESET pin while the RESET signal is high level and the USBRST# signal is low level (reset cancel).
  • Page 84 CHAPTER 7 PMU (POWER MANAGEMENT UNIT) If 1 is input to the ARBCLKSEL pin and the internal clock (48 MHz clock divided by 6) is used for system bus arbitration, the arbitration function is also stopped when the 48 MHz clock is stopped. When 0 is input to the BUSRQ (0:1)# pins immediately before the 48 MHz clock is stopped, the V 4172 sets the HOLDRQ# signal to 0 and requests the bus to the V...

  • Page 85: Chapter 8 Icu (Interrupt Control Unit)

    CHAPTER 8 ICU (INTERRUPT CONTROL UNIT) The ICU controls interrupts to the IEEE1284 parallel controller and the 16550 serial controller. For details on the GPIO interrupts, refer to CHAPTER 4 GPIO (GENERAL-PURPOSE I/O PORT), and for details on the USB interrupts, refer to CHAPTER 11 USB HOST CONTROLLER. 8.1 Register Set Table 8-1 lists the ICU registers.

  • Page 86: 1284Intrq (0X1500 3808)

    CHAPTER 8 ICU (INTERRUPT CONTROL UNIT) 8.1.1 1284INTRQ (0x1500 3808) Bit Position Bit name After reset Bit Position Bit name MASK3 MASK2 THRU LATCH After reset Undefined Bit Position Bit Name Function 15:4 Reserved. Write 0. 0 returned when read. MASK3 Interrupt mask (IRQ pin) 1: Output interrupt to IRQ pin.

  • Page 87: 16550Intrq (0X1500 380A)

    CHAPTER 8 ICU (INTERRUPT CONTROL UNIT) 8.1.2 16550INTRQ (0x1500 380A) Bit Position Bit name After reset Bit Position Bit name THRU LATCH After reset Undefined Bit Position Bit Name Function 15:2 Reserved. Write 0. 0 returned when read. THRU Serial controller interrupt status (through, read only) 1: Interrupt occurrence 0: No interrupt LATCH...
  • Page 88 [MEMO] User’s Manual U14386EJ3V0UM00...

  • Page 89: Chapter 9 Ieee1284 Parallel Controller

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER This controller is a parallel interface (host controller) that complies with IEEE1284. This controller uses the NBH1284L core macro. 9.1 Macro Functions The NBH1284L macro provides 7 types of macro modes, which are selected by writing to the MODE (2:0) bits of the ECR register (refer to 9.2.14 ECR (0x1500 3834)).
  • Page 90 CHAPTER 9 IEEE1284 PARALLEL CONTROLLER Table 9-1. Macro Mode Functions (2/2) Macro ECR Register Function Mode MODE (2:0) Bits EPP mode Normal direction and reverse direction transfers using the EPPA register and the EPPD register are possible. Normal direction transfer using the DATA register like in the STD mode is also possible (FIFO is not reset).
  • Page 91 CHAPTER 9 IEEE1284 PARALLEL CONTROLLER Furthermore, whether compatible, nibble, byte, ECP, and EPP transfer mode, which are set in IEEE1284, can be used is determined by the macro mode. Table 9-2 shows the relationships between the macro modes and the IEEE1284 transfer mode.

  • Page 92: Register Set

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2 Register Set Table 9-3 lists the parallel control registers. Table 9-3. Parallel Control Registers Address MODE (2:0) Symbol Function 0x1500 3820 001, 100 DATA Parallel port data register 000, 001, 100 DATA Parallel port data register AFIFO ECP address FIFO 0x1500 3822...

  • Page 93: Data (0X1500 3820: Mode (2:0) = 001, 100, Dir = 1, During Read)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.1 DATA (0x1500 3820: MODE (2:0) = 001, 100, DIR = 1, during read) Bit Position Bit name After reset Bit Position Bit name DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 After reset Bit Position Bit Name Function 15:8...

  • Page 94: Afifo (0X1500 3820: Mode (2:0) = 011, Dir = 0, During Write)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.3 AFIFO (0x1500 3820: MODE (2:0) = 011, DIR = 0, during write) Bit Position Bit name After reset Bit Position Bit name DTYPE AFIFO6 AFIFO5 AFIFO4 AFIFO3 AFIFO2 AFIFO1 AFIFO0 After reset Bit Position Bit Name Function 15:8...

  • Page 95: Dsr (0X1500 3822)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.4 DSR (0x1500 3822) Bit Position Bit name After reset Bit Position Bit name nBusy nAck PError Select nFault After reset Undefined Undefined Undefined Undefined Undefined Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. nBusy BUSY pin status 1: Low level...

  • Page 96: Dcr (0X1500 3824)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.5 DCR (0x1500 3824) Bit Position Bit name After reset Bit Position Bit name acklntEN Selectln nlnit autofd strobe After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. Reserved. Write 1. 1 returned when read. Transfer direction 1: External device →...

  • Page 97: Mcr (0X1500 3826: Mode (2:0) = 000, 001)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.6 MCR (0x1500 3826: MODE (2:0) = 000, 001) Bit Position Bit name After reset Bit Position Bit name eppM After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. eppM EPP mode setting 1: EPP1.9 mode...

  • Page 98: Eppa (0X1500 3826: Mode (2:0) = 100)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.7 EPPA (0x1500 3826: MODE (2:0) = 100) Bit Position Bit name After reset Bit Position Bit name eppA7 eppA6 eppA5 eppA4 eppA3 eppA2 eppA1 eppA0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. eppA (7:0) Transmit/receive data in EPP mode (address) This register stores transfer data in the EPP mode.

  • Page 99: Eppd (0X1500 3828: Mode (2:0) = 100)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.8 EPPD (0x1500 3828: MODE (2:0) = 100) Bit Position Bit name After reset Bit Position Bit name eppD7 eppD6 eppD5 eppD4 eppD3 eppD2 eppD1 eppD0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. eppD (7:0) Transmit/receive data in EPP mode (data) This register stores transmit/receive data in the EPP mode.

  • Page 100: Dfifo (0X1500 3830: Mode (2:0) = 011)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.10 DFIFO (0x1500 3830: MODE (2:0) = 011) Bit Position Bit name After reset Bit Position Bit name DFIFO7 DFIFO6 DFIFO5 DFIFO4 DFIFO3 DFIFO2 DFIFO1 DFIFO0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. DFIFO (7:0) Transmit/receive data in ECP mode This register stores transmit/receive data in the ECP mode.

  • Page 101: Tfifo (0X1500 3830: Mode (2:0) = 110)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.11 TFIFO (0x1500 3830: MODE (2:0) = 110) Bit Position Bit name After reset Bit Position Bit name TFIFO7 TFIFO6 TFIFO5 TFIFO4 TFIFO3 TFIFO2 TFIFO1 TFIFO0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. TFIFO (7:0) Data stored to FIFO in TEST mode This register is used to view the FIFO configuration.

  • Page 102: Cnfga (0X1500 3830: Mode (2:0) = 111)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.12 CNFGA (0x1500 3830: MODE (2:0) = 111) Bit Position Bit name After reset Bit Position Bit name ISALVL impID2 impID1 impID0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. ISALVL Interrupt level setting 1: Level...

  • Page 103: Cnfgb (0X1500 3832: Mode (2:0) = 111)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.13 CNFGB (0x1500 3832: MODE (2:0) = 111) Bit Position Bit name After reset Bit Position Bit name compress intrValue intrLine2 intrLine1 intrLine0 After reset Undefined Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. compress Support of compressed data from peripheral in ECP mode 1: Support...

  • Page 104: Ecr (0X1500 3834)

    CHAPTER 9 IEEE1284 PARALLEL CONTROLLER 9.2.14 ECR (0x1500 3834) Bit Position Bit name After reset Bit Position Bit name MODE2 MODE1 MODE0 nErIntEn dmaEn serviceInt full empty After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. MODE (2:0) Operation mode setting 111: CNFIG (Config) mode...

  • Page 105: Chapter 10 16550 Serial Controller

    CHAPTER 10 16550 SERIAL CONTROLLER The 16550 serial controller is a serial interface that supports RS-232-C compliant communication. It provides 1 channel each for transmit and receive. This serial controller is functionally compatible with the NS16550D. 10.1 Register Set Table 10-1 lists the serial control registers. Table 10-1.

  • Page 106: Rbr (0X1500 3810: Lcr7 = 0, During Read)

    CHAPTER 10 16550 SERIAL CONTROLLER 10.1.1 RBR (0x1500 3810: LCR7 = 0, during read) Bit Position Bit name After reset Bit Position Bit name RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 After reset Bit Position Bit Name Function 15:8 Reserved.

  • Page 107: Dll (0X1500 3810: Lcr7 = 1)

    CHAPTER 10 16550 SERIAL CONTROLLER 10.1.3 DLL (0x1500 3810: LCR7 = 1) Bit Position Bit name After reset Bit Position Bit name DLL7 DLL6 DLL5 DLL4 DLL3 DLL2 DLL1 DLL0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. DLL (7:0) Baud rate divisor (lower byte) This register sets the baud rate generator divisor (divide ratio).

  • Page 108: Ier (0X1500 3812: Lcr7 = 0)

    CHAPTER 10 16550 SERIAL CONTROLLER 10.1.4 IER (0x1500 3812: LCR7 = 0) Bit Position Bit name After reset Bit Position Bit name After reset Bit Position Bit Name Function 15:4 Reserved. Write 0. 0 returned when read. Modem status interrupt 1: Enable 0: Disable Receive status interrupt...

  • Page 109: Dlm (0X1500 3812: Lcr7 = 1)

    CHAPTER 10 16550 SERIAL CONTROLLER 10.1.5 DLM (0x1500 3812: LCR7 = 1) Bit Position Bit name After reset Bit Position Bit name DLM7 DLM6 DLM5 DLM4 DLM3 DLM2 DLM1 DLM0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. DLM (7:0) Baud rate divisor (higher byte) This register sets the baud rate generator divisor (divide ratio).
  • Page 110 CHAPTER 10 16550 SERIAL CONTROLLER Table 10-2. Relationship Between Baud Rate and Divisor Note Error Percentage Baud Rate Divisor 2304 1536 1047 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 Note Error percentage for baud rate User’s Manual U14386EJ3V0UM00...

  • Page 111: Iir (0X1500 3814: During Read)

    CHAPTER 10 16550 SERIAL CONTROLLER 10.1.6 IIR (0x1500 3814: during read) Bit Position Bit name After reset Bit Position Bit name IIR7 IIR6 IIR3 IIR2 IIR1 IIR0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. IIR (7:6) 11 when the FCR0 bit of the FCR register is 1 (always set to 0 in 16450 mode) Reserved.
  • Page 112 CHAPTER 10 16550 SERIAL CONTROLLER Table 10-3. Interrupt Set/Reset IIR Register Interrupt Set/Reset Function Bit 3 Bit 2 Bit 1 Priority Interrupt Type Interrupt Source Interrupt Reset Note Order Control Receive line Overrun error, parity error, framing Line status register priority status error, or break...

  • Page 113: Fcr (0X1500 3814: During Write)

    CHAPTER 10 16550 SERIAL CONTROLLER 10.1.7 FCR (0x1500 3814: during write) Bit Position Bit name After reset Bit Position Bit name FCR7 FCR6 FCR3 FCR2 FCR1 FCR0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. FCR (7:6) Receive FIFO trigger 11: 14 bytes...

  • Page 114: Lcr (0X1500 3816)

    CHAPTER 10 16550 SERIAL CONTROLLER 10.1.8 LCR (0x1500 3816) Bit Position Bit name After reset Bit Position Bit name LCR7 LCR6 LCR5 LCR4 LCR3 LCR2 LCR1 LCR0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. LCR7 Register switch when divisor latch address 1: Divisor latch register...

  • Page 115: Mcr (0X1500 3818)

    CHAPTER 10 16550 SERIAL CONTROLLER 10.1.9 MCR (0x1500 3818) Bit Position Bit name After reset Bit Position Bit name MCR4 MCR3 MCR2 MCR1 MCR0 After reset Bit Position Bit Name Function 15:5 Reserved. Write 0. 0 returned when read. MCR4 Diagnosis test (local loopback) use 1: RFU 0: Disable...

  • Page 116: Lsr (0X1500 381A)

    CHAPTER 10 16550 SERIAL CONTROLLER 10.1.10 LSR (0x1500 381A) Bit Position Bit name After reset Bit Position Bit name LSR7 LSR6 LSR5 LSR4 LSR3 LSR2 LSR1 LSR0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. LSR7 Detection of various types of errors (in FIFO (16550) mode) 1: Parity error, framing error, break detection...
  • Page 117 CHAPTER 10 16550 SERIAL CONTROLLER This register is used for CPU to obtain information regarding data transfer. When the LSR7 and LSR (4:1) bits are set to 1, they are cleared to 0 when this register is read. The LSR7 bit is valid only in the FIFO (16550) mode. It is always 0 in the 16450 mode. The LSR4 bit becomes 1 when the receive data input is in spacing status (0) for longer than the transmit time of 1 word (start bit + data bit + parity bit + stop bit) (break).

  • Page 118: Msr (0X1500 381C)

    CHAPTER 10 16550 SERIAL CONTROLLER 10.1.11 MSR (0x1500 381C) Bit Position Bit name After reset Bit Position Bit name MSR7 MSR6 MSR5 MSR4 MSR3 MSR2 MSR1 MSR0 After reset Undefined Undefined Undefined Undefined Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. MSR7 DCD# signal status 1: Low level...

  • Page 119: Scr (0X1500 381E)

    CHAPTER 10 16550 SERIAL CONTROLLER 10.1.12 SCR (0x1500 381E) Bit Position Bit name After reset Bit Position Bit name SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 After reset Bit Position Bit Name Function 15:8 Reserved. Write 0. 0 returned when read. SCR (7:0) General-purpose data This register is a read- and write-enabled 8-bit register that can be used freely by the user.
  • Page 120 [MEMO] User’s Manual U14386EJ3V0UM00...

  • Page 121: Chapter 11 Usb Host Controller

    CHAPTER 11 USB HOST CONTROLLER The USB host controller conforms with OPEN HCI Specification Release 1.0. This controller supports power management such as the clock stop function on the PCI/USB side. It also provides two downstream ports. However, it does not support legacy functions. 11.1 Features The features of the USB host controller are shown below.

  • Page 122: Usb Host Control Configuration Registers

    CHAPTER 11 USB HOST CONTROLLER 11.2 USB Host Control Configuration Registers In the case of the PCI local bus (internal PCI bus in the V 4172), the USB host control configuration registers are accessed to set the hardware resources used by devices and the characteristics and operation of devices. Each register is accessed with the PCI configuration cycle.

  • Page 123: Register Set

    Table 11-1. USB Host Control Configuration Registers Offset Name Reset Value Contents Address 0x00 Vendor ID register 15:0 0x1033 NEC vendor ID 0x02 Device ID register 31:16 0x0000 Device ID of this macro 0x04 Command register 15:0 0x0000 Refer to 11.2.2 Refer to 11.2.3...

  • Page 124: Command Register (Offset Address: 0X04)

    CHAPTER 11 USB HOST CONTROLLER 11.2.2 Command register (offset address: 0x04) Position Bit name Fast back- SERR# to-back enable enable After reset Position Bit name Wait cycle Parity Memory Special Memory I/O space control Error palette write and Cycles Master space response snoop...

  • Page 125: Status Register (Offset Address: 0X06)

    CHAPTER 11 USB HOST CONTROLLER 11.2.3 Status register (offset address: 0x06) (1/2) Bit Position Bit name Detected Signaled Received Received Signal DEVSEL DEVSEL Data parity system master target target timing timing Parity error error abort abort abort Error detected After reset Bit Position Bit name Fast back-...
  • Page 126 CHAPTER 11 USB HOST CONTROLLER (2/2) Bit Position Bit Name Function Fast back-to-back capable Response to fast back-to-back access Fixed to 0 (disabled). UDF support UDF is not supported. 66 MHz capable 33 MHz operation Reserved. Write 0. 0 returned when read. User’s Manual U14386EJ3V0UM00...

  • Page 127: Base Address Register (Offset Address: 0X10)

    CHAPTER 11 USB HOST CONTROLLER 11.2.4 Base address register (offset address: 0x10) Bit Position Bit name Base Base Base Base Base Base Base Base address address address address address address address address (MSB) (MSB) (MSB) (MSB) (MSB) (MSB) (MSB) (MSB) After reset Bit Position Bit name...

  • Page 128: Power Management Control/Status Register (Offset Address: 0Xe0)

    CHAPTER 11 USB HOST CONTROLLER 11.2.5 Power management control/status register (offset address: 0xE0) (1/2) Bit Position Bit name After reset Bit Position Bit name Wakeup_ Enable After reset Bit Position Bit name Wakeup_ Status After reset Bit Position Bit name ID Write PC_mode REQ_...
  • Page 129 CHAPTER 11 USB HOST CONTROLLER (2/2) Bit Position Bit Name Function REQ_Enable REQ signal (internal PCI bus signal) output timing control 1: PCICLK (internal clock) asynchronous output 0: PCICLK synchronous output Reserved. Write 0. 0 returned when read. Status Change Standby Device status regarding power status change control 1: Supported 0: Not supported...

  • Page 130: Operational Registers

    CHAPTER 11 USB HOST CONTROLLER 11.3 Operational Registers The USB host controller (HC) contains operational registers, which serve as the windows for communicating with the host CPU. These registers are mapped to a 4 KB space in the 4 GB main memory space of the system, and they are used by the host controller driver (HCD).

  • Page 131: Hcrevision (Offset Address: 0X00)

    CHAPTER 11 USB HOST CONTROLLER 11.3.2 HcRevision (offset address: 0x00) Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined...

  • Page 132: Hccontrol (Offset Address: 0X04)

    CHAPTER 11 USB HOST CONTROLLER 11.3.3 HcControl (offset address: 0x04) (1/2) Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined...
  • Page 133 CHAPTER 11 USB HOST CONTROLLER (2/2) Bit Position Bit Name Function Interrupt Routing Routing of interrupt request generated by event registered in the HcInterruptStatus register 1: SMI# signal output 0: USBINT# signal output HCFS Host Controller Functional Status for USB USB operation mode 11: UsbSuspend 10: UsbOperational...

  • Page 134: Hccommandstatus (Offset Address: 0X08)

    CHAPTER 11 USB HOST CONTROLLER 11.3.4 HcCommandStatus (offset address: 0x08) (1/2) Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined...
  • Page 135 CHAPTER 11 USB HOST CONTROLLER (2/2) Bit Position Bit Name Function Control List Filled Existence of TD in control list 1: Yes 0: No Host Controller Reset HC software reset Set to 1 by HCD, cleared to 0 by HC User’s Manual U14386EJ3V0UM00...

  • Page 136: Hcinterruptstatus (Offset Address: 0X0C)

    CHAPTER 11 USB HOST CONTROLLER 11.3.5 HcInterruptStatus (offset address: 0x0C) (1/2) Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined...
  • Page 137 CHAPTER 11 USB HOST CONTROLLER (2/2) Bit Position Bit Name Function Unrecoverable Error Detection of system error not related to USB 1: Detected 0: Normal Resume Detected Detection of Resume signal 1: Detected 0: Normal Start of Frame This bit is set at the start of a frame. It is cleared by writing 0 to it. Writeback Done Head This bit is set when the contents of the HcDoneHead register are written to Note...

  • Page 138: Hcinterruptenable (Offset Address: 0X10)

    CHAPTER 11 USB HOST CONTROLLER 11.3.6 HcInterruptEnable (offset address: 0x10) (1/2) Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined...
  • Page 139 CHAPTER 11 USB HOST CONTROLLER (2/2) Bit Position Bit Name Function Frame Number Overflow Interrupt request with Frame Number Overflow 1: Enable 0: Disable Unrecoverable Error Interrupt request with Unrecoverable Error 1: Enable 0: Disable Resume Detected Interrupt request with Resume Detect 1: Enable 0: Disable Start of Frame...

  • Page 140: Hcinterruptdisable (Offset Address: 0X14)

    CHAPTER 11 USB HOST CONTROLLER 11.3.7 HcInterruptDisable (offset address: 0x14) (1/2) Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined...
  • Page 141 CHAPTER 11 USB HOST CONTROLLER (2/2) Bit Position Bit Name Function Unrecoverable Error Interrupt request with Unrecoverable Error 1: Disable Resume Detected Interrupt request with Resume Detect 1: Disable Start of Frame Interrupt request with Start of Frame 1: Disable Writeback Done Head Interrupt request with HcDoneHead Writeback 1: Disable...

  • Page 142: Hchcca (Offset Address: 0X18)

    CHAPTER 11 USB HOST CONTROLLER 11.3.8 HcHCCA (offset address: 0x18) Bit Position Bit name HCCA HCCA HCCA HCCA HCCA HCCA HCCA HCCA R/W (HCD) R/W (HC) After reset Bit Position Bit name HCCA HCCA HCCA HCCA HCCA HCCA HCCA HCCA R/W (HCD) R/W (HC) After reset...

  • Page 143: Hcperiodcurrented (Offset Address: 0X1C)

    CHAPTER 11 USB HOST CONTROLLER 11.3.9 HcPeriodCurrentED (offset address: 0x1C) Bit Position Bit name PCED PCED PCED PCED PCED PCED PCED PCED R/W (HCD) R/W (HC) After reset Bit Position Bit name PCED PCED PCED PCED PCED PCED PCED PCED R/W (HCD) R/W (HC) After reset...

  • Page 144: Hccontrolheaded (Offset Address: 0X20)

    CHAPTER 11 USB HOST CONTROLLER 11.3.10 HcControlHeadED (offset address: 0x20) Bit Position Bit name CHED CHED CHED CHED CHED CHED CHED CHED R/W (HCD) R/W (HC) After reset Bit Position Bit name CHED CHED CHED CHED CHED CHED CHED CHED R/W (HCD) R/W (HC) After reset...

  • Page 145: Hccontrolcurrented (Offset Address: 0X24)

    CHAPTER 11 USB HOST CONTROLLER 11.3.11 HcControlCurrentED (offset address: 0x24) Bit Position Bit name CCED CCED CCED CCED CCED CCED CCED CCED R/W (HCD) R/W (HC) After reset Bit Position Bit name CCED CCED CCED CCED CCED CCED CCED CCED R/W (HCD) R/W (HC) After reset...

  • Page 146: Hcbulkheaded (Offset Address: 0X28)

    CHAPTER 11 USB HOST CONTROLLER 11.3.12 HcBulkHeadED (offset address: 0x28) Bit Position Bit name BHED BHED BHED BHED BHED BHED BHED BHED R/W (HCD) R/W (HC) After reset Bit Position Bit name BHED BHED BHED BHED BHED BHED BHED BHED R/W (HCD) R/W (HC) After reset...

  • Page 147: Hcbulkcurrented (Offset Address: 0X2C)

    CHAPTER 11 USB HOST CONTROLLER 11.3.13 HcBulkCurrentED (offset address: 0x2C) Bit Position Bit name BCED BCED BCED BCED BCED BCED BCED BCED R/W (HCD) R/W (HC) After reset Bit Position Bit name BCED BCED BCED BCED BCED BCED BCED BCED R/W (HCD) R/W (HC) After reset...

  • Page 148: Hcdonehead (Offset Address: 0X30)

    CHAPTER 11 USB HOST CONTROLLER 11.3.14 HcDoneHead (offset address: 0x30) Bit Position Bit name R/W (HCD) R/W (HC) After reset Bit Position Bit name R/W (HCD) R/W (HC) After reset Bit Position Bit name R/W (HCD) R/W (HC) After reset Bit Position Bit name R/W (HCD)

  • Page 149: Hcfminterval (Offset Address: 0X34)

    CHAPTER 11 USB HOST CONTROLLER 11.3.15 HcFmInterval (offset address: 0x34) Bit Position Bit name FSMPS FSMPS FSMPS FSMPS FSMPS FSMPS FSMPS R/W (HCD) R/W (HC) After reset Bit Position Bit name FSMPS FSMPS FSMPS FSMPS FSMPS FSMPS FSMPS FSMPS R/W (HCD) R/W (HC) After reset Bit Position...

  • Page 150: Hcfmremaining (Offset Address: 0X38)

    CHAPTER 11 USB HOST CONTROLLER 11.3.16 HcFmRemaining (offset address: 0x38) Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined...

  • Page 151: Hcfmnumber (Offset Address: 0X3C)

    CHAPTER 11 USB HOST CONTROLLER 11.3.17 HcFmNumber (offset address: 0x3C) Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined...

  • Page 152: Hcperiodicstart (Offset Address: 0X40)

    CHAPTER 11 USB HOST CONTROLLER 11.3.18 HcPeriodicStart (offset address: 0x40) Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined...

  • Page 153: Hclsthreshold (Offset Address: 0X44)

    CHAPTER 11 USB HOST CONTROLLER 11.3.19 HcLSThreshold (offset address: 0x44) Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name R/W (HCD) R/W (HC) After reset Undefined Undefined Undefined Undefined Undefined...

  • Page 154: Hcrhdescriptora (Offset Address: 0X48)

    CHAPTER 11 USB HOST CONTROLLER 11.3.20 HcRhDescriptorA (offset address: 0x48) (1/2) Bit Position Bit name POTPGT POTPGT POTPGT POTPGT POTPGT POTPGT POTPGT POTPGT R/W (HCD) R/W (HC) Note Note Note Note Note Note Note Note After reset Bit Position Bit name R/W (HCD) R/W (HC) After reset...
  • Page 155 CHAPTER 11 USB HOST CONTROLLER (2/2) Bit Position Bit Name Function Device Type Indicates that the root hub is not a composite device. No Power Switching Power application switching 1: Always apply power to ports when HC is ON. 0: Port power can be turned ON/OFF. Power Switching Mode Mode for power application 1: Apply power to each port separately...

  • Page 156: Hcrhdescriptorb (Offset Address: 0X4C)

    CHAPTER 11 USB HOST CONTROLLER 11.3.21 HcRhDescriptorB (offset address: 0x4C) (1/2) Bit Position Bit name PPCM PPCM PPCM PPCM PPCM PPCM PPCM PPCM R/W (HCD) R/W (HC) Note Note Note Note Note Note Note Note After reset Bit Position Bit name PPCM PPCM PPCM...
  • Page 157 CHAPTER 11 USB HOST CONTROLLER (2/2) Bit Position Bit Name Function 15:0 Reserved. Write 0. 0 returned when read. Device Removable Connection of device to port 2 1: Connected 0: Not connected Device Removable Connection of device to port 1 1: Connected 0: Not connected Reserved.

  • Page 158: Hcrhstatus (Offset Address: 0X50)

    CHAPTER 11 USB HOST CONTROLLER 11.3.22 HcRhStatus (offset address: 0x50) (1/3) Bit Position Bit name CRWE R/W (HCD) R/W (HC) Note 1 After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Note 2 Bit name OCIC R/W (HCD) R/W (HC) Note 1 Note 1...
  • Page 159 CHAPTER 11 USB HOST CONTROLLER (2/3) Bit Position Bit Name Function CRWE Clean Remote Wakeup Enable 1: Clear the RWE bit of the HcControl register to 0 0: No change 30:18 Reserved. Write 0. Since the values of these bits become undefined after reset, initialize them by software.
  • Page 160 CHAPTER 11 USB HOST CONTROLLER (3/3) Bit Position Bit Name Function Note (During HCD write) Clear Global Power 1: When the PSM bit of the HcRhDescriptorA register is 1, only the PPS bit of the HcRhPortStatus register of the ports that are not set by the PPCM area of the HcRhDescriptorB register is cleared to 0.

  • Page 161: Hcrhportstatus 1 And 2 (Offset Address: 0X54, 0X58)

    CHAPTER 11 USB HOST CONTROLLER 11.3.23 HcRhPortStatus 1 and 2 (offset address: 0x54, 0x58) (1/4) Bit Position Bit name R/W (HCD) R/W (HC) After reset Bit Position Bit name PRSC POCIC PSSC PESC R/W (HCD) R/W (HC) Note 1 Note 1 Note 1 Note 1 Note 1...
  • Page 162 CHAPTER 11 USB HOST CONTROLLER (2/4) Bit Position Bit Name Function 31:21 Reserved. Write 0. 0 returned when read. PRSC Port Reset Status Change This bit is set to 1 upon the end of the reset. It is cleared to 0 when the HCD writes 1 to it. POCIC Port Over Current Indicator Change This bit is set to 1 when the POCI bit changes.
  • Page 163 CHAPTER 11 USB HOST CONTROLLER (3/4) Bit Position Bit Name Function (During write) Set Port Power This bit is set to 1 at the following times. • When the PSM bit of the HcRhDescriptorA register is 0 and the SGP bit of the HcRhStatus register becomes 1 •...
  • Page 164 CHAPTER 11 USB HOST CONTROLLER (4/4) Bit Position Bit Name Function (During write) Set Port Suspend This bit is set to 1 when the HCD writes 1 while the CCS bit is 1. This bit is cleared to 0 when the port power is switched OFF while the PSSC bit is set to 1, or the PRSC bit is set to 1, and the HCFS area of the HcControl register is 01.

  • Page 165: Register Set

    CHAPTER 12 PS/2 CONTROLLER The PS/2 controller controls bi-directional data transfer using the PS2CLK and PS2DATA signals. 12.1 Register Set Table 12-1 lists the PS/2 registers. Table 12-1. PS/2 Registers Address Symbol Function 0x1500 3870 PS2DATA PS/2 transmit/receive data register 0x1500 3872 PS2CTRL PS/2 control register...

  • Page 166: Ps2Data (0X1500 3870)

    CHAPTER 12 PS/2 CONTROLLER 12.1.1 PS2DATA (0x1500 3870) Bit Position Bit name After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Position Bit name PSDATA7 PSDATA6 PSDATA5 PSDATA4 PSDATA3 PSDATA2 PSDATA1 PSDATA0 After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined...

  • Page 167: Ps2Ctrl (0X1500 3872)

    CHAPTER 12 PS/2 CONTROLLER 12.1.2 PS2CTRL (0x1500 3872) Bit Position Bit name After reset Bit Position Bit name PERR RVEN INTEN PS2EN TEMT REMT After reset Undefined Bit Position Bit Name Function 15:6 Reserved. Write 0. 0 returned when read. PERR Receive data parity error detection (Enabled only when the REMT bit is 1, odd parity) 1: Error...

  • Page 168: Chapter 12 Ps/2 Controller

    CHAPTER 12 PS/2 CONTROLLER 12.2 Transmit Procedure The transmit procedure is described below. 1. Set the PS2EN bit to 1 to disable reception. 2. Check that the PS2EN bit is set to 1. 3. If receive data exists, read all the receive data. 4.

  • Page 169: Chapter 13 Connection With V R 4121

    CHAPTER 13 CONNECTION WITH V 4121 This chapter describes how to connect the V 4172 and the V 4121. When connecting the V 4172 and the V 4121, connect the pins corresponding to the following signals using wired OR connection. SCLK AD (0:24) DATA (0:31)

  • Page 170: Cautions When Connecting Load Reduction Buffer

    CHAPTER 13 CONNECTION WITH V 4121 (2) SYSDIR pin (V 4121) Controls the buffer direction used for the data bus. 4172) → V External I/O device (not including V 4121 4121 → External I/O device (not including V 4172) Note When HLDAK# = 0, pull down the SYSDIR pin so that SYSDIR = 0. (3) CKE pin (V 4121) Buffer operation enable...

  • Page 171: Chapter 14 Interrupt Signals

    CHAPTER 14 INTERRUPT SIGNALS The V 4172 has 6 interrupt notification signals, IRQ, INTRP, PS2INT, USBINT#, WAKE, and SMI#. The interrupt source detection block of each interrupt signal is shown in Table 14-1. For the generation source, refer to the chapter of each detection block.
  • Page 172 [MEMO] User’s Manual U14386EJ3V0UM00...

  • Page 173: Chapter 15 Reset

    CHAPTER 15 RESET There are two types of reset, hardware reset and software reset, by external pins (RESET, USBRST# pins). The USBRST# signal is the reset signal for the USB host controller and the internal PCI bus controller (including the SDRAM controller), and the RESET signal is the reset signal for the other blocks. Reset to the various blocks of the 16550 serial controller, IEEE1284 parallel controller, and PS/2 controller starts when the RESET signal becomes active, but these blocks are reset even if the RESET signal becomes inactive.
  • Page 174 [MEMO] User’s Manual U14386EJ3V0UM00...

  • Page 175: Chapter 16 Usage Cautions

    CHAPTER 16 USAGE CAUTIONS The following usage cautions apply to the use of the V 4172. 16.1 Power Supply Control (1) Linkage with SDRAM power supply If the 3.3 V power supply of the V 4121 and the power supply system of the SDRAM are separated and the system is designed so that the power supply to the SDRAM is switched ON after using the SPOWER pin of the V 4121, link the power supply of the V...

  • Page 176: Preserving Sdram Data

    CHAPTER 16 USAGE CAUTIONS 16.4 Preserving SDRAM Data As SDRAM data may be corrupted in the following cases, be sure to take the appropriate countermeasures. (1) When SDRAM is accessed using the USB function in V 4121 Suspend mode When the V 4121 enters Suspend mode, a self-refresh command is issued to SDRAM, and while the V 4121 is in Suspend mode, the bus can be released via a bus hold request.

  • Page 177: Appendix General Index

    Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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