Expansion Ram Board Block Diagram - Data I/O 298 Manual

The decode PROMs provide selection of the various gates,
registers and other devices connected to the
data
bus.
Refei to the memory map of table 5-1. V•02 is connected
to the chip select of each decode PROM to provide the
correct timing for writing to registers or reading gates or
memory.
R/W
is used for EPROM timing.
The programming module interface is provided by address
registers, status gates, data register, data gates and control
register.
When a programming module is removed, the
microprocessor is held reset by a high on the line HH of
J7. When the programming module is installed, line HH of
J7 is grounded, removing the reset after a short delay. This
feature allows programming modules to be changed with
the power on in order to preserve RAM data.
Additional flexibility of the programming module interface
can be gained with software control of the interface control
register. The programming module interface can be set up
so that the microprocessor bus is buffered and directly
available at the port. This is accomplished by disabling the
address register outputs, enabling the address gates in the
outward direction, and connecting the data gate directly to
...._
---
U20,
~
U21
.,.____
U22
AO-A15 _
ADDRESS
-
,.
""7'
DECODER
'~
""1L._
DO-D7
U17
-
PAGE
~4
...
---,.
REGISTER
~
the R/W line. The data gate is enabled at the appropriate
address by decoding done externally to the port over the
Data Gate Enable line.
The seiial inteiface is controlled by a 6850 Asynchronous
Communications Interface Adapter (ACIA, U14) and
appropriate sofu'Vare. The timing signal for the ACIA is
provided by the baud rate generator U7. The baud rate is
selected by rate· select switch US. The status switch
provides for selecting parity and stop bits. The ACIA
occupies two addresses (table 5-1) and uses !RQ to
interface with the microprocessor.
The on-board program memory occupies ups to 28K bytes
of PROM U32-U38 decoded in 4K segments.
Temporary data storage on the controller board consists of
2K bytes of RAM (U17, U28) decoded in 1 K segments.
Expansion RAM Board
The Expansion RAM Board (figure 5-9) allows the
expansion of the base unit memory by up to 64K bytes.
The RAM is in 16K byte banks with four banks per page.
Future expansion of the board RAM wiU permit 128K of
memory .
I
' "
'~
U23, U26
U27, U28
--
....
U1-U16
ADDRESS
...
---,.
RAM
MUX
'~
U24
REFRESH
COUNTER
EXPANSION RAM BOARD
Figure 5-9. Expansion RAM Board Block Diagram
5-9
10-990-0013