D
c
B
A
8
7
6
5
4
3
J2
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BUS
A0
Al
A2
A3
A4
A5
A6
A7
AS
A9
Al0
All
Al2
Al3
Al4
Al5
00
DI
D2
D3
D4
05
06
Isl
07
~&----
-m
37
E 2
TOR-
R
IRQ
NMI
R/W 4
m
74LSl26
+5V
~
DATA
DATA
BUS
B
SHT3.D4
DATA
BUS A
BUFFER B
SHT2,D3
PROCESSOR
SHT4,06
I
A
B
19
33
DO
NJ
U48
8304
18
32
DI
Al
iO
~
17
31
D2
A2 II
!2
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-- I?
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16
29
04
M
13
15
05
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14
14
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A6
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7
13
26
UT
l>.7
16
EN
DIR
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EN
H
Ul3
SHT3 ,A2
6802
3
MR
OR
R/W
6808
74LSl26
38
XTAL
+5
Y2
110 DECODE 0
CJ4MHz
SHT3 ,C2
39
EXTAL
DATA
cs
IOPF/200V
~
BUFFER A
I A
19
Q
B
Ul2
2
18
8304
.3
17
4
cy
16
- - - · · - -
12
14
13
EN
t5
9
8
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12
R/W BUFFER IN
BA
R/W
12
y
+~
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"(Pi
3.31<
CR27
+ c
5
o - -
IN4148
~l/35V
CRR
TONE
TP3 •
74LSOO
INTERLOCK
SHT3, A4
SHT 5,82
+
GND
GNO
HALT
2
12
BA
_\IM
RIW
34
14
R65
U54
LM555
74LS367
5
ADDRESS
BUFFER
2
18
ii
Uii
3
4
74LS244
16
........
..
-q-1,:
12
II
9
iG
2G
19
U23.
74LS244
{(-
iG
2G
19
2
12
74LSOO
74LSOO
RD GATE
C47
.Ol/IOOV
BA
~
BA
WR
R/W
RD
R/W
SHT2.D8
SHT3,D5
SHT3.C3
SHT 4.06
ASSY 701-0047-002
SHT2,B3.D8
SHT4,B8
SHT3,D5
CONTROL
BUS
QUAL. ASSUR.
fNGR. MGR
2
REVISIONS
LTR
DESCRIPTION
DR CHK APPR'D DATE
A
RELEAS
B
ECP
#0006,
ADCNHAI
C
ADCN Bl , ECP NO.
0024
NOTES:
UNLESS OTHERWISE SPECIFIED
I. ALL RESISTORS ARE
l/4W
AND IN OHMS,
5'%.
2. ALL CAPACITORS ARE IN MICROFARAD$.
3. LAST REFERENCE DESIGNATOR USED=
C54, CR28,J8,
JP5,Q26,R69,RP8,TP3,U55,
VR4,Y2
4. REFERENCE DESIGNATORS NOT USED:
C7, Cl6,C33,C4!5
5.
UNUSED GATES:
6
8
4
U3
74 HCi4
4 PLACES
~
~
1488
2PLACES
~
1489
6. POWER SUPPLY
CHART ON
SHEET 4.
SCHEMATIC
DIAGRAM
CONTROLLER BOARD
SIZE
CODE INDENT.
DRAWING NO.
NO.
0
30-101-0047
SHEET
I OF 5
In
I .,
I
c
B
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