Optional Handler Interface Block Diagram - Data I/O 298 Manual

Timing is generated using system timing in conjunction
with a tapped digital delay line (U20), with a PAL (U21) as
the combinational logic.
Address decoding is performed by PAL U22. U17 serves as
the bank and page register, with D6 and D7 at address
E300 controlling the bank select, and DO at address E301
controlling the page select.
Address multiplexing is accomplished via U23, U26, U27
and U28. Multiplex timing is generated by the delay
line/ PAL timing generator.
The board uses invisible refresh for the RAMs. During the
first half of each 'E' cycle, the RAMs are refreshed.
Refresh timing is generated by the delay line/PAL timing
generator. The refresh address is generated by U24.
J1
~
COMP
U1
3-T0-8
RUN
DECODER
D4-D7
~
64K or 128K (future) configuration is selected by the
programming of PAL, U22.
The D-RAM array is addressed at 2000 through 5FFF,
hexidecimal.
Handler Interface Board (Optional)
The handler interface board (Figure 5-10) is comprised of a
3-to-8 decoder (U1) which receives binning information
from the controller register U31 and ouputs this information
to the handler interface connector at the back panel of the
298. Also at this interface a strobe signal is used to notify
the handler when the binning information is stable.
Only one of four possible binning signals are sent at any
one time: pass bin, illegal bit bin, program error bin, or
verify error bin.
J3
~
...
-,
U3
--
PASS BIN
ILLEGAL BIN
PROGRAMMING ERROR BIN
VERIFY ERROR BIN
STROBE
IDO
ID1
ID2
START
OPTIONAL HANDLER INTERFACE
Figure 5-10. Optional Handler Interface, Block Diagram
5-10
10-990-CX)13