ADV7181B
2
I
C PROGRAMMING EXAMPLES
EXAMPLES FOR 28 MHz CLOCK
Mode 1 CVBS Input (Composite Video on AIN6)
All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
Table 86. Mode 1 CVBS Input
Register Address
Register Value
0x15
0x00
0x17
0x41
0x1D
0x40
0x0F
0x40
0x3A
0x16
0x3D
0xC3
0x3F
0xE4
0x50
0x04
0xC3
0x05
0xC4
0x80
0x0E
0x80
0x50
0x20
0x52
0x18
0x58
0xED
0x77
0xC5
0x7C
0x93
0x7D
0x00
0x90
0xC9
0x91
0x40
0x92
0x3C
0x93
0xCA
0x94
0xD5
0xCF
0x50
0xD0
0x4E
0xD6
0xDD
0xE5
0x51
0xD5
0xA0
0xD7
0xEA
0xE4
0x3E
0xEA
0x0F
0xE9
0x3E
0x0E
0x00
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Notes
Slow down digital clamps.
Set CSFM to SH1.
Enable 28 MHz crystal.
TRAQ.
Power down ADC 1 and ADC 2.
MWE enable manual window.
BGB to 36.
Set DNR threshold.
Man mux AIN6 to ADC0 (0101).
Enable manual muxing.
ADI recommended programming sequence. This sequence must be followed exactly when setting
up the decoder.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Rev. B | Page 88 of 100
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