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FEATURES
Multiformat video decoder supports NTSC-(M, J, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, 9-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive Digital Line Length Tracking (ADLLT™),
signal processing, and enhanced FIFO management
give mini-TBC functionality
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
®
Macrovision
copy protection detection
Chroma transient improvement (CTI)
Digital noise reduction (DNR)
Multiple programmable analog input formats
Composite video (CVBS)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and BetaCam)
6 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit or16-bit)
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
0.5 V to 1.6 V analog signal input range
Differential gain: 0.6% typ
Differential phase: 0.6° typ
GENERAL DESCRIPTION
The ADV7181B integrated video decoder automatically detects
and converts a standard analog baseband television signal
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data compatible with 16-bit/8-bit
CCIR601/CCIR656.
The advanced, highly flexible digital output interface enables
performance video decoding and conversion in line-locked
clock-based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video charac-
teristics, including tape-based sources, broadcast sources,
security/surveillance cameras, and professional systems.
The six analog input channels accept standard composite,
S-Video, and YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an input
video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively,
these can be bypassed for manual settings.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
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electronic components distributor
Multiformat SDTV Video Decoder
Programmable video controls
Peak white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free-run mode (generates stable video output with no I/P)
VBI decode support for
close captioning, WSS, CGMS, EDTV, Gemstar® 1×/2×
VBI decode support for
close captioning, WSS, CGMS, EDTV, and
Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
Temperature grade: –40°C to +85°C
64-lead LQFP Pb-free package and 64-lead LFCSP package
APPLICATIONS
DVD recorders
PC video
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
Portable video devices
Automotive entertainment
AVR receivers
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allows very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line-locked even with ±5% line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7181B modes
are set up over a 2-wire, serial, bidirectional port (I
The ADV7181B is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7181B is available in two packages, a small 64-lead
LQFP Pb-free package and a 64-lead LFCSP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
ADV7181B
2
C®-compatible)
2
C-compatible).
www.analog.com
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Table of Contents
Related Manuals for Analog Devices ADV7181BCP
Summary of Contents for Analog Devices ADV7181BCP
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Page 1: Changes To General Description Section
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. -
Page 2: Table Of Contents
ADV7181B TABLE OF CONTENTS Introduction ..................4 General Setup................20 Analog Front End ................. 4 Color Controls ................22 Standard Definition Processor ........... 4 Clamp Operation................ 24 Functional Block Diagram .............. 5 Luma Filter .................. 25 Specifications..................6 Chroma Filter................28 Electrical Characteristics............. - Page 3 ADV7181B Typical Circuit Connection ............97 Ordering Guide .................100 Outline Dimensions................99 REVISION HISTORY Changes to Figure 11 to Figure 14 ..........28 9/05—Rev. A to Rev. B Changes to Description of Chroma Filter........28 Changes to Table 1 ................6 Changes to Figure 15 ..............29 Changes to Table 2 ................7 Changes to Luma Gain LAGC[2:0] Bits Address......30 Changes to Table 3 and Table 4 ............8...
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Page 4: Introduction
ADV7181B INTRODUCTION include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, The ADV7181B is a high quality, single chip, multiformat video NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The decoder that automatically detects and converts PAL, NTSC, ADV7181B can automatically detect the video standard and and SECAM standards in the form of composite, S-Video, and process it accordingly. -
Page 5: Functional Block Diagram
ADV7181B FUNCTIONAL BLOCK DIAGRAM OUTPUT FORMATTER Figure 1. Rev. B | Page 5 of 100 Downloaded from Elcodis.com electronic components distributor... -
Page 6: Specifications
ADV7181B SPECIFICATIONS ELECTRICAL CHARACTERISTICS = 3.15 V to 3.45 V, D = 1.65 V to 2.0 V, D = 3.0 V to 3.6 V, P = 1.65 V to 2.0 V; operating temperature range, unless VDDIO otherwise noted. Table 1. 1, 2 Parameter Symbol... -
Page 7: Video Specifications
ADV7181B VIDEO SPECIFICATIONS Guaranteed by characterization. A = 3.15 V to 3.45 V, D = 1.65 V to 2.0 V, D = 3.0 V to 3.6 V, P = 1.65 V to 2.0 V; VDDIO operating temperature range, unless otherwise noted. Table 2. -
Page 8: Timing Specifications
ADV7181B TIMING SPECIFICATIONS Guaranteed by characterization. A = 3.15 V to 3.45 V, D = 1.65 V to 2.0 V, D = 3.0 V to 3.6 V, P = 1.65 V to 2.0 V; VDDIO operating temperature range, unless otherwise noted. Table 3. -
Page 9: Thermal Specifications
ADV7181B THERMAL SPECIFICATIONS Table 5. 1, 2 Parameter Symbol Test Conditions Unit THERMAL CHARACTERISTICS Junction-to-Ambient Thermal θ 4-layer PCB with solid ground plane, 64-lead LFCSP 45.5 °C/W Resistance (Still Air) Junction-to-Case Thermal Resistance θ 4-layer PCB with solid ground plane, 64-lead LFCSP °C/W Junction-to-Ambient Thermal θ... -
Page 10: Absolute Maximum Ratings
ADV7181B ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating Stresses above those listed under Absolute Maximum Ratings to GND may cause permanent damage to the device. This is a stress to AGND rating only; functional operation of the device at these or any to DGND 2.2 V other conditions above those indicated in the operational... -
Page 11: Pin Configuration And Function Descriptions
ADV7181B PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTRQ AIN5 PIN 1 AIN4 INDICATOR DGND AIN3 DVDDIO AGND CAPC2 AGND ADV7181B REFOUT TOP VIEW AVDD (Not to Scale) DGND CAPY2 DVDDIO CAPY1 AGND AIN2 AIN1 DGND NC = NO CONNECT Figure 4. 64-Lead LFCSP/LQFP Pin Configuration Rev. - Page 12 The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 45. Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. REFOUT Internal Voltage Reference Output.
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Page 13: Analog Front End
ADV7181B ANALOG FRONT END ADC_SW_MAN_EN AIN2 AIN1 ADC0_SW[3:0] AIN4 AIN3 AIN6 ADC0 AIN5 AIN4 AIN3 ADC1_SW[3:0] AIN6 AIN5 ADC1 AIN6 AIN5 ADC2_SW[3:0] ADC2 Figure 5. Internal Pin Connections SETADC_sw_man_en, Manual Input Muxing Enable, The two key steps to configure the ADV7181B to correctly decode the input video are: Address C4[7] ADC0_sw[3:0], ADC0 mux configuration, Address C3[3:0]... - Page 14 ADV7181B Table 8. Manual Mux Settings for All ADCs (SETADC_sw_man_en = 1) ADC0_sw[3:0] ADC0 Connected to ADC1_sw[3:0] ADC1 Connected to ADC2_sw[3:0] ADC2 Connected to: 0000 No connection 0000 No connection 0000 No connection 0001 AIN2 0001 No connection 0001 No connection 0010 No connection 0010...
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Page 15: Global Control Registers
ADV7181B GLOBAL CONTROL REGISTERS PWRDN_ADC_0, Address 0x3A[3] Register control bits listed in this section affect the whole chip. When PWRDN_ADC_0 is 0 (default), the ADC is in normal POWER-SAVE MODES operation. Power-Down When PWRDN_ADC_0 is 1, ADC 0 is powered down. The digital core of the ADV7181B can be shut down by using a pin ( PWRDN ) and a bit (PWRDN);... -
Page 16: Global Pin Control
ADV7181B GLOBAL PIN CONTROL Individual drive strength controls are provided via the DR_STR_XX bits. Three-State Output Drivers TOD, Address 0x03[6] When TIM_OE is 0 (default), HS, VS, and FIELD are three- stated according to the TOD bit. This bit allows the user to three-state the output drivers of the ADV7181B. - Page 17 ADV7181B Polarity LLC Pin Enable Subcarrier Frequency Lock Pin PCLK Address 0x37[0] EN_SFL_PIN Address 0x04[1] The polarity of the clock that leaves the ADV7181B via the LLC The EN_SFL_PIN bit enables the output of subcarrier lock pin can be inverted using the PCLK bit. information (also known as GenLock) from the ADV7181B core to an encoder in a decoder-encoder back-to-back Changing the polarity of the LLC clock output can be necessary...
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Page 18: Global Status Registers
ADV7181B GLOBAL STATUS REGISTERS Four registers provide summary information about the video Table 14. STATUS 1 Function decoder. The IDENT register allows the user to identify the STATUS 1[7:0] Bit Name Description revision code of the ADV7181B. The other three registers IN_LOCK In lock (right now). -
Page 19: Standard Definition Processor (Sdp)
ADV7181B STANDARD DEFINITION PROCESSOR (SDP) STANDARD DEFINITION PROCESSOR MACROVISION STANDARD SLLC VBI DATA DETECTION AUTODETECTION CONTROL RECOVERY DIGITIZED CVBS LUMA DIGITIZED Y (YC) LUMA GAIN LUMA LUMA DIGITAL FILTER CONTROL RESAMPLE 2D COMB FINE CLAMP LINE SYNC RESAMPLE VIDEO DATA LENGTH CODE EXTRACT... -
Page 20: Sync Processing
ADV7181B SYNC PROCESSING GENERAL SETUP Video Standard Selection The ADV7181B extracts syncs embedded in the video data stream. There is currently no support for external HS/VS The VID_SEL[3:0] register allows the user to force the digital inputs. The sync extraction has been optimized to support core into a specific video standard. -
Page 21: Changes To Lock Related Controls Section
NTSC. Setting AD_P60_EN to 0 disables the autodetection of PAL Second, there was a design change in Analog Devices encoders systems with a 60 Hz field rate. from ADV717x to ADV719x. The older versions used the SFL Setting AD_P60_EN to 1 (default) enables the detection. -
Page 22: Color Controls
ADV7181B SRLS Select Raw Lock Signal, Address 0x51[6] COL[2:0] Count Out-of-Lock, Address 0x51[5:3] Using the SRLS bit, the user can choose between two sources for COL[2:0] determines the number of consecutive lines for which determining the lock status (per Bits[1:0] in the Status 1 register). the out-of-lock condition must be true before the system switches into unlocked state, and reports this via Status 0[1:0]. - Page 23 ADV7181B SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address HUE[7:0] Hue Adjust, Address 0x0B[7:0] 0xE4[7:0] This register contains the value for the color hue adjustment. This register allows the user to control the gain of the Cr It allows the user to adjust the hue of the picture. channel only, which in turn adjusts the saturation of the picture.
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Page 24: Clamp Operation
ADV7181B DEF_VAL_EN Default Value Enable, Address 0x0C[0] The clamping can be divided into two sections • This bit forces the use of the default values for Y, Cr, and Cb. Clamping before the ADC (analog domain): current Refer to the descriptions for DEF_Y and DEF_C for additional sources. -
Page 25: Luma Filter
ADV7181B The following sections describe the I C signals that can be used LUMA FILTER to influence the behavior of the clamping block. Data from the digital fine clamp block is processed by three sets of filters. The data format at this point is CVBS for CVBS input Previous revisions of the ADV7181B had controls (FACL/FICL, or luma only for Y/C and YPrPb input formats. - Page 26 ADV7181B Y-Shaping Filter In automatic mode, the system preserves the maximum possible bandwidth for good CVBS sources (since they can successfully For input signals in CVBS format, the luma shaping filters play be combed) as well as for luma components of YPrPb and YC an essential role in removing the chroma component from a sources, since they need not be combed.
- Page 27 ADV7181B SET YSFM YSFM IN AUTO MODE? 00000 OR 00001 VIDEO QUALITY GOOD USE YSFM SELECTED FILTER REGARDLESS FOR GOOD AND BAD VIDEO AUTO SELECT LUMA SHAPING FILTER TO WYSFMOVR COMPLEMENT COMB SELECT WIDEBAND SELECT AUTOMATIC FILTER AS PER WIDEBAND FILTER WYSFM[4:0] Figure 10.
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Page 28: Chroma Filter
ADV7181B COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS, The filter plots in Figure 11 show the S-VHS 1 (narrowest) to Y RESAMPLE S-VHS 18 (widest) shaping filter settings. Figure 13 shows the PAL notch filter responses. The NTSC-compatible notches are shown in Figure 14. –10 COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS, –20... -
Page 29: Gain Operation
ADV7181B CSFM[2:0] C Shaping Filter Mode, Address 0x17[7] GAIN OPERATION The C shaping filter mode bits allow the user to select from a The gain control within the ADV7181B is done on a purely range of low-pass filters, SH1 to SH5 and wideband mode, for digital basis. -
Page 30: Changes To Luma Gain Lagc[2:0] Bits Address
ADV7181B Table 32. AGC Modes Input Video Type Luma Gain Chroma Gain Manual gain luma Manual gain chroma CVBS Dependent on horizontal sync depth Dependent on color burst amplitude; taken from luma path Peak white Dependent on color burst amplitude; taken from luma path Dependent on horizontal sync depth Dependent on color burst amplitude;... -
Page 31: Changes To Table References In Betacam Section
ADV7181B For example, program the ADV7181B into manual fixed gain PW_UPD Peak White Update, Address 0x2B[0] mode with a desired gain of 0.89. The peak white and average video algorithms determine the gain based on measurements taken from the active video. The Use Equation 1 to convert the gain: PW_UPD bit determines the rate of gain change. -
Page 32: Chroma Transient Improvement (Cti)
ADV7181B CG[11:0] Chroma Gain, Address 0x2D[3:0]; CKILLTHR[2:0] Color Kill Threshold, Address 0x2E[7:0]; CMG[11:0] Chroma Manual Gain, Address 0x3D[6:4] Address 0x2D[3:0]; Address 0x2E[7:0] The CKILLTHR[2:0] bits allow the user to select a threshold for the color kill function. The threshold applies to only QAM- Chroma gain[11:0] is a dual-function register. -
Page 33: Digital Noise Reduction (Dnr)
ADV7181B The chroma transient improvement block examines the input CTI_C_TH[7:0] CTI Chroma Threshold, video data. It detects transitions of chroma, and can be Address 0x4E[7:0] programmed to steepen the chroma edges in an attempt to The CTI_C_TH[7:0] value is an unsigned, 8-bit number speci- artificially restore lost color bandwidth. -
Page 34: Changes To Pal Comb Filter Settings Section
ADV7181B NSFSEL[1:0] Split Filter Selection NTSC, CTAPSN[1:0] Chroma Comb Taps NTSC, Address 0x19[3:2] Address 0x38[7:6] Table 44. CTAPSN Function The NSFSEL[1:0] control selects how much of the overall signal CTAPSN[1:0] Description bandwidth is fed to the combs. A narrow split filter selection Do not use gives better performance on diagonal lines, but leaves more dot NTSC chroma comb adapts 3 lines (3 taps) to 2... - Page 35 ADV7181B CTAPSP[1:0] Chroma Comb Taps PAL, Address 0x39[7:6] Table 48. CTAPSP Function CTAPSP[1:0] Description Do not use PAL chroma comb adapts 5 lines (3 taps) to 3 lines (2 taps); cancels cross luma only PAL chroma comb adapts 5 lines (5 taps) to 3 lines (3 taps);...
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Page 36: Av Code Insertion And Controls
ADV7181B AV CODE INSERTION AND CONTROLS This section describes the I C-based controls that affect: In this output interface mode, the following assignment takes place: Cb = FF, Y = 00, Cr = 00, and Y = AV. • Insertion of AV codes into the data stream. In a 16-bit output interface where Y and Cr/Cb are delivered via •... - Page 37 ADV7181B BL_C_VBI Blank Chroma During VBI, Address 0x04[2] LTA[1:0] Luma Timing Adjust, Address 0x27[1:0] Setting BL_C_VBI high, the Cr and Cb values of all VBI lines The luma timing adjust register allows the user to specify a are blanked. This is done so any data that may arrive during timing difference between chroma and luma samples.
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Page 38: Synchronization Output Signals
ADV7181B SYNCHRONIZATION OUTPUT SIGNALS HSE[10:0] HS End, Address 0x34[2:0], Address 0x36[7:0] HS Configuration The position of this edge is controlled by placing a binary number into HSE[10:0]. The number applied offsets the edge The following controls allow the user to configure the behavior with respect to an internal counter that is reset to 0 immediately of the HS output pin only: after EAV Code FF, 00, 00, XY (see Figure 19). -
Page 39: Changes To Vsehe Vs End Horizontal Position Section
ADV7181B VS and FIELD Configuration VSBHO VS Begin Horizontal Position Odd, The following controls allow the user to configure the behavior Address 0x32[7] of the VS and FIELD output pins, as well as the generation of The VSBHO and VSBHE bits select the position within a line at embedded AV codes: which the VS pin (not the bit in the AV code) becomes active. -
Page 40: Changes To Figure 20
ADV7181B When PF is 0 (default), FIELD is active high. PF Polarity FIELD, Address 0x37[3] When PF is 1, FIELD is active low. The polarity of the FIELD pin can be inverted using the PF bit. The FIELD pin can be inverted using the PF bit. FIELD 1 OUTPUT VIDEO... -
Page 41: Changes To Table 54
ADV7181B Table 55. Recommended User Settings for NTSC (See Figure 21) Register Register Name Write 0x31 Vsync Field Control 1 0x1A 0x32 Vsync Field Control 2 0x81 0x33 Vsync Field Control 3 0x84 0x34 Hsync Pos. Control 1 0x00 0x35 Hsync Pos. -
Page 42: Changes To Table 55
ADV7181B NVENDSIGN ADVANCE END OF DELAY END OF VSYNC VSYNC BY NVEND[4:0] BY NVEND[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? NVENDDELO NVENDDELE ADDITIONAL ADDITIONAL DELAY BY DELAY BY 1 LINE 1 LINE VSEHO VSEHE ADVANCE BY ADVANCE BY 0.5 LINE 0.5 LINE VSYNC END Figure 23. -
Page 43: Change To Nftog Section
ADV7181B NFTOGSIGN ADVANCE TOGGLE OF DELAY TOGGLE OF FIELD BY NFTOG[4:0] FIELD BY NFTOG[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? NFTOGDELO NFTOGDELE ADDITIONAL ADDITIONAL DELAY BY DELAY BY 1 LINE 1 LINE FIELD TOGGLE Figure 24. NTSC Field Toggle Table 56. - Page 44 ADV7181B FIELD 1 OUTPUT VIDEO PVBEG[4:0] = 0x5 PVEND[4:0] = 0x4 PFTOG[4:0] = 0x3 FIELD 2 OUTPUT VIDEO PVBEG[4:0] = 0x5 PVEND[4:0] = 0x4 PFTOG[4:0] = 0x3 Figure 25. PAL Default (BT.656). The Polarity of H, V, and F is Embedded in the Data FIELD 1 OUTPUT VIDEO...
- Page 45 ADV7181B For all NTSC/PAL Vsync timing controls, both the V bit in the PVBEGSIGN AV code and the Vsync on the VS pin are modified. ADVANCE BEGIN OF DELAY BEGIN OF PVENDSIGN VSYNC BY PVBEG[4:0] VSYNC BY PVBEG[4:0] ADVANCE END OF DELAY END OF VSYNC NOT VALID FOR USER VSYNC BY PVEND[4:0]...
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Page 46: Sync Processing
ADV7181B PVEND[4:0] PAL Vsync End, Address 0xE9[4:0] SYNC PROCESSING The default value of PVEND is 10100, indicating the PAL Vsync The ADV7181B has two additional sync processing blocks that end position. postprocess the raw synchronization information extracted from the digitized input video. If preferred, the blocks can be For all NTSC/PAL Vsync timing controls, both the V bit in the disabled via the following two I C bits. - Page 47 ADV7181B The closed captioning data (CCAP) is available in the I CGMSD CGMS-A Sequence Detected, Address 0x90[3] registers, and is also inserted into the output video data stream Logic 1 for this bit indicates the data in the CGMS1, 2, 3 during horizontal blanking.
- Page 48 ADV7181B Table 57. WSS Access Information Signal Name Register Location Address Register Default Value WSS1[7:0] WSS 1[7:0] 145d 0x91 Readback only WSS2[5:0] WSS 2[5:0] 146d 0x92 Readback only EDTV1[7:0] EDTV2[7:0] EDTV3[5:0] NOT SUPPORTED 1 2 3 4 0 1 2 Figure 31.
- Page 49 ADV7181B Table 59. CGMS Access Information Signal Name Register Location Address Register Default Value CGMS1[7:0] CGMS 1[7:0] 150d 0x96 Readback Only CGMS2[7:0] CGMS 2[7:0] 151d 0x97 Readback Only CGMS3[3:0] CGMS 3[3:0] 152d 0x98 Readback Only ± 10.5 0.25μs 12.91μs 7 CYCLES OF 0.5035MHz CCAP1[7:0] CCAP2[7:0]...
- Page 50 ADV7181B LB_LCT[7:0] Letterbox Line Count Top, The recovered data is not available through I C, but is inserted Address 0x9B[7:0]; LB_LCM[7:0] Letterbox Line Count into the horizontal blanking period of an ITU-R BT.656-com- Mid, Address 0x9C[7:0]; LB_LCB[7:0] Letterbox Line Count patible data stream.
- Page 51 ADV7181B DATA IDENTIFICATION SECONDARY DATA IDENTIFICATION DATA OPTIONAL PADDING CHECK SDID USER DATA COUNT BYTES PREAMBLE FOR ANCILLARY DATA USER DATA (4 OR 8 WORDS) Figure 34. Gemstar and CCAP Embedded Data Packet (Generic) Table 63. Generic Data Output Packet Byte D[9] D[8]...
- Page 52 ADV7181B • Gemstar 2× Format, Half-Byte Output Mode CS[8:2]. The checksum is provided to determine the integrity of the ancillary data packet. It is calculated by Half-byte output mode is selected by setting CDECAD = 0; summing up D[8:2] of DID, SDID, the data count byte, and full-byte output mode is selected by setting CDECAD = 1.
- Page 53 ADV7181B Table 67. Gemstar 1× Data, Half-Byte Mode Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description Fixed preamble Fixed preamble Fixed preamble Line[3:0] SDID Data count Gemstar Word1[7:4] User data-words Gemstar Word1[3:0] User data-words Gemstar Word2[7:4] User data-words Gemstar Word2[3:0] User data-words...
- Page 54 ADV7181B NTSC CCAP Data PAL CCAP Data Half-byte output mode is selected by setting CDECAD = 0; the Half-byte output mode is selected by setting CDECAD = 0; full-byte mode is enabled by CDECAD = 1. See the GDECAD full-byte output mode is selected by setting CDECAD = 1. Gemstar Decode Ancillary Data Format, See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] section.
- Page 55 ADV7181B Table 72. PAL CCAP Data, Full-Byte Mode Byte D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Description Fixed preamble Fixed preamble Fixed preamble SDID Data count CCAP Word1[7:0] User data-words CCAP Word2[7:0] User data-words UDW padding 0x200 UDW padding 0x200 !CS[8] CS[8]...
- Page 56 ADV7181B Table 73. NTSC Line Enable Bits and Corresponding Line Table 74. PAL Line Enable Bits and Corresponding Line Numbering Numbering Line Number Line Number Line[3:0] (ITU-R BT.470) Enable Bit Comment Line[3:0] (ITU-R BT.470) Enable Bit Comment GDECOL[0] Gemstar GDECOL[0] Not valid GDECOL[1] Gemstar...
- Page 57 ADV7181B IF Compensation Filter C Interrupt System IF FILTSEL[2:0] IF Filter Select Address 0xF8[2:0] The ADV7181B has a comprehensive interrupt register set. This map is located in Register Access Page 2. See Table 83 or details The IF FILTSEL[2:0] register allows the user to compensate of the interrupt register map.
- Page 58 ADV7181B Macrovision Interrupt Selection Bits INTRQ_OP_SEL[1:0], Interrupt Duration Select Address 0x40 (Interrupt Space)[1:0] The user can select between pseudo sync pulse and color stripe Table 76. INTRQ_OP_SEL detection as follows: INTRQ_OP_SEL[1:0] Description MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection Open drain (default) Bits, Address 0x40 (Interrupt Space)[5:4] Drive low when active Table 77.
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Page 59: Pixel Port Configuration
ADV7181B PIXEL PORT CONFIGURATION The ADV7181B has a very flexible pixel port that can be config- LLC1 Output Selection, LLC_PAD_SEL[2:0], ured in a variety of formats to accommodate downstream ICs. Address 0x8F[6:4] Table 78 and Table 79 summarize the various functions that the The following I C write allows the user to select between the ADV7181B pins can have in different modes of operation. -
Page 60: Mpu Port Description
ADV7181B MPU PORT DESCRIPTION The ADV7181B supports a 2-wire (I C-compatible) serial inter- Logic 0 on the LSB of the first byte means that the master writes face. Two inputs, serial data (SDA) and serial clock (SCLK), information to the peripheral. Logic 1 on the LSB of the first carry information between the ADV7181B and the system I byte means that the master reads information from the master controller. -
Page 61: Register Accesses
ADV7181B C SEQUENCER REGISTER ACCESSES An I C sequencer is used when a parameter exceeds eight bits The MPU can write to or read from all of the ADV7181B’s and is, therefore, distributed over two or more I C registers, for registers, except the subaddress register, which is write only. -
Page 62: I 2 C Register Maps
ADV7181B C REGISTER MAPS Table 81. Common and Normal (Page 1) Register Map Details Subaddress Register Name Reset Value Input Control 0000 0000 0x00 Video Selection 1100 1000 0x01 Reserved 0000 0100 0x02 Output Control 0000 1100 0x03 Extended Output Control 01xx 0101 0x04 Reserved... - Page 63 ADV7181B Subaddress Register Name Reset Value Reserved xxxx xxxx 62 to 64 0x3E to 0x40 Resample Control 0100 0001 0x41 Reserved xxxx xxxx 66 to 71 0x42 to 0x47 Gemstar Ctrl 1 00000000 0x48 Gemstar Ctrl 2 0000 0000 0x49 Gemstar Ctrl 3 0000 0000 0x4A...
- Page 64 ADV7181B Subaddress Register Name Reset Value Drive Strength xx01 0101 0xF4 Reserved xxxx xxxx 245-247 0xF5-0xF7 IF Comp Control 0000 0000 0xF8 VS Mode Control 0000 0000 0xF9 Table 82. Common and Normal (Page 1) Register Map Bit Names Register Name Bit 7 Bit 6...
- Page 65 ADV7181B Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Luma Gain LMG.7 LMG.6 LMG.5 LMG.4 LMG.3 LMG.2 LMG.1 LMG.0 Control 2 Vsync Field NEWAVMODE HVSTIM Control 1 Vsync Field VSBHO VSBHE Control 2 Vsync Field...
- Page 66 ADV7181B Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Letterbox LB_TH.4 LB_TH.3 LB_TH.2 LB_TH.1 LB_TH.0 Control 1 Letterbox LB_SL.3 LB_SL.2 LB_SL.1 LB_SL.0 LB_EL.3 LB_EL.2 LB_EL.1 LB_EL.0 Control 2 Reserved Reserved Reserved SD Offset Cb SD_OFF_CB.7...
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Page 67: I 2 C Register Map Details
ADV7181B C REGISTER MAP DETAILS The following registers are located in Register Access Page 2. Table 83. Interrupt Register Map Bit Names Subaddress Register Reset Name Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Interrupt 0001 x000... - Page 68 ADV7181B Table 84. Interrupt Register Map Details Subaddress Register Bit Description Comments Notes 0x40 Interrupt INTRQ_OP_SEL[1:0]. Open drain Config 1 Interrupt Drive Level Select. Drive low when active Drive high when active Register Reserved Access MPU_STIM_INTRQ[1:0]. Manual interrupt mode disabled Page 2 Manual Interrupt Set Mode.
- Page 69 ADV7181B Subaddress Register Bit Description Comments Notes 0x44 Interrupt SD_LOCK_MSKB. Masks SD_LOCK_Q bit Mask 1 Unmasks SD_LOCK_Q bit SD_UNLOCK_MSKB. Masks SD_UNLOCK_Q bit Read/Write Unmasks SD_UNLOCK_Q bit Register Reserved. Not used Reserved. Not used Register Reserved. Not used Access Page 2 SD_FR_CHNG_MSKB.
- Page 70 ADV7181B Subaddress Register Bit Description Comments Notes 0x48 Interrupt CCAPD_MSKB. Masks CCAPD_Q bit Mask 2 Unmasks CCAPD_Q bit GEMD_MSKB. Masks GEMD_Q bit Read/ Unmasks GEMD_Q bit Write CGMS_CHNGD_MSKB. Masks CGMS_CHNGD_Q bit Unmasks CGMS_CHNGD_Q bit Register WSS_CHNGD_MSKB. Masks WSS_CHNGD_Q bit Access Page 2 Unmasks WSS_CHNGD_Q bit Reserved.
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Page 71: Changes To Table 84
ADV7181B Subaddress Register Bit Description Comments Notes 0x4B Interrupt SD_OP_CHNG_CLR. Do not clear Clear 3 Clears SD_OP_CHNG_Q bit SD_V_LOCK_CHNG_CLR. Do not clear Write Only Clears SD_V_LOCK_CHNG_Q bit Register SD_H_LOCK_CHNG_CLR. Do not clear Clears SD_H_LOCK_CHNG_Q bit Register SD_AD_CHNG_CLR. Do not clear Access Page 2 Clears SD_AD_CHNG_Q bit... -
Page 72: Changes To Table 85
ADV7181B Table 85. Common and Normal (Page 1) Register Map Details Bits Subaddress Register Bit Description Comments Notes 0x00 Input INSEL[3:0]. The INSEL bits allow the Composite Control user to select an input channel as Reserved well as the input format. Reserved Reserved Reserved... - Page 73 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0x03 Output SD_DUP_AV. Duplicates the AV AV codes to suit 8-bit Control codes from the Luma into the interleaved data output chroma path. AV codes duplicated (for 16-bit interfaces) Reserved. Set as default OF_SEL[3:0].
- Page 74 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0x07 Autodetect AD_PAL_EN. PAL B/G/I/H autodetect Disable nable enable. Enable AD_NTSC_EN. NTSC autodetect Disable enable. Enable AD_PALM_EN. PAL M autodetect Disable enable. Enable AD_PALN_EN. PAL N autodetect Disable enable. Enable AD_P60_EN. PAL60 autodetect Disable enable.
- Page 75 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0x0F Power Reserved. Set to default Management PDBP. Power-down bit priority Chip power-down selects between PWRDN bit and PIN. controlled by pin Bit has priority (pin disregarded) Reserved. Set to default PWRDN. Power-down places the System functional decoder in a full power-down mode.
- Page 76 ADV7181B Bits Subaddress Register Bit Description Comments Notes Analog 0x14 Reserved. Set to default Clamp CCLEN. Current clamp enable allows Current sources switched Control the user to switch off the current sources in the analog front. Current sources enabled Reserved. Set to default 0x15 Digital...
- Page 77 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0x18 Shaping WYSFM[4:0]. Wideband Y shaping Reserved; do not use Filter filter mode allows the user to select Reserved; do not use Control 2 which Y shaping filter is used for the SVHS 1 Y component of Y/C, YPbPr, B/W SVHS 2...
- Page 78 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0x27 Pixel Delay LTA[1:0]. Luma timing adjust allows No delay CVBS mode Control the user to specify a timing difference LTA[1:0] = 00b; Luma 1 clk (37 ns) delayed between chroma and luma samples. S-Video mode Luma 2 clk (74 ns) early LTA[1:0]= 01b,...
- Page 79 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0x2D Chroma CMG[11:8]. Chroma manual gain can CAGC[1:0] settings Gain be used to program a desired decide in which Control 1 manual chroma gain. Reading back mode CMG[11:0] from this register in AGC mode gives operates.
- Page 80 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0x34 HS Position HSE[10:8]. HS end allows the HS output ends HSE[10:0] Using HSB and Control 1 positioning of the HS output within pixels after the falling edge HSE,the user can the video line. of Hsync program the position and length...
- Page 81 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0x39 PAL Comb YCMP[2:0]. Luma comb mode, PAL. Adaptive 5-line, 3-tap Control luma comb Use low-pass notch Fixed luma comb Top lines of memory. Fixed luma comb (5-line) All lines of memory. Fixed luma comb (3-line) Bottom lines of memory.
- Page 82 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0x41 Resample Reserved. Set to default Control SFL_INV. Controls the behavior of SFL compatible with the PAL switch bit. ADV7190/ADV7191/ ADV7194 encoders SFL compatible with ADV717x/ADV7173x encoders Reserved. Set to default 0x48 Gemstar GDECEL[15:8].
- Page 83 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0x51 Lock Count CIL[2:0]. Count-into-lock determines 1 line of video the number of lines the system must 2 lines of video remain in lock before showing a 5 lines of video locked status. 10 lines of video 100 lines of video 500 lines of video...
- Page 84 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0x99 CCAP1 CCAP1[7:0] CCAP1[7] contains parity (Read Only) Closed caption data register. bit for byte 0 0x9A CCAP2 CCAP2[7:0] CCAP2[7] contains parity (Read Only) Closed caption data register. bit for byte 0 0x9B Letterbox 1 LB_LCT[7:0]...
- Page 85 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0xC4 ADC2_SW[3:0]. Manual muxing No connection SETADC_sw_ SWITCH 2 control for ADC2. man_en = 1. No connection No connection No connection No connection AIN6 No connection No connection No connection No connection No connection No connection No connection...
- Page 86 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0xE6 NTSC V Bit NVEND[4:0]. How many lines after NTSC default (BT.656) rollover to set V low. COUNT NVENDSIGN. Set to low when manual programming Not suitable for user programming NVENDDELE. Delay V bit going low No delay by one line relative to NVEND (even Additional delay by 1 line...
- Page 87 ADV7181B Bits Subaddress Register Bit Description Comments Notes 0xF4 Drive DR_STR_S[1:0]. Select the drive Low drive strength (1x) Strength strength for the Sync output signals. Medium-low drive strength (2x) Medium-high drive strength (3x) High drive strength (4x) DR_STR_C[1:0]. Select the drive Low drive strength (1x) strength for the Clock output signal.
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Page 88: I 2 C Programming Examples
ADV7181B C PROGRAMMING EXAMPLES EXAMPLES FOR 28 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN6) All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8. Table 86. Mode 1 CVBS Input Register Address Register Value Notes 0x15... -
Page 89: Changes To Table 86
ADV7181B Mode 2 S-Video Input (Y on AIN1 and C on AIN4) All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 87. Mode 2 S-Video Input Register Address Register Value Notes 0x00 0x06 S-Video input. 0x15 0x00 Slow down digital clamps. -
Page 90: Changes To Table 87
ADV7181B Mode 3 525i/625i YPrPb Input (Y on AIN1, Pr on AIN3, and Pb on AIN5) All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 88. Mode 3 YPrPb Input 525i/625i Register Address Register Value Notes 0x00 0x0A... -
Page 91: Changes To Table 88
ADV7181B Mode 4 CVBS Tuner Input CVBS PAL on AIN6 All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 89. Mode 4 Tuner Input CVBS PAL Only Register Address Register Value Notes 0x00 0x80 Force PAL input only mode. -
Page 92: Examples For 27 Mhz Clock
ADV7181B EXAMPLES FOR 27 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN6) All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8. Table 90. Mode 1 CVBS Input Register Address Register Value Notes 0x15 0x00 Slow down digital clamps. - Page 93 ADV7181B Mode 3 525i/625i YPrPb Input (Y on AIN1, Pr on AIN3, and Pb on AIN5) All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 92. Mode 3 YPrPb Input 525i/625i Register Address Register Value Notes 0x00 0x0A...
- Page 94 ADV7181B Mode 4 CVBS Tuner Input CVBS PAL on AIN6 All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 92. Mode 4 Tuner Input CVBS PAL Only Register Address Register Value Notes 0x00 0x80 Force PAL input only mode.
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Page 95: Pcb Layout Recommendations
ADV7181B PCB LAYOUT RECOMMENDATIONS The ADV7181B is a high precision, high speed mixed-signal It is also recommended to use a single ground plane for the device. To achieve the maximum performance from the part, it entire board. This ground plane should have a space between the analog and digital sections of the PCB (see Figure 41). -
Page 96: Digital Inputs
ADV7181B DIGITAL INPUTS CRYSTAL LOAD CAPACITOR VALUE SELECTION The digital inputs on the ADV7181B are designed to work with Figure 43 shows an example reference clock circuit for the a 3.3 V signals, and are not tolerant of 5 V signals. Extra compo- ADV7181B. -
Page 97: Typical Circuit Connection
ADV7181B TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7181B video decoder are shown in Figure 44 and Figure 45. For a detailed schematic diagram for the ADV7181B, refer to the ADV7181B evaluation note. AVDD_5V 0 Ω BUFFER 4.7k Ω 100 μ... -
Page 98: Replaced Figure 45
ADV7181B FERRITE BEAD DVDDIO (3.3V) POWER SUPPLY 33μF 10μF 0.1μF 0.01μF DECOUPLING FOR EACH POWER PIN DGND DGND DGND DGND FERRITE BEAD PVDD (1.8V) POWER SUPPLY 33μF 10μF 0.1μF 0.01μF DECOUPLING FOR EACH POWER PIN AGND AGND AGND AGND FERRITE BEAD AVDD (3.3V) POWER SUPPLY... -
Page 99: Outline Dimensions
ADV7181B OUTLINE DIMENSIONS 0.30 9.00 0.25 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 INDICATOR PIN 1 INDICATOR * 7.25 8.75 EXPOSED PAD 7.10 SQ BSC SQ (BOTTOM VIEW) VIEW 6.95 0.45 0.40 0.35 0.25 MIN 7.50 0.80 MAX 1.00 THE EXPOSED METAL PADDLE ON THE 12°... -
Page 100: Ordering Guide
220°C to 235°C. Z = Pb-free part. Purchase of licensed I C components of Analog Devices or one of its sublicensed AssociatedCompanies conveys a license for the purchaser under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
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