Analog Devices ADV7181BCP Manual page 44

ADV7181B
622
OUTPUT
VIDEO
H
V
PVBEG[4:0] = 0x5
F
310
OUTPUT
VIDEO
H
V
PVBEG[4:0] = 0x5
F
622
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
FIELD
OUTPUT
310
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
FIELD
OUTPUT
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FIELD 1
623 624 625 1 2
PFTOG[4:0] = 0x3
FIELD 2
311 312 313 314 315
PFTOG[4:0] = 0x3
Figure 25. PAL Default (BT.656). The Polarity of H, V, and F is Embedded in the Data
FIELD 1
623 624 1 2
625
FIELD 2
311 312 313 314 315
PVBEG[4:0] = 0x1
Figure 26. PAL Typical Vsync/Field Positions Using Register Writes in Table 56
3 4 5 6 7
316 317 318 319 320
3 4 5 6 7
PVBEG[4:0] = 0x1 PVEND[4:0] = 0x4
316 317 318 319 320
PVEND[4:0] = 0x4
Rev. B | Page 44 of 100
8 9 10 22 23
PVEND[4:0] = 0x4
321 322 335 336 337
PVEND[4:0] = 0x4
8 9 10 11 23
PFTOG[4:0] = 0x6
321 322 323 336 337
PFTOG[4:0] = 0x6
24
24