Analog Devices ADV7181BCP Manual page 69

Subaddress Register
0x44 Interrupt
Mask 1
Read/Write
Register
Register
Access
Page 2
0x45 Reserved
0x46 Interrupt
Status 2
Read Only
Register
Register
Access
Page 2
0x47 Interrupt
Clear 2
Write Only
Register
Access
Page 2
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Bit Description 7
SD_LOCK_MSKB.
SD_UNLOCK_MSKB.
Reserved.
Reserved.
Reserved.
SD_FR_CHNG_MSKB.
MV_PS_CS_MSKB.
Reserved. x
x
CCAPD_Q.
GEMD_Q.
CGMS_CHNGD_Q.
WSS_CHNGD_Q.
Reserved.
Reserved.
Reserved.
MPU_STIM_INTRQ_Q. 0
1
CCAPD_CLR.
GEMD_CLR.
CGMS_CHNGD_CLR.
WSS_CHNGD_CLR.
Reserved.
Reserved.
Reserved.
MPU_STIM_INTRQ_CLR. 0
1
Bit
6 5 4 3 2 1 0
0
1
0
1
0
0
0
0
1
0
1
x x x x x x x
0
1
0
1
0
1
0
1
x
x
x
0
1
0
1
0
1
0
1
x
x
x
Rev. B | Page 69 of 100
ADV7181B
Comments
Masks SD_LOCK_Q bit
Unmasks SD_LOCK_Q bit
Masks SD_UNLOCK_Q bit
Unmasks SD_UNLOCK_Q bit
Not used
Not used
Not used
Masks SD_FR_CHNG_Q bit
Unmasks SD_FR_CHNG_Q bit
Masks MV_PS_CS_Q bit
Unmasks MV_PS_CS_Q bit
Not used
Closed captioning not detected
in the input video signal
Closed captioning data detected
in the video input signal
Gemstar data not detected in
the input video signal
Gemstar data detected in the
input video signal
No change detected in CGMS
data in the input video signal
A change is detected in the
CGMS data in the input video
signal
No change detected in WSS
data in the input video signal
A change is detected in the WSS
data in the input video signal
Not used
Not used
Not used
Manual interrupt not set
Manual interrupt set
Do not clear
Clears CCAPD_Q bit
Do not clear
Clears GEMD_Q bit
Do not clear
Clears CGMS_CHNGD_Q bit
Do not clear
Clears WSS_CHNGD_Q bit
Not used
Not used
Not used
Do not clear
Clears MPU_STIM_INTRQ_Q bit
Notes
These bits
can be
cleared or
masked by
Registers
0x47 and
0x48,
respectively.