I 2 C Register Map Details; Changes To Table 84; Changes To Table 83 - Analog Devices ADV7181BCP Manual

2
I C REGISTER MAP DETAILS
The following registers are located in Register Access Page 2.
Table 83. Interrupt Register Map Bit Names
Register Reset
Name Value
Interrupt 0001 x000
Config 0
Reserved
Interrupt
Status 1
Interrupt x000 0000
Clear 1
Interrupt x000 0000
Maskb 1
Reserved
Interrupt
Status 2
Interrupt 0xxx 0000
Clear 2
Interrupt 0xxx 0000
Maskb 2
Raw Status 3
Interrupt
Status 3
Interrupt xx00 0000
Clear 3
Interrupt xx00 0000
Maskb 3
1 To access the Interrupt Register map, the bits of the register access page[1:0] in Register Address 0x0E must be programmed to 01b.
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1
Subaddress
rw Bit 7
Dec Hex
rw 64 0x40 INTRQ_
DUR_SEL.1
65 0x41
r 66 0x42
w 67 0x43
rw 68 0x44
69 0x45
r 70 0x46 MPU_
STIM_
INTRQ_Q
w 71 0x47 MPU_
STIM_INT
RQ_CLR
rw 72 0x48 MPU_
STIM_INT
RQ_MSKB
r 73 0x49
r 74 0x4A
w 75 0x4B
rw 76 0x4C
Bit 6 Bit 5 Bit 4
INTRQ_ MV_INTRQ MV_INTRQ
_SEL.1 _SEL.0
DUR_SEL.0
MV_PS_ SD_FR_
CS_Q CHNG_Q
MV_PS_ SD_FR_
CS_CLR CHNG_CLR
MV_PS_ SD_FR_
CS_MSKB CHNG_
MSKB
SCM_
LOCK
PAL_SW_ SCM_
LK_ LOCK_
CHNG_Q CHNG_Q
PAL_SW_ SCM_
LK_CHNG LOCK_
_CLR CHNG_CLR
PAL_SW_ SCM_
LK_CHNG LOCK_CH
_MSKB NG_MSKB
Rev. B | Page 67 of 100
ADV7181B
Bit 3 Bit 2 Bit 1
MPU_ INTRQ_
STIM_INTRQ OP_SEL.1
SD_
UNLOCK_Q
SD_UNLO
CK_CLR
SD_
UNLOCK_
MSKB
WSS_ CGMS_ GEMD_Q
CHNGD_Q CHNGD_Q
WSS_ CGMS_ GEMD_
CHNGD_ CHNGD_ CLR
CLR CLR
WSS_CHN CGMS_ GEMD_
GD_MSKB CHNGD_ MSKB
MSKB
SD_H_ SD_V_
LOCK LOCK
SD_AD_ SD_H_ SD_V_
CHNG_Q LOCK_ LOCK_
CHNG_Q CHNG_Q
SD_AD_ SD_H_ SD_V_LO
CHNG_ LOCK_ CK_CHNG
CLR CHNG_CLR _CLR
SD_AD_ SD_H_ SD_V_
CHNG_ LOCK_CH LOCK_CH
MSKB NG_MSKB NG_MSKB
Bit 0
INTRQ_
OP_SEL.0
SD_LOCK_
Q
SD_LOCK
_CLR
SD_LOCK
_MSKB
CCAPD_Q
CCAPD_
CLR
CCAPD_
MSKB
SD_OP_
50HZ
SD_OP_
CHNG_Q
SD_OP_
CHNG_CLR
SD_OP_
CHNG_
MSKB