Analog Devices ADV7181BCP Manual page 70

ADV7181B
Subaddress Register
0x48 Interrupt
Mask 2
Read/
Write
Register
Access
Page 2
0x49 Raw
Status 3
Read Only
Register
Register
Access
Page 2
0x4A Interrupt
Status 3
Read Only
Register
Register
Access
Page 2
Downloaded from Elcodis.com electronic components distributor
Bit Description 7
CCAPD_MSKB.
GEMD_MSKB.
CGMS_CHNGD_MSKB.
WSS_CHNGD_MSKB.
Reserved.
Reserved.
Reserved.
MPU_STIM_INTRQ_MSKB. 0
SD_OP_50Hz.
SD 60/50Hz frame rate at
output.
SD_V_LOCK.
SD_H_LOCK.
Reserved.
SCM_LOCK.
SECAM Lock.
Reserved.
Reserved.
Reserved. x
SD_OP_CHNG_Q.
SD 60/50 Hz frame rate at
input.
SD_V_LOCK_CHNG_Q.
SD_H_LOCK_CHNG_Q.
SD_AD_CHNG_Q.
SD autodetect changed.
SCM_LOCK_CHNG_Q.
SECAM Lock.
PAL_SW_LK_CHNG_Q.
Reserved.
Reserved. x
Bit
6 5 4 3 2 1 0
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
1
x
0
1
x
x
0
1
0
1
0
1
x
0
1
x
x
Rev. B | Page 70 of 100
Comments
Masks CCAPD_Q bit
Unmasks CCAPD_Q bit
Masks GEMD_Q bit
Unmasks GEMD_Q bit
Masks CGMS_CHNGD_Q bit
Unmasks CGMS_CHNGD_Q bit
Masks WSS_CHNGD_Q bit
Unmasks WSS_CHNGD_Q bit
Not used
Not used
Not used
Masks MPU_STIM_INTRQ_Q bit
Unmasks MPU_STIM_INTRQ_Q
bit
SD 60 Hz signal output
SD 50 Hz signal output
SD vertical sync lock not
established
SD vertical sync lock established
SD horizontal sync lock not
established
SD horizontal sync lock
established
Not used
SECAM lock not established
SECAM lock established
Not used
Not used
Not used
No change in SD signal standard
detected at the input
A change in SD signal standard
is detected at the input
No change in SD vertical sync
lock status
SD vertical sync lock status has
changed
No change in SD horizontal sync
lock status
SD horizontal sync lock status
has changed
No change in AD_RESULT[2:0]
bits in Status Register 1
AD_RESULT[2:0] bits in Status
Register 1 have changed
No change in SECAM lock status
SECAM lock status has changed
No change in PAL swinging
burst lock status
PAL swinging burst lock status
has changed
Not used
Not used
Notes
These bits
cannot be
cleared or
masked.
Register
0x4A is used
for this
purpose.
These bits
can be
cleared and
masked by
Registers
0x4B and
0x4C,
respectively.