Analog Devices ADV7181BCP Manual page 58

ADV7181B
INTRQ_OP_SEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space)[1:0]
Table 76. INTRQ_OP_SEL
INTRQ_OP_SEL[1:0]
00
01
10
11
Multiple Interrupt Events
If Interrupt Event 1 occurs and then Interrupt Event 2 occurs
before the system controller has cleared or masked Interrupt
Event 1, the ADV7181B does not generate a second interrupt
signal. The system controller should check all unmasked
interrupt status bits since more than one can be active.
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Description
Open drain (default)
Drive low when active
Drive high when active
Reserved
Macrovision Interrupt Selection Bits
The user can select between pseudo sync pulse and color stripe
detection as follows:
MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection
Bits, Address 0x40 (Interrupt Space)[5:4]
Table 77. MV_INTRQ_SEL
MV_INTRQ_SEL[1:0]
00
01
10
11
Additional information relating to the interrupt system is
detailed in Table 83.
Rev. B | Page 58 of 100
Description
Reserved
Pseudo sync only (default)
Color stripe only
Either pseudo sync or color stripe