Analog Devices ADV7181BCP Manual page 83

Subaddress Register
0x51 Lock Count
0x8F Free Run
Line
Length 1
0x90 VBI Info
(Read
Only)
0x91 WSS1
(Read Only)
0x92 WSS2
(Read Only)
0x93 EDTV1
(Read Only)
0x94 EDTV2
(Read Only)
0x95 EDTV3
(Read Only)
0x96 CGMS1
(Read Only)
0x97 CGMS2
(Read Only)
0x98 CGMS3
(Read Only)
Downloaded from Elcodis.com electronic components distributor
Bit Description
CIL[2:0]. Count-into-lock determines
the number of lines the system must
remain in lock before showing a
locked status.
COL[2:0]. Count-out-of-lock
determines the number of lines the
system must remain out-of-lock
before showing a lost-locked status.
SRLS. Select raw lock signal. Selects
the determination of the locked
status.
FSCLE. Fsc lock enable.
Reserved.
LLC_PAD_SEL[2:0]. Enables manual
selection of clock for LLC1 pin.
Reserved.
WSSD. Screen signaling detected.
CCAPD. Closed caption data.
EDTVD. EDTV sequence.
CGMSD. CGMS sequence.
Reserved.
WSS1[7:0]
Wide screen signaling data.
WSS2[7:0]
Wide screen signaling data.
EDTV1[7:0]
EDTV data register.
EDTV2[7:0]
EDTV data register.
EDTV3[7:0]
EDTV data register.
CGMS1[7:0]
CGMS data register.
CGMS2[7:0]
CGMS data register.
CGMS3[7:0]
CGMS data register.
Bits
7 6 5 4 3 2 1 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
0
1
0 0 0 0
0 0 0
1 0 1
0
0
1
0
1
0
1
0
1
x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
Rev. B | Page 83 of 100
ADV7181B
Comments Notes
1 line of video
2 lines of video
5 lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100000 lines of video
1 line of video
2 lines of video
5 lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100000 lines of video
Over field with vertical
info
Line-to-line evaluation
Lock status set only by
horizontal lock
Lock status set by
horizontal lock and
subcarrier lock
Set to default
LLC1 (nominal 27 MHz)
selected out on LLC1 pin
LLC2 (nominally 13.5 MHz) For 16-bit 4:2:2 out,
selected out on LLC1 pin OF_SEL[3:0] = 0010.
Set to default
No WSS detected Read only status
bits.
WSS detected
No CCAP signals detected
CCAP sequence detected
No EDTV sequence
detected
EDTV sequence detected
No CGMS transition
detected
CGMS sequence decoded
WSS2[7:6] are
undetermined
EDTV3[7:6] are EDTV3[5] is reserved
undetermined for future use.
CGMS3[7:4] are
undetermined