Evaluating the ad5340 12-bit single-channel voltage output digital-to-analog converter (dac) (13 pages)
Summary of Contents for Analog Devices AD9257
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Though the information on this page applies generally to the currently released version of the AD9257-65EBZ and AD9637-80EBZ, the specifics (i.e. photos, jumper labels, etc.) are for the soon-to-be-released version. Information specifically for the released version can be found here quickstartguide_ad9257_ad9637_prb.pdf.
Figure 1. Evaluation Board Connection—AD9257-65EBZ AD9637-80EBZ (on Left) and HSC-ADC-EVALCZ (on Right) Features Full featured evaluation board for the AD9257/AD9637 SPI interface for setup and control External, on-board oscillator, or AD9517 clocking option Balun/transformer or amplifier input drive option On-board LDO regulator or switching regulator, needing a single external 6V, 2A dc supply VisualAnalog®...
Use a shielded, RG-58, 50Ω coaxial cable (optimally 1 m or shorter) to connect the signal generator. For best results, use a narrow-band, band-pass filter with 50Ω terminations and an appropriate center frequency. (Analog Devices, Inc. uses TTE, Allen Avionics, and K&L band-pass filters.)
(see the Specifications section in the data sheet of the respective part). When connecting the analog input source, use of a multipole, narrow-band band-pass filter with 50Ω terminations is recommended. Analog Devices uses band-pass filters from TTE and K&L Microwave, Inc. Connect the filters directly to the evaluation board.
Output Signals The default setup uses the Analog Devices high speed converter evaluation platform ( HSC-ADC-EVALCZ) for data capture. The serial LVDS outputs from the ADC are routed to Connector P1302 using 100Ω differential traces. For more information on the data capture board and its optional settings, visit www.analog.com/hsadcevalboard.
Figure 2. Default Jumper Connections for AD9257-65EBZ/AD9637-80EBZ Board Evaluation Board Circuitry This section explains the default and optional ADC settings or modes allowed on the AD9257-65EBZ and the AD9637-80EBZ boards. Power Connect the switching power supply that is supplied in the evaluation kit between a rated 100V ac to 240V ac, 47Hz to 63Hz wall outlet and P101.
The clock input is 50 Ω terminated and ac-coupled to handle single-ended sinusoidal inputs. The transformer converts the single-ended input to a differential signal that is clipped by CR1101 before entering the ADC clock inputs. The AD9257 AD9637 ADCs are equipped with an internal 8:1 clock divider to facilitate usage with higher frequency clocks.
1.8V_DUT_AVDD (jumper J301 Pin 5 to Pin 6) 10 0000 0000 0000 Note that the above settings only apply when CSB is tied high (J301 Pin 8 “floating”) at power up. Additional information on the Standalone (PIN) Mode is provided in the AD9257 AD9637 data sheets.
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Figure 3. VisualAnalog, New Canvas Window After the template is selected, a message might appear asking if the default configuration can be used to program the FPGA (see Figure 4). If this message appears, click Yes, and the window closes. Figure 4.
Figure 6. VisualAnalog, Main Window Expanded Display Evaluation And Test Setting up the SPI Controller Software After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure: Open the SPI controller software by going to the Start menu or by double-clicking the SPIController software desktop icon.
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Figure 7. SPI Controller, CHIP ID(1) Box Click the New DUT button in the SPIController window (see Figure 8) Figure 8. SPI Controller, New DUT Button Rev 13 Nov 2013 00:23 | Page 11...
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In the ADCBase 0 tab of the SPIController window, find the CLOCK DIVIDE(B) box (see Figure 9), and the MODES(8) box (see Figure 10). If using the clock divider, use the drop-down box to select the correct clock divide ratio, if necessary. If there is any interruption of the ADC clock during power-up or during operation, a Digital Reset may be needed to re-initialize the ADC (Figure 10).
The next step is to adjust the amplitude of the input signal for each channel as follows: Adjust the amplitude of the input signal so that the fundamental is at the desired level. Examine the Fund Power reading in the left panel of the VisualAnalog Graph - AD9257 FFT window (see Figure 13).
13. Graph Window of VisualAnalog Repeat this procedure for the other channels, if desired Click the floppy-disk icon within the VisualAnalog Graph - AD9257 FFT window to save the performance data as a .csv formatted file for plotting or analysis.
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