Analog Devices ADV7181BCP Manual page 65

Register
Name Bit 7
Luma Gain LMG.7
Control 2
Vsync Field
Control 1
Vsync Field VSBHO
Control 2
Vsync Field VSEHO
Control 3
Hsync
Position
Control 1
Hsync HSB.7
Position
Control 2
Hsync HSE.7
Position
Control 3
Polarity PHS
NTSC Comb CTAPSN.1
Control
PAL Comb CTAPSP.1
Control
ADC Control
Reserved
Manual
Window
Control
Reserved
Resample
Control
Reserved
Gemstar Ctrl 1 GDECEL.15
Gemstar Ctrl 2 GDECEL.7
Gemstar Ctrl 3 GDECOL.15
Gemstar Ctrl 4 GDECOL.7
Gemstar Ctrl 5
CTI DNR Ctrl 1
CTI DNR Ctrl 2 CTI_C_TH.7
Reserved
CTI DNR Ctrl 4 DNR_TH.7
Lock Count FSCLE
Reserved
Free Run Line
Length 1
Reserved
VBI Info
WSS 1 WSS1.7
WSS 2 WSS2.7
EDTV 1 EDTV1.7
EDTV 2 EDTV2.7
EDTV 3 EDTV3.7
CGMS 1 CGMS1.7
CGMS 2 CGMS2.7
CGMS 3 CGMS3.7
CCAP 1 CCAP1.7
CCAP 2 CCAP2.7
Letterbox 1 LB_LCT.7
Letterbox 2 LB_LCM.7
Letterbox 3 LB_LCB.7
Reserved
CRC Enable
Reserved
ADC Switch 1 ADC1_SW.3
ADC Switch 2 ADC_SW_M AN
Reserved
Downloaded from Elcodis.com electronic components distributor
Bit 6 Bit 5
LMG.6 LMG.5
VSBHE
VSEHE
HSB.10 HSB.9
HSB.6 HSB.5
HSE.6 HSE.5
PVS
CTAPSN.0 CCMN.2
CTAPSP.0 CCMP.2
CKILLTHR.2 CKILLTHR.1
SFL_INV
GDECEL.14 GDECEL.13
GDECEL.6 GDECEL.5
GDECOL.14 GDECOL.13
GDECOL.6 GDECOL.5
DNR_EN
CTI_C_TH.6 CTI_C_TH.5
DNR_TH.6 DNR_TH.5
SRLS COL.2
LLC_PAD_SEL.2 LLC_PAD_SEL.1
WSS1.6 WSS1.5
WSS2.6 WSS2.5
EDTV1.6 EDTV1.5
EDTV2.6 EDTV2.5
EDTV3.6 EDTV3.5
CGMS1.6 CGMS1.5
CGMS2.6 CGMS2.5
CGMS3.6 CGMS3.5
CCAP1.6 CCAP1.5
CCAP2.6 CCAP2.5
LB_LCT.6 LB_LCT.5
LB_LCM.6 LB_LCM.5
LB_LCB.6 LB_LCB.5
ADC1_SW.2 ADC1_SW.1
Rev. B | Page 65 of 100
Bit 4 Bit 3
LMG.4 LMG.3
NEWAVMODE HVSTIM
HSB.8
HSB.4 HSB.3
HSE.4 HSE.3
PF
CCMN.1 CCMN.0
CCMP.1 CCMP.0
PWRDN_AD C_0
CKILLTHR.0
GDECEL.12 GDECEL.11
GDECEL.4 GDECEL.3
GDECOL.12 GDECOL.11
GDECOL.4 GDECOL.3
CTI_AB.1
CTI_C_TH.4 CTI_C_TH.3
DNR_TH.4 DNR_TH.3
COL.1 COL.0
LLC_PAD_SEL.0
CGMSD
WSS1.4 WSS1.3
WSS2.4 WSS2.3
EDTV1.4 EDTV1.3
EDTV2.4 EDTV2.3
EDTV3.4 EDTV3.3
CGMS1.4 CGMS1.3
CGMS2.4 CGMS2.3
CGMS3.4 CGMS3.3
CCAP1.4 CCAP1.3
CCAP2.4 CCAP2.3
LB_LCT.4 LB_LCT.3
LB_LCM.4 LB_LCM.3
LB_LCB.4 LB_LCB.3
ADC1_SW.0 ADC0_SW.3
ADC2_SW.3
ADV7181B
Bit 2 Bit 1
LMG.2 LMG.1
HSE.10 HSE.9
HSB.2 HSB.1
HSE.2 HSE.1
YCMN.2 YCMN.1
YCMP.2 YCMP.1
PWRDN_AD C_1 PWRDN_ADC_2
GDECEL.10 GDECEL.9
GDECEL.2 GDECEL.1
GDECOL.10 GDECOL.9
GDECOL.2 GDECOL.1
CTI_AB.0 CTI_AB_EN
CTI_C_TH.2 CTI_C_TH.1
DNR_TH.2 DNR_TH.1
CIL.2 CIL.1
EDTVD CCAPD
WSS1.2 WSS1.1
WSS2.2 WSS2.1
EDTV1.2 EDTV1.1
EDTV2.2 EDTV2.1
EDTV3.2 EDTV3.1
CGMS1.2 CGMS1.1
CGMS2.2 CGMS2.1
CGMS3.2 CGMS3.1
CCAP1.2 CCAP1.1
CCAP2.2 CCAP2.1
LB_LCT.2 LB_LCT.1
LB_LCM.2 LB_LCM.1
LB_LCB.2 LB_LCB.1
CRC_ENABLE
ADC0_SW.2 ADC0_SW.1
ADC2_SW.2 ADC2_SW.1
Bit 0
LMG.0
HSE.8
HSB.0
HSE.0
PCLK
YCMN.0
YCMP.0
GDECEL.8
GDECEL.0
GDECOL.8
GDECOL.0
GDECAD
CTI_EN
CTI_C_TH.0
DNR_TH.0
CIL.0
WSSD
WSS1.0
WSS2.0
EDTV1.0
EDTV2.0
EDTV3.0
CGMS1.0
CGMS2.0
CGMS3.0
CCAP1.0
CCAP2.0
LB_LCT.0
LB_LCM.0
LB_LCB.0
ADC0_SW.0
ADC2_SW.0