ADLINK Technology SMARC LEC-MTK-I1200 User Manual
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ADLINK Technology SMARC LEC-MTK-I1200 User Manual

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COM-HPC-sIDH User's Guide
LEC-MTK-I1200
Page 1
User's Guide
Revision:
Rev. 0.1
Date:
2023-06-01
Part Number:
50M-72516-1000
Copyright © 2023 ADLINK Technology, Inc.
PICMG COM-HPC R1.1

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Summary of Contents for ADLINK Technology SMARC LEC-MTK-I1200

  • Page 1 COM-HPC-sIDH User’s Guide PICMG COM-HPC R1.1 LEC-MTK-I1200 User’s Guide Revision: Rev. 0.1 Date: 2023-06-01 Part Number: 50M-72516-1000 Page 1 Copyright © 2023 ADLINK Technology, Inc.

  • Page 2: Revision History

    LEC-MTK-i1200 User’s Guide SGET SMARC Rev 2.1 Revision History Revision Description Date Author Preliminary release 2023-06-01 Page 2 copyright © 2023 ADLINK Technology Inc.

  • Page 3: Preface

    Product names mentioned herein are used for identification purposes only and may be trademarks / registered trademarks of respective companies. Copyright © 2023 ADLINK Technology Incorporated This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
  • Page 4 Caution: This information indicates the possibility of minor physical injury, component damage, data loss, and/or program corruption. Warning: This information warns of possible serious physical injury, component damage, data loss, and/or program corruption. Page 4 copyright © 2023 ADLINK Technology Inc.
  • Page 5 ADLINK Technology GmbH Hans-Thoma-Strasse 11, D-68163 Mannheim, Germany Tel: +49-621-43214-0 Fax: +49-621 43214-30 Email: emea@adlinktech.com Please visit the Contact page at www.adlinktech.com for information on how to contact the ADLINK regional office nearest you. Page 5 copyright © 2023 ADLINK Technology Inc.

  • Page 6: Table Of Contents

    2.9 Debug Header DB30 ........................................................15 2.10 Fan Control ............................................................15 2.11 Power ..............................................................15 2.12 Mechanical and Environmental ....................................................16 3. Block Diagram ............................................................17 4. Pinout and Signal Descriptions ......................................................18 Page 6 copyright © 2023 ADLINK Technology Inc.
  • Page 7 5. Software Support ............................................................. 56 5.1 Yocto ..............................................................56 5.2 Android ..............................................................56 5.3 AI ................................................................56 6. Mechanical ..............................................................57 7. Thermal Solutions ............................................................ 58 7.1 Heatspreader: HTS ........................................................... 58 7.2 Heatsink: THS ............................................................. 59 Page 7 copyright © 2023 ADLINK Technology Inc.
  • Page 8 Figure 1 – Module function diagram ...................................................... 17 Figure 2 – Module top/botom side pin numbering ................................................. 18 Figure 3 – Module Dimensions ......................................................... 57 Figure 4 – Heatspreader HTS ........................................................58 Figure 5 – Heatsink THS ..........................................................59 Page 8 copyright © 2023 ADLINK Technology Inc.

  • Page 9: Introduction

    The modular approach allows scalability, faster time to market and upgradability while still maintaining low costs, low power, and small physical size. SMARC module and carrier specifications are available online at: https://www.sget.org/standards/smarc.html Note: This module is compliant with the new 2.1.1 pinout. Page 9 copyright © 2023 ADLINK Technology Inc.

  • Page 10: Specifications

    LPDDR4X SDRAM @2133MHz supporting up to 16GB system memory down L2 Cache System L2 cache (ECC), 256KB/core for Cortex-A78, 128KB per core for Cotex-A55 L3 Cache Shared 2MB L3 cache Security Arm TrustZone security, TPM 2.0 (optional) Page 10 copyright © 2023 ADLINK Technology Inc.

  • Page 11: Video

    Image resizer, scaling ratio range 1/128 to 64 Image sharpening Preference color tuning Graphics 3D graphic accelerator capable of processing 17600M pixel/sec @880MHz • OpenGL ES 3.2/2.0/1.1 • Vulkan 1.1/1.0 • OpenCL 2.2 • Page 11 copyright © 2023 ADLINK Technology Inc.

  • Page 12: Camera

    Displayport 1.4, 4K p60 2.3 Camera Supports CSI0 2-lane and CSI1 4-lane MIPI CSI2 camera input over MXM connector. CSI2 on module feature connector (4 lanes) 2.4 Audio Supports on-carrier I S codec Page 12 copyright © 2023 ADLINK Technology Inc.

  • Page 13: Dual Ethernet

    1x PCI Express Gen3 x1/x, 1x PCI Express Gen2 x1 2x USB 3.0/2.0, 2x USB 2.0 coming from USB hub, 2 x USB 2.0 coming from SoC UART 4x UART interfaces SER0,1,2,3 (SER2 derives from USB2UART) Page 13 copyright © 2023 ADLINK Technology Inc.

  • Page 14: System Storage

    GPIO 14 x GPIO with interrupt, one GPIO with PWM 2.8 System Storage SDIO 1x SDIO (4-bit) compatible with SD3.0, MMC version 4.51 to edge connector UFS Storage Up to 256GB UFS Page 14 copyright © 2023 ADLINK Technology Inc.

  • Page 15: Debug Header Db30

    2.9 Debug Header DB30 Multipurpose Connector: ADLINK standard 30-pin FPC with following pins Boot Select strap pins Serial port 2.10 Fan Control Passive cooling, no fan control pins 2.11 Power 5.0V +/- 5% Page 15 copyright © 2023 ADLINK Technology Inc.

  • Page 16: Mechanical And Environmental

    EN55022 Class B inside an enclosure Shock and Vibration MIL-STD-202F, Method 213B, Table 213-I, Condition A. MIL-STD-202F, Method 214A, Table 214-I, Condition D. MTBF 300,000 hrs (at 40°C), 100,000 hrs (at 85°C), Page 16 copyright © 2023 ADLINK Technology Inc.

  • Page 17: Block Diagram

    SDIO SDIO TPM 2.0 SER 0,1,2,3 UART PCIe x1 BT / Wi-Fi USB P1 4x I Power Management LITE CSI_0/1 APU system (APU + VPU) CSI_2 Figure 1 – Module function diagram Page 17 copyright © 2023 ADLINK Technology Inc.

  • Page 18: Pinout And Signal Descriptions

    The below table is a comprehensible list of all signal pins on the MXM 3 connector in the standard specification SMARC 2.1. Signals not supported on LEC-MTK-i1200 are strikethrough STRIKETHROUGH Top Side Bottom Side P156 S156 Figure 2 – Module top/botom side pin numbering Page 18 copyright © 2023 ADLINK Technology Inc.
  • Page 19 USB3_SSTX+ GBE0_CTREF GBE1_CTREF USB0_VBUS_DET USB3_SSTX- GBE0_MDI0- PCIE_D_TX+ / USB0_OTG_ID GBE0_MDI0+ PCIE_D_TX- / SERDES_1_TX- USB1+ USB3_SSRX+ SPI0_CS1# GBE1_LINK_ACT# USB1- USB3_SSRX- PCIE_D_RX+ / USB1_EN_OC# SDIO_WP PCIE_D_RX- / USB3+ SDIO_CMD USB2+ USB3- SDIO_CD# USB4+ USB2- Page 19 copyright © 2023 ADLINK Technology Inc.
  • Page 20 P134 SER1_TX S134 LVDS0_CK+/eDP0_AUX/ P100 S100 DP0_LANE2- P135 SER1_RX S135 LVDS0_CK-/eDP0_AUX-/ P101 HDMI_CK+ / DP1_LANE3+ S101 P136 SER2_TX S136 P102 HDMI_CK- / DP1_LANE3- S102 DP0_LANE3+ P137 SER2_RX S137 LVDS0_3+ / eDP0_TX3+ / Page 20 copyright © 2023 ADLINK Technology Inc.
  • Page 21 CAN0_RX S144 eDP0_HPD / DSI0_TE P155 VDD_IN S155 FORCE_RECOV# P145 CAN1_TX S145 WDT_TIME_OUT# P156 VDD_IN S156 BATLOW# P146 CAN1_RX S146 PCIE_WAKE# S157 TEST# S158 P147 VDD_IN S147 VDD_RTC P148 VDD_IN S148 LID# Page 21 copyright © 2023 ADLINK Technology Inc.

  • Page 22: Signal Terminology Descriptions

    Module is in its lowest power state Runtime Module is full on. CARRIER_PWRON is high and CARRIER_SBY# is NOT active (i.e. both signals are high) Standby Module is in standby state or higher Page 22 copyright © 2023 ADLINK Technology Inc.

  • Page 23: Signal Description By Function

    LCD1_VDD_EN LCD1_VDD_EN S127 LCD0_BKLT_EN LCD0_BKLT_EN LCD0_BKLT_EN S107 LCD1_BKLT_EN LCD1_BKLT_EN LCD1_BKLT_EN S141 LCD0_BKLT_PWM LCD0_BKLT_PWM LCD0_BKLT_PWM S122 LCD1_BKLT_PWM LCD1_BKLT_PWM LCD1_BKLT_PWM S144 DSI0_TE eDP0_HPD S113 DSI1_TE eDP1_HPD S139 I2C_LCD_CK I2C_LCD_CK I2C_LCD_CK S140 I2C_LCD_DAT I2C_LCD_DAT I2C_LCD_DAT Page 23 copyright © 2023 ADLINK Technology Inc.
  • Page 24 Runtime Not supported DSI1_CLK- S109 D-PHY LCD1_VDD_EN S116 Secondary panel power enable, active high 1.8V Runtime Not supported CMOS LCD1_BKLT_EN S107 Secondary panel backlight enable, active 1.8V Runtime Not supported high CMOS Page 24 copyright © 2023 ADLINK Technology Inc.
  • Page 25 Primary panel power enable, active high 1.8V Runtime CMOS LCD0_BKLT_EN S127 Primary panel backlight enable, active high 1.8V Runtime CMOS LCD0_BKLT_PWM S141 Primary panel brightness control through 1.8V Runtime pulse width modulation (PWM) CMOS Page 25 copyright © 2023 ADLINK Technology Inc.
  • Page 26 Possible EDID EEPROM address conflicts may CMOS occur if multiple displays are implemented I2C_LCD_CK S139 I2C clock to read LCD display EDID EEPROMs 1.8V Runtime PU 2k2 Possible conflict if 2 panels are used CMOS Page 26 copyright © 2023 ADLINK Technology Inc.

  • Page 27: Secondary Display Interface

    The pull-ups may be part of an integrated HDMI ESD protection and control-line level shift device, such as the Texas Instruments TPD12S016. If discrete Carrier pull-ups are used, the value depends on the individual carrier board implementation. Page 27 copyright © 2023 ADLINK Technology Inc.
  • Page 28 Pulled to GND on Carrier for DP operation in Dual Mode or DP output CMOS (DP++) implementations. Driven to 1.8V on carrier for HDMI mode. Module must tolerate high level in stand- by mode Page 28 copyright © 2023 ADLINK Technology Inc.
  • Page 29 1.8V Runtime Shared with GPIO0 GPIO0 output. CAM0_RST# / P110 Camera 0 reset, active low output O CMOS 1.8V Runtime Shared with GPIO2 GPIO2 CAM_MCK Master clock output O CMOS 1.8V Runtime Page 29 copyright © 2023 ADLINK Technology Inc.
  • Page 30 Shared with GPIO 3 GPIO3 CAM_MCK Master clock output O CMOS 1.8V Runtime Note: MediaTek has support for up to 3 cameras. The 3 camera goes to a feature connector on the module as CSI2. Page 30 copyright © 2023 ADLINK Technology Inc.
  • Page 31 Module Input if CPU acts in Slave Mode AUDIO_MCK Master clock output to I2S 1.8V Runtime Shared with I2S2 codec(s) CMOS Note: Support for I2S1 signalling has been removed during update to SMARC 2.0 specification Page 31 copyright © 2023 ADLINK Technology Inc.
  • Page 32 USB over-current sense for port 2 I/O OD 3.3V Standby PU 10k Pulled low by Module OD driver to disable USB2 power. note 1 CMOS Pulled low by Carrier OD driver to indicate over-current situation. Page 32 copyright © 2023 ADLINK Technology Inc.
  • Page 33 1. 3.3V or switched 3.3V — when an USB channel is not used, then USB[0:5]_EN_OC# pull-up rails may be held at GND to prevent current leak. 2. USB0 directly connects to the SoC and offers OTG, others share bandwidth through an USB 2.0/3.1 hub. Page 33 copyright © 2023 ADLINK Technology Inc.
  • Page 34 PCIe Port B reset output 3.3V Runtime CMOS PCIE_B_CKREQ# PCIe Port B clock request I OD 3.3V Runtime Can be used for power saving mode on PCIe - CMOS Pulled up or terminated on Module Page 34 copyright © 2023 ADLINK Technology Inc.
  • Page 35 GBE0_SDP IEEE 1588 Trigger Signal. For hardware implementation 3.3V Standby of PTP (precision time protocol) CMOS Note 1: LAN_0 port comes from SoC RGMII interface while LAN_1 port derives from USB (optional) Page 35 copyright © 2023 ADLINK Technology Inc.
  • Page 36 (if required by the Module GBE PHY)` GBE1_SDP IEEE 1588 Trigger Signal. For hardware implementation 3.3V Standby of PTP (precision time protocol) CMOS Note: Second optional LAN port comes from USB 3.1 Page 36 copyright © 2023 ADLINK Technology Inc.
  • Page 37 SDIO_PWR_EN SDIO Power Enable. This signal is used to 3.3V Runtime should be driven low in STB Mode by the enable the power being supplied to a SD/MMC card CMOS module device. Page 37 copyright © 2023 ADLINK Technology Inc.
  • Page 38 MISO can also be used as ESPI_IO_1 SPI1_DO SPI1 Master output / Slave input O CMOS 1.8V Standby also referred to as MOSI can also be used as ESPI_IO_0 Page 38 copyright © 2023 ADLINK Technology Inc.
  • Page 39 General purpose I/O pin 13 1.8V Runtime PU 470K CMOS Note: Allows for in-SoC Pull-Ups. These can be ≤ 10k. Max 2.2k PD should be implemented on Carrier when needing low levels. Page 39 copyright © 2023 ADLINK Technology Inc.
  • Page 40 Driven by OD on Carrier WDT_TIME_OUT# S145 Watch-Dog-Timer Output, low active. 1.8V Runtime CMOS PWM_OUT P113 Pulse Width Modulation (PWM) 1.8V Runtime PU 470K GPIO5 is the default pin configuration / GPIO5 output CMOS Page 40 copyright © 2023 ADLINK Technology Inc.
  • Page 41 Active low, level CMOS Pulled up on module. sensitive. Should be debounced on the Module. RESET_OUT# P126 General purpose reset output to Carrier board. 1.8V Standby CMOS Page 41 copyright © 2023 ADLINK Technology Inc.
  • Page 42 On x86 systems these serve as SMB CMOS Sleep CLK. Pulled up on module. SMB_ALERT_1V8# SMBus Alert# (interrupt) signal I OD 1.8V to 5V Standby/ PU 2k2 only used on x86 design CMOS Sleep Page 42 copyright © 2023 ADLINK Technology Inc.
  • Page 43 SOC native Force Recovery mode – such as over a Serial Port. For x86 systems this signal may be used to load BIOS defaults. Pulled up on Module. Driven by OD part on Carrier. Page 43 copyright © 2023 ADLINK Technology Inc.
  • Page 44 P Not defined within Signal [2 to 3.25] / 3.25V power – 3.0V nominal. May be Terminolgy Descriptions. sourced from a Carrier based Should we define a specific Lithium cell or Super Cap. rail? Page 44 copyright © 2023 ADLINK Technology Inc.

  • Page 45: Smarc Pin-To-Controller Mapping

    GPIO / 3.3V DP83867IRRGZR LED_1 GBE0_LINK1000# GPIO / 3.3V DP83867IRRGZR LED_2 GBE0_MDI2- GBE MDI DP83867IRRGZR TD_M_C GBE0_MDI2+ GBE MDI DP83867IRRGZR TD_P_C GBE0_LINK_ACT# GPIO / 3.3V DP83867IRRGZR LED_0 GBE0_MDI1- GBE MDI DP83867IRRGZR TD_M_B Page 45 copyright © 2023 ADLINK Technology Inc.
  • Page 46 SPI0_DO SPI / 1.8V MT8395 SPIM1_MO ALT1 SATA_TX+ SATA_TX- SATA_RX+ SATA_RX- ESPI_CS0# / SPI1_CS0# SPI / 1.8V MT8395 SPIM2_CSB ALT1 ESPI_CS1# / SPI1_CS1# ESPI_CK / SPI1_CK SPI / 1.8V MT8395 SPIM2_CLK ALT1 Page 46 copyright © 2023 ADLINK Technology Inc.
  • Page 47 MT8395 PCIE_PERESET_N ALT1 USB4_EN_OC# GPIO / 3.3V USB5807C/KD PRT_CTL5/GPIO21 PCIE_B_CKREQ# PCIE_A_CKREQ# PU-10K PCIE / 3.3V MT8395 PCIE_CLKREQ_N ALT1 PCIE_C_REFCK+ PCIE_C_REFCK- PCIE_A_REFCK+ PCIe MT8395 PCIEG3_CLKP PCIE_A_REFCK- PCIe MT8395 PCIEG3_CLKN PCIE_A_RX+ PCIe MT8395 PCIEG3_LN0_RXP Page 47 copyright © 2023 ADLINK Technology Inc.
  • Page 48 MT8395 GPIO ALT0 P113 GPIO5 / PWM_OUT PU-470K GPIO / 1.8V MT8395 GPIO ALT0 P114 GPIO6 / TACHIN GPIO / 1.8V MT8395 GPIO ALT0 P115 GPIO7 PU-470K GPIO / 1.8V SX1509BIULTRT I/O1 Page 48 copyright © 2023 ADLINK Technology Inc.
  • Page 49 SER3_TX UART / 1.8V MT8395 UTXD3 ALT4 P141 SER3_RX UART / 1.8V MT8395 URXD3 ALT4 P142 P143 MCP2518FDT- CAN0_TX CAN / 1.8V TXCAN E/QBB P144 MCP2518FDT- CAN0_RX CAN / 1.8V RXCAN E/QBB Page 49 copyright © 2023 ADLINK Technology Inc.
  • Page 50 I2C / 1.8V MT8395 SDA0 ALT1 CSI0_CK+ MT8395 CSI1A_L1P_T0C CSI0_CK- MT8395 CSI1A_L1N_T1A CSI0_RX0+ MT8395 CSI1A_L0P_T0A CSI0_RX0- MT8395 CSI1A_L0N_T0B CSI0_RX1+ MT8395 CSI1A_L2P_T1B CSI0_RX1- MT8395 CSI1A_L2N_T1C GBE1_MDI0+ GBE MDI LAN7800/VSX TR0P GBE1_MDI0- GBE MDI LAN7800/VSX TR0N Page 50 copyright © 2023 ADLINK Technology Inc.
  • Page 51 I2S0_SDOUT I2S/ 1.8V MT8395 I2SO1_D0 ALT1 I2S0_SDIN I2S / 1.8V MT8395 I2SIN_D0 ALT1 I2S0_CK I2S / 1.8V MT8395 I2SO1_BCK ALT1 ESPI_ALERT0# ESPI_ALERT1# MDIO_CLK MDIO_DAT I2C_GP_CK PU-2.2K I2C / 1.8V MT8395 SCL3 ALT1 Page 51 copyright © 2023 ADLINK Technology Inc.
  • Page 52 USB2_SSTX+ USB / 3.3V USB5807C/KD USB3DN_TXDP3 USB2_SSTX- USB / 3.3V USB5807C/KD USB3DN_TXDM3 USB2_SSRX+ USB / 3.3V USB5807C/KD USB3DN_RXDP3 USB2_SSRX- USB / 3.3V USB5807C/KD USB3DN_RXDM3 PCIE_B_RST# PCIE_C_RST# PCIE_C_RX+ / SERDES_2_RX+ PCIE PI3PCIE3415AZHEX DOa+ Page 52 copyright © 2023 ADLINK Technology Inc.
  • Page 53 PI3PCIE3415AZHEX PCIE_B_TX- PCIE PI3PCIE3415AZHEX DP0_LANE0+ DP0_LANE0- DP0_AUX_SEL DP0_LANE1+ DP0_LANE1- DP0_HPD DP0_LANE2+ S100 DP0_LANE2- S101 S102 DP0_LANE3+ S103 DP0_LANE3- S104 USB3_OTG_ID S105 DP0_AUX+ S106 DP0_AUX- S107 LCD1_BKLT_EN GPIO / 1.8V MT8395 GPIO ALT0 Page 53 copyright © 2023 ADLINK Technology Inc.
  • Page 54 S125 LVDS0_0+ / eDP0_TX0+ / eDP/DSI TMUXHS4212IRKSR DSI0_D0+ S126 LVDS0_0- / eDP0_TX0- / eDP/DSI TMUXHS4212IRKSR DSI0_D0- S127 LCD0_BKLT_EN GPIO / 1.8V MT8395 GPIO ALT0 S128 LVDS0_1+ / eDP0_TX1+ / eDP/DSI TMUXHS4212IRKSR DSI0_D1+ Page 54 copyright © 2023 ADLINK Technology Inc.
  • Page 55 PU-10K GPIO / 5V From Carrier board S151 CHARGING# PU-10K GPIO / 1.8V From Carrier board S152 CHARGER_PRSNT# PU-10K GPIO / 1.8V From Carrier board S153 CARRIER_STBY# GPIO / 1.8V Logic IC Page 55 copyright © 2023 ADLINK Technology Inc.

  • Page 56: Software Support

    LEC-MTK-i1200 User’s Guide SGET SMARC Rev 2.1 5. Software Support 5.1 Yocto Latest release supported 5.2 Android Android 13 5.3 AI Supports Arm NN and TFlite models Page 56 copyright © 2023 ADLINK Technology Inc.

  • Page 57: Mechanical

    LEC-MTK-i1200 User’s Guide SGET SMARC Rev 2.1 6. Mechanical Figure 3 – Module Dimensions Page 57 copyright © 2023 ADLINK Technology Inc.

  • Page 58: Thermal Solutions

    7.1 Heatspreader: HTS Sustainable temperature range with high performance LAB copper heatsink with high airflow = -40 to 85°C ambient M3 x 4pcs ؈ 2.7mm x 4pcs Figure 4 – Heatspreader HTS Page 58 copyright © 2023 ADLINK Technology Inc.

  • Page 59: Heatsink: Ths

    LEC-MTK-i1200 User’s Guide SGET SMARC Rev 2.1 7.2 Heatsink: THS Sustainable temperature range with moderate airflow = 0 to 60°C ambient ؈ 2.7mm x 4pcs Figure 5 – Heatsink THS Page 59 copyright © 2023 ADLINK Technology Inc.

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