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All About the Logic Analyzer Training Board
Jumpers
The glitch is generated using the delay between the falling edge of D4 and
rising edge of D5 of the ripple counter, and the delay using R2 with the input
capacitance of the 74F02N. The ripple counter is a 74HC393. A 74F02 is
used to generate the pulse (glitch) and combine it with D7 of the ripple
counter. Because the 74F02 is a fast CMOS gate, it boosts the amplitude of
the glitch it receives from the 74HC393 counter. This combination of logic
families produces a positive glitch that is about 6 ns wide and has an
amplitude of about 4 volts. The glitch is available on channel D7 of J1 and J2
when the GLITCH jumper is set to ON.
Jumpers
The jumpers are used to turn the glitch on and off and to select the sources
for state clocks 1 (CLK1) and 2 (CLK2).
Glitch
When the GLITCH jumper is set to OFF, the waveform on D7 of J1 and J2 is
the most significant bit of the counter. When this jumper is set to ON, a
glitch appears on D7 and the waveform no longer represents the most
significant bit of the counter. The glitch always appears on the test point
labeled GLITCH, regardless of the position of this jumper.
CLK1
The CLK1 jumper selects the source of state clock 1. If you choose OSC (the
default), the source of the clock will be the oscillator on the training board. If
you choose P.G., the source of the clock will be Strobe 2 or D7 of the pattern
generator, depending on which pattern generator pod you have connected to
the training board.
CLK2
The CLK2 jumper selects the source of state clock 2 for the HP 16540A used
in an HP 16500 system. If you choose OSC, the source of the clock will be
the oscillator on the training board. If you choose P.G. (the default), the
source of the clock will be Strobe 2 or D7 of the pattern generator, depending
on which pattern generator pod you have connected to the training board.
12-3
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