Page 1 Service Guide Publication number 01660-97002 First edition, August 1993 For Safety information, Warranties, and Regulatory information, see the pages at the end of the book. © Copyright Hewlett-Packard Company 1987–1993 All Rights Reserved. HP 1660 Series Logic Analyzers...
Page 2 Notice Hewlett-Packard to Agilent Technologies Transition This manual may contain references to HP or Hewlett-Packard. Please note that Hewlett- Packard’s former test and measurement, semiconductor products and chemical analysis businesses are now part of Agilent Technologies. To reduce potential confusion, the only change to product numbers and names has been in the company name prefix: where a product name/number was HP XXXX the current name/number is now Agilent XXXX.
Page 3 HP 1660A Series and HP 1660AS Series Logic Analyzers The HP 1660A Series are 100-MHz State/500-MHz Timing Logic Analyzers. The HP 1660AS Series include all the features of the HP 1660A Series, as well as a 2-channel, 1 GSa/s oscilloscope. Feat ur es...
Page 4 The HP 1660-series Logic Analyzer...
Page 5 In This Book This book is the service guide for the HP 1660 Series Logic Analyzers and is divided into eight chapters. Chapter 1 contains information about the logic analyzer and includes accessories, specifications and characteristics, and equipment required for servicing.
Page 6: Table Of Contents
Contents 1 1 Gener al I nf or mat i on Gener al I nf or mat i on Accessories 1-2 Specifications ( logic analyzer) 1-3 Specifications ( oscilloscope) 1-4 Characteristics ( logic analyzer) 1-5 Characteristics ( oscilloscope) 1-5 Supplemental Characteristics ( logic analyzer) 1-6 Supplemental Characteristics ( oscilloscope) 1-9 Recommended Test Equipment ( Logic Analyzer) 1-13 Recommended Test Equipment ( Oscilloscope) 1-14...
Page 7 Contents To test the single-clock, single-edge, state acquisition ( logic analyzer) 3-23 Set up the equipment 3-23 Set up the logic analyzer 3-24 Connect the logic analyzer 3-25 Verify the test signal 3-28 Check the setup/hold combination 3-30 Test the next channels 3-34 To test the multiple-clock, multiple-edge, state acquisition ( logic analyzer) 3-35 Set up the equipment 3-35 Set up the logic analyzer 3-36...
Page 8 Contents To test the voltage measurement accuracy ( oscilloscope) 3-72 Set up the equipment 3-72 Set up the logic analyzer 3-73 Connect the logic analyzer 3-74 Acquire the data 3-75 To test the offset accuracy ( oscilloscope) 3-76 Set up the equipment 3-76 Set up the logic analyzer 3-77 Connect the logic analyzer 3-78 Acquire the zero input data 3-79...
Page 9 To remove and replace the switch actuator assembly 6-8 To remove and replace the rear panel assembly 6-9 To remove and replace the acquisition board ( oscilloscope board for HP 1660AS-series) 6-10 To remove and replace the front panel and keyboard 6-11...
Page 10 Contents 8 8 Theor y of Oper at i on Theor y of Oper at i on Block-Level Theory 8-3 The HP 1660 Series Logic Analyzer 8-3 The Logic Acquisition Board 8-6 The Oscilloscope Board 8-9 Self-Tests Description 8-12 Power-up Self-Tests 8-12...
Page 12 Accessories 1-2 Specifications ( logic analyzer) 1-3 Specifications ( oscilloscope) 1-4 Characteristics ( logic analyzer) 1-5 Characteristics ( oscilloscope) 1-5 Supplemental Characteristics ( logic analyzer) 1-6 Supplemental Characteristics ( oscilloscope) 1-9 Recommended Test Equipment ( logic analyzer) 1-13 Recommended Test Equipment ( oscilloscope) 1-14 General Information...
Page 13: Accessories
3 - 1661A. 1661AS 2 - 1662A. 1662AS 1 - 1663A. 1663AS In addition to the above, the following accessories are supplied with the HP 1660AS Series Logic Analyzers. Accessor i es Suppl i ed Accessor i es Suppl i ed...
Page 14: Specifications (Logic Analyzer)
General Information Specifications (logic analyzer) Specifications (logic analyzer) The specifications are the performance standards against which the product is tested. Maximum State Speed 100 MHz Minimum State Clock Pulse Width 3.5 ns Minimum Master to Master Clock Time 10.0 ns Minimum Glitch Width* 3.5 ns ±...
Page 15: Specifications (Oscilloscope)
General Information Specifications (oscilloscope) Specifications (oscilloscope) The HP 1660AS Logic Analyzers also include the following specifications: ( *,1) Bandwidth DC to 250 MHz ( real time, dc-coupled) ( *,3,6) ± [( 0.005% X ∆t) + Time Interval Measurement Accuracy − 6...
Page 16: Characteristics (Logic Analyzer)
HP 1660A/AS HP 1661A/AS HP 1662A/AS HP 1663A/AS * For all modes except glitch. Characteristics (oscilloscope) The HP 1660AS Logic Analyzers also include the following characteristics: Maximum Sample Rate 1 Gigasample per second Number of Channels ( 2) Rise Time 1.4 ns...
Page 17: Supplemental Characteristics (Logic Analyzer)
Timing Sequence Levels Maximum Occurrence Counter Value 1,048,575 Pattern Recognizers Maximum Pattern Width 136 channels in HP 1660A, 102 channels in HP 1661A, 68 channels in HP 1662A, 34 channels in HP 1663A Range Recognizers Range Width 32 bits each Timers...
Page 18 Ti mi ng Wavefor m Pattern readout of timing waveforms at X or O marker. Ti mi ng Wavefor m Bases Binary, Octal, Decimal, Hexadecimal, ASCII ( display only) , Two’s Complement, Bases and User-defined symbols. Symbol s 1,000 maximum. Symbols can be downloaded over RS-232 or HP-IB. Symbol s 1–7...
Page 19 General Information Supplemental Characteristics (logic analyzer) Mar ker Funct i ons Mar ker Funct i ons Ti me I nt er val Ti me I nt er val The X and O markers measure the time interval between a point on a timing waveform and the trigger, two points on the same timing waveform, two points on different waveforms, or two states ( time tagging on) .
Page 20: Supplemental Characteristics (Oscilloscope)
General Information Supplemental Characteristics (oscilloscope) Pr oduct Regul at i ons Pr oduct Regul at i ons Safety IEC 348 UL 1244 CSA Standard C22.2 No.231 ( Series M-89) This product meets the requirement of the European Communities ( EC) EMC Directive 89/336/EEC. Emissions EN55011/CSIPR 11 ( ISM, Group1,Class A equipment) SABS RAA Act No.
Page 21 General Information Supplemental Characteristics (oscilloscope) Tr i gger i ng Tr i gger i ng Trigger Level Range Within display window ( full scale and offset) Trigger Modes Immediate Triggers immediately after arming condition is met. Edge Triggers on rising or falling edge of any internal channel, count adjustable from 1 to 32,000.
Page 22 General Information Supplemental Characteristics (oscilloscope) Wavefor m Di spl ay Wavefor m Di spl ay Displayed Waveforms Eight waveform windows maximum, with scrolling across 96 waveforms. Display Formats Waveforms can be displayed in an overlapping and/or non-overlapping format. Display capability of A− B and A+B is also provided.
Page 23 General Information Supplemental Characteristics (oscilloscope) Measur ement and Di spl ay Funct i ons Measur ement and Di spl ay Funct i ons Ti me Mar ker s Ti me Mar ker s Two vertical markers, X and O, are provided for measurements of time and voltage.
Page 24: Recommended Test Equipment (Logic Analyzer)
Equipment Critical Specifications Recommended Model/Part Pulse Generator 100 MHz, 3.5 ns pulse width, HP 8131A Option 020 < 600 ps rise time ≥ 6 GHz bandwidth, < 58 ps rise time Digitizing Oscilloscope HP 54121T − 6 Accuracy ≤ (5)(10 ) ×...
Page 25: Recommended Test Equipment (Oscilloscope)
Use* Model/Part Signal Generator Frequency: 1 - 250 MHz at approx . HP 8656B Option 001 170 mV RMS Output Accuracy: ± 1 dB 1 MHz time base accuracy 0.25 ppm Range: − 35.000 to +35.000 Vdc, ± 1 mV...
Page 26 To inspect the logic analyzer 2-2 To apply power 2-3 To operate the user interface 2-3 To set the line voltage 2-3 To degauss the display 2-4 To clean the logic analyzer 2-4 To test the logic analyzer 2-4 Preparing for Use...
Page 27: To Inspect The Logic Analyzer
Preparing For Use This chapter gives you instructions for preparing the logic analyzer for use. Power Requi r ement s Power Requi r ement s The logic analyzer requires a power source of either 115 Vac or 230 Vac, –22 % to +10 %, single phase, 48 to 66 Hz, 200 Watts maximum power.
Page 28: To Apply Power
HP 1660 Ser i es Logi c Analyzer User ’s Refer ence. To set the HP-IB address or to configure for RS-232C, refer to the HP 1660 Ser i es Logi c Analyzer User ’s Refer ence.
Page 29: To Degauss The Display
Preparing for Use To degauss the display Reinsert the fuse module with the arrow for the appropriate line voltage aligned with the arrow on the line filter assembly switch. Reconnect the power cord. Turn on the instrument by setting the power switch to the On position.
Page 30 To perform the self-tests 3-3 To make the test connectors ( logic analyzer) 3-6 To test the threshold accuracy ( logic analyzer) 3-8 To test the glitch capture ( logic analyzer) 3-17 To test the single-clock, single-edge, state acquisition ( logic analyzer) 3-23 To test the multiple-clock, multiple-edge, state acquisition ( logic analyzer) 3-35 To test the single-clock, multiple-edge, state acquisition ( logic analyzer) 3-47 To test the time interval accuracy ( logic analyzer) 3-59...
Page 31 To select a field on the logic analyzer screen, use the arrow keys to highlight the field, then press the Select key. For more information about the logic analyzer interface, refer to the HP 1660 Ser i es Logi c Analyzer User ’s Refer ence. Test St r at egy...
Page 32: To Perform The Self-Tests
The performance verification ( PV) self-tests consist of system PV tests, analyzer PV tests, and oscilloscope PV tests ( HP 1660AS series only) . Disconnect all inputs, then turn on the power switch. Wait until the power-up tests are complete.
Page 33 Testing Performance To perform the self-tests Install a formatted disk that is not write protected into the disk drive. Connect an RS-232C loopback connector onto the RS-232C port. Select All System Tests. You can run all tests at one time, except for the Front Panel Test and Display Test, by running All System Tests.
Page 34 Record the results of the tests on the performance test record at the end of this chapter. For the HP 1660AS-series Logic Analyzers, Select Sys PV, then select Scope PV in the pop-up menu. In the Scope PV menu, select Functional Tests then select All Tests.
Page 35: To Make The Test Connectors (Logic Analyzer)
To make the test connectors (logic analyzer) The test connectors connect the logic analyzer to the test equipment. Materials Required Description Recommended Part BNC (f) Connector HP 1250-1032 100 Ω 1% resistor HP 0698-7212 Berg Strip, 17-by-2 Berg Strip, 6-by-2 20:1 Probe...
Page 36 Testing Performance To make the test connectors (logic analyzer) Build one test connector using a BNC connector and a 17-by-2 section of Berg strip. a a Solder a jumper wire to all pins on one side of the Berg strip. b b Solder a jumper wire to all pins on the other side of the Berg strip.
Page 37: To Test The Threshold Accuracy (Logic Analyzer)
Digital Multimeter 0.1 mV resolution, 0.005% accuracy HP 3458A − 6 Accuracy ≤ (5)(10 ) × frequency, Function Generator HP 3325B Option 002 DC offset voltage ± 6.3 V BNC-Banana Cable HP 11001-60001 BNC Tee HP 1250-0781 BNC Cable HP 10503A...
Page 38: Set Up The Logic Analyzer
Testing Performance To test the threshold accuracy (logic analyzer) Set up the logic analyzer Press the Config key. Unassign Pods 3 and 4, Pods 5 and 6, and Pods 7 and 8. To unassign the pods, select the pod field. In the pop-up menu, select Unassigned. Connect the logic analyzer Using the 17-by-2 test connector, BNC cable, and probe tip assembly, connect the data and clock channels of pod 1 to one side of the BNC Tee.
Page 39: Test The Ttl Threshold
Testing Performance To test the threshold accuracy (logic analyzer) Test the TTL threshold Press the Format key. Select the field to the right of Pod 1, then select TTL in the pop-up menu. On the function generator front panel, enter 1.750 V ± 1 mV DC offset. Use the multimeter to verify the voltage.
Page 40 Testing Performance To test the threshold accuracy (logic analyzer) Using the Modify up arrow on the function generator, increase offset voltage in 1-mV increments until all activity indicators for pod 1 show the channels at a logic high. Record the function generator voltage in the performance test record. 3–11...
Page 41: Test The Ecl Threshold
Testing Performance To test the threshold accuracy (logic analyzer) Test the ECL threshold Select the field to the right of Pod 1, then select ECL in the pop-up menu. On the function generator front panel, enter − 1.160 V ± 1 mV DC offset. Use the multimeter to verify the voltage.
Page 42: Test The - User Threshold
Testing Performance To test the threshold accuracy (logic analyzer) Test the − User threshold Move the cursor to the field to the right of Pod 1. Type –6.00, then use the left and right cursor control keys to highlight V. Press the Select key. On the function generator front panel, enter −...
Page 43 Testing Performance To test the threshold accuracy (logic analyzer) Test the + User threshold Move the cursor to the field to the right of Pod 1. Type +6.00, then use the left and right cursor control keys to highlight V. Press the Select key. On the function generator front panel, enter +6.282 V ±...
Page 44: Test The 0 V User Threshold
Testing Performance To test the threshold accuracy (logic analyzer) Test the 0 V User threshold Move the cursor to the field to the right of Pod 1. Type 0, then press the Select key. On the function generator front panel, enter +0.102 V ± 1 mV DC offset. Use the multimeter to verify the voltage.
Page 45: Test The Next Pod
Testing Performance To test the threshold accuracy (logic analyzer) Test the next pod Using the 17-by-2 test connector and probe tip assembly, connect the data and clock channels of the next pod to the output of the function generator until all pods have been tested.
Page 46: To Test The Glitch Capture (Logic Analyzer)
Equipment Required Equipment Critical Specifications Recommended Model/Part Pulse Generator 100 MHz 3.5 ns pulse width, < 600 ps rise time HP 8131A Option 020 ≥ 6 GHz bandwidth , < 58 ps rise time Digitizing HP 54121T Oscilloscope SMA Coax...
Page 47: Set Up The Logic Analyzer
Testing Performance To test the glitch capture (logic analyzer) Set up the oscilloscope. Oscilloscope Setup Time Base Display Delta V Delta T Time/Div: 1.00 ns/div mode: avg V markers on T markers on delay: 17.7000 ns # of avg: 16 marker 1 position: Chan 1 start on: Pos Edge 1 screens: dual...
Page 48 Testing Performance To test the glitch capture (logic analyzer) The table includes all the HP 1660 Series. Use the pods that correspond to your logic analyzer: • HP 1660A – pods 1 through 8 • HP 1661A – pods 1 and 2, pods 3 and 4, and pods 5 and 6 •...
Page 49: Test The Glitch Capture On The Connected Channels
Testing Performance To test the glitch capture (logic analyzer) Test the glitch capture on the connected channels Set up the Format menu. a a Press the Format key. b b Select the field to the right of each pod, then select ECL in the pop-up menu. Use the knob to access pods not shown on the screen (to activate the knob for pods, use the cursor to select the Pods field and push Select).
Page 50 Testing Performance To test the glitch capture (logic analyzer) Set up the Trigger menu. a a Press the Trigger key. b b Select Clear Trigger, then select All. Using the Precision Edge Find in the Delta T menu of the oscilloscope, verify that the pulse widths of the pulse generator channels 1 and 2 are 3.450 ns, +50 ps or −...
Page 51: Test The Next Channels
Testing Performance To test the glitch capture (logic analyzer) On the logic analyzer, press the Run key. The display should be similar to the figure below. On the pulse generator, enable Channel 1 and Channel 2 COMP (with the LED on). On the logic analyzer, press the Run key.
Page 52: To Test The Single-Clock, Single-Edge, State Acquisition (Logic Analyzer)
Equipment Required Equipment Critical Specifications Recommended Model/Part Pulse Generator 100 MHz 3.5 ns pulse width, < 600 ps rise time HP 8131A option 020 ≥ 6 GHz bandwidth, < 58 ps rise time Digitizing Oscilloscope HP 54121T Adapter SMA(m)-BNC(f) HP 1250-1200...
Page 53: Set Up The Logic Analyzer
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Set up the oscilloscope. Oscilloscope Setup Time Base Display Delta V Delta T Time/Div: 1.00 ns/div V markers on T markers on # of avg: 16 marker 1 position: Chan 1 start on: Pos Edge 1 screen: dual marker 2 position: Chan 1...
Page 54 "anystate," then select "no state." Select Done to exit the State Sequence Levels menu. d d Select the field next to "a," under the label Lab1. Type the following for your logic analyzer, then press the Select key. HP 1660A–"00AA" HP 1662A–"00AA" HP 1661A–"002A"...
Page 55: Connect The Logic Analyzer
Using the 6-by-2 test connectors, connect the first combination of logic analyzer clock and data channels listed in one of the following tables to the pulse generator. If you are testing an HP 1660A or HP 1661A, you will repeat this test for the second combination.
Page 56 Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Connect the HP 1662A or HP 1663A Logic Analyzer to the Pulse Generator Testing Connect to Connect to Connect to Combination HP 8131A HP 8131A HP 8131A Channel 1 Output...
Page 57: Verify The Test Signal
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Verify the test signal Check the clock pulse width. Using the oscilloscope, verify that the clock pulse width is 3.50 ns, +0 ps or − 100 ps. a a Enable the pulse generator channel 1 and channel 2 outputs. b b In the oscilloscope Timebase menu, select Delay.
Page 58 Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Check the data pulse width. Using the oscilloscope, verify that the data pulse width is 3.50 ns, +0 ps or − 100 ps. a a Enable the pulse generator channel 1 and channel 2 outputs. Leave channel 2 output disabled.
Page 59: Check The Setup/Hold Combination
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Check the setup/hold combination Select the logic analyzer setup/hold time. a a In the logic analyzer Format menu, select Master Clock. b b Select the Setup/Hold field, then select the setup/hold combination to be tested for all pods.
Page 60 Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) c c Adjust the pulse generator channel 1 Delay, then select Precision Edge Find in the oscilloscope Delta T menu. Repeat this step until the pulses are aligned according to the setup time of the setup/hold combination selected, +0.0 ps or −...
Page 61 Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Note: This step is only done the first time through the test, to create a Compare file. For subsequent runs, go to step 6. Use the following to create a Compare file: a a Press Run.
Page 62 Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Using the Delay mode of the pulse generator channel 1, position the pulses according to the setup/hold combination selected, +0.0 ps or − 100 ps. a a In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set Marker 1 at −...
Page 63: Test The Next Channels
Testing Performance To test the single-clock, single-edge, state acquisition (logic analyzer) Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record.
Page 64: To Test The Multiple-Clock, Multiple-Edge, State Acquisition (Logic Analyzer)
Equipment Required Equipment Critical Specifications Recommended Model/Part Pulse Generator 100 MHz 3.5 ns pulse width, < 600 ps rise time HP 8131A option 020 ≥ 6 GHz bandwidth, < 58 ps rise time Digitizing Oscilloscope HP 54121T Adapter SMA(m)-BNC(f) HP 1250-1200...
Page 65: Set Up The Logic Analyzer
To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Set up the oscilloscope. Oscilloscope Setup Time Base Display Delta V Delta T Time/Div: 1.00 ns/div V markers on T markers on # of avg: 16 marker 1 position: Chan 1 start on: Pos Edge 1 screen: dual marker 2 position: Chan 1...
Page 66 "anystate", then select "no state." Select Done to exit the State Sequence Levels menu. d d Select the field next to the pattern recognizer "a," under the label Lab1. Type the following for your logic analyzer, then press Select. HP 1660A–"00AA" HP 1662A–"00AA" HP 1661A–"002A"...
Page 67: Connect The Logic Analyzer
Using the 6-by-2 test connectors, connect the first combination of logic analyzer clock and data channels listed in one of the following tables to the pulse generator. If you are testing an HP 1660A or HP 1661A, you will repeat this test for the second combination.
Page 68 To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Connect the HP 1662A or HP 1663A Logic Analyzer to the Pulse Generator Testing Connect to Connect to Connect to Connect to Combination HP 8131A HP 8131A HP 8131A HP 8131A...
Page 69: Verify The Test Signal
To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Verify the test signal Check the clock pulse width. Using the oscilloscope, verify that the clock pulse width is 3.50 ns, +0 ps or − 100 ps. a a Enable the pulse generator channel 1 and channel 2 outputs (with the LED off). b b In the oscilloscope Timebase menu, select Delay.
Page 70 To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Check the data pulse width. Using the oscilloscope verify that the data pulse width is 4.450 ns, +50 ps or − 100 ps. a a In the oscilloscope Timebase menu, select Sweep Speed 1.00 ns/div. b b Select Delay.
Page 71: Check The Setup/Hold With Single Clock Edges, Multiple Clocks
To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Check the setup/hold with single clock edges, multiple clocks Select the logic analyzer setup/hold time. a a In the logic analyzer Format menu, select Master Clock. b b Select and activate any two clock edges. c c Select the Setup/Hold field and select the setup/hold to be tested for all pods.
Page 72 To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) c c Adjust the pulse generator channel 1 Delay, then select Precision Edge Find in the oscilloscope Delta T menu. Repeat this step until the pulses are aligned according to the setup time of the setup/hold combination selected, +0.0 ps or − 100 ps. Select the clocks to be tested.
Page 73 To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) If you have not already created a Compare file for the previous test (single-clock, 5 5 5 5 single-edge state acquisition, page 32), use the following steps to create one. For subsequent passes through this test, skip this step and go to step 6.
Page 74 To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Using the Delay mode of the pulse generator channel 1, position the pulses according to the setup time of the setup/hold combination selected, +0.0 ps or − 100 ps. a a In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set Marker 1 at −...
Page 75: Test The Next Channels
To test the multiple-clock, multiple-edge, state acquisition (logic analyzer) Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtained without the "Stop Condition Satisfied" message appearing, then the test passes. Press Stop to halt the acquisition. Record the Pass or Fail results in the performance test record.
Page 76: To Test The Single-Clock, Multiple-Edge, State Acquisition (Logic Analyzer)
Equipment Required Equipment Critical Specifications Recommended Model/Part Pulse Generator 100 MHz 3.5 ns pulse width, < 600 ps rise time HP 8131A option 020 ≥ 6 GHz bandwidth, < 58 ps rise time Digitizing Oscilloscope HP 54121T Adapter SMA(m)-BNC(f) HP 1250-1200...
Page 77: Set Up The Logic Analyzer
To test the single-clock, multiple-edge, state acquisition (logic analyzer) Set up the oscilloscope. Oscilloscope Setup Time Base Display Delta V Delta T Time/Div: 1.00 ns/div V markers on T markers on # of avg: 16 marker 1 position: Chan 1 start on: Neg Edge 1 screen: dual marker 2 position: Chan 1...
Page 78 To test the single-clock, multiple-edge, state acquisition (logic analyzer) Set up the Format menu. a a Press the Format key. Select State Acquisition Mode, then select Full Channel/4K Memory/100MHz. b b Select the field to the right of each pod field, then select ECL. The screen does not show all pod fields at one time.
Page 79: Connect The Logic Analyzer
Using the 6-by-2 test connectors, connect the first combination of logic analyzer clock and data channels listed in one of the following tables to the pulse generator. If you are testing an HP 1660A or HP 1661A, you will repeat this test for the second combination.
Page 80 To test the single-clock, multiple-edge, state acquisition (logic analyzer) Connect the HP 1662A or HP 1663A Logic Analyzer to the Pulse Generator Testing Connect to Connect to Connect to Combination HP 8131A HP 8131A HP 8131A Channel 1 Output Channel 1 Output...
Page 81: Verify The Test Signal
To test the single-clock, multiple-edge, state acquisition (logic analyzer) Verify the test signal Check the clock period. Using the oscilloscope, verify that the clock period is 20 ns, +0 ps or − 250 ps. a a Enable the pulse generator channel 1 and channel 2 outputs (with the LED off). b b In the oscilloscope Timebase menu, select Sweep Speed 2.50 ns/div.
Page 82 To test the single-clock, multiple-edge, state acquisition (logic analyzer) Check the data pulse width. Using the oscilloscope, verify that the data pulse width is 3.950 ns, +50 ps or − 100 ps. a a In the oscilloscope Timebase menu, select Sweep Speed 2.00 ns/div. b b Select Delay.
Page 83: Check The Setup/Hold With Single Clock, Multiple Clock Edges
To test the single-clock, multiple-edge, state acquisition (logic analyzer) Check the setup/hold with single clock, multiple clock edges Select the logic analyzer setup/hold time. a a In the logic analyzer Format menu, select Master Clock. b b Select and activate any multiple clock edge. c c Select the Setup/Hold field, then select the setup/hold to be tested for all pods.
Page 84 To test the single-clock, multiple-edge, state acquisition (logic analyzer) c c Adjust the pulse generator channel 2 Delay, then select Precision Edge Find in the oscilloscope Delta T menu. Repeat this step until the pulses are aligned according to the setup time of the setup/hold combination selected, +0.0 ps or − 100 ps. Select the clock to be tested.
Page 85 To test the single-clock, multiple-edge, state acquisition (logic analyzer) Create a Compare file with the pattern 01010101 (if you are at this step as a return 5 5 5 5 from step 10, the pattern will be 10101010). Use the following to create a Compare file: a a Press Run.
Page 86 To test the single-clock, multiple-edge, state acquisition (logic analyzer) Ensure the pulses are positioned according to the setup time of the setup/hold combination selected, +0.0 ps or − 100 ps. a a In the oscilloscope Delta V menu, set the Marker 1 Position to Chan 1, then set Marker 1 at −...
Page 87: Test The Next Channels
To test the single-clock, multiple-edge, state acquisition (logic analyzer) Test the next channels • Connect the next combination of data channels and clock channels, then test them. Start on page 3–50, "Connect the logic analyzer," connect the next combination, then continue through the complete test.
Page 88: To Test The Time Interval Accuracy (Logic Analyzer)
Equipment Required Equipment Critical Specifications Recommended Model/Part Pulse Generator 100 MHz 3.5 ns pulse width, < 600 ps rise time HP 8131A Option 020 − 6 Accuracy ≤ (5)(10 ) × frequency Function Generator HP 3325B Option 002 SMA Cable...
Page 89: Set Up The Logic Analyzer
To test the time interval accuracy (logic analyzer) Set up the function generator according to the following table. Function Generator Setup Freq: 200 000 . 0 Hz Main Function: Square wave Amptd: 3.000 V High Voltage: Disabled (LED Off) Phase: 0.0 deg DC Offset: 0.0 V Set up the logic analyzer Set up the Configuration menu.
Page 90 To test the time interval accuracy (logic analyzer) Set up the Format menu. a a Press the Format key. Select Timing Acquisition Mode, then select Transitional Full Channel 125 MHz. b b Select the field to the right of the Pod 1 field, then select ECL. c c Select the field showing the channel assignments for Pod 1.
Page 91: Connect The Logic Analyzer
To test the time interval accuracy (logic analyzer) Set up the Waveform menu. a a Press the Waveform key. b b Move the cursor to the sec/Div field, then use the RPG knob to dial in 2.00 µs. c c Select the Markers Off field, then select Pattern. d d Select the Specify Patterns field.
Page 92: Acquire The Data
Acquire the data Enable the pulse generator channel 1 output (with the LED off). Press the blue key, then press the Run key to select Run-Repetitive. Allow the logic analyzer to acquire data for at least 100 valid runs as indicated in the pattern statistics field.
Page 93: To Test The Cal Output Ports (Oscilloscope)
Equipment Required Equipment Critical Specifications Recommended Model/Part Digital Multimeter 0.1 mV resolution, better than 0.005% accuracy HP 3458A Cable BNC (m)(m) 48-inch HP 10503A Adapter BNC (f) to Dual Banana Plug HP 1251-2277 Set up the equipment Turn on the equipment required and the logic analyzer.
Page 94: Set Up The Logic Analyzer
To test the CAL OUTPUT ports (oscilloscope) Set up the logic analyzer Set up the Calibration menu. a a Press the Waveform key. b b Press the Waveform key again. At the pop up, select Scope Calibration. c c Select the Mode field, then select Service Cal. d d Select the Procedure field, then select DC Cal BNC.
Page 95: Verify The Dc Cal Output Port
To test the CAL OUTPUT ports (oscilloscope) Verify the DC CAL OUTPUT port Using the BNC-to-banana adapter, connect the BNC cable between the multimeter and the oscilloscope DC CAL OUTPUT connector. The digital voltmeter should read close to 0.0000 V. Record the reading to four decimal places.
Page 96: Set Up The Logic Analyzer
To test the CAL OUTPUT ports (oscilloscope) Set up the logic analyzer Set up the Calibration menu. a a Select the Procedure field, then select Osc Out. b b Select the Signal field, then select Probe Comp. Set up the Channel menu. a a Press the Chan key.
Page 97: To Test The Input Resistance (Oscilloscope)
This test checks the input resistance at the 50 Ω and 1 MΩ settings in the Coupling field. Equipment Required Equipment Critical Specifications Recommended Model/Part Digital Multimeter Measure resistance (4-wire) better than 0.25% HP 3458A accuracy Cables (2) BNC (m)(m) 48-inch HP 10503A Adapter BNC Tee (m)(f)(f) HP 1250-0781 Adapters (2)
Page 98: Set Up The Logic Analyzer
To test the input resistance (oscilloscope) Set up the logic analyzer Set up the Channel menu. a a Press the Config key. b b At the pop up menu, select Scope Channel. c c Select the Input field, then select C1. d d Move the cursor to the Probe field, then use the RPG knob to dial in 1:1.
Page 99: Connect The Logic Analyzer
To test the input resistance (oscilloscope) Connect the logic analyzer Using the BNC-to-banana adapters, connect one end of each BNC cable to the 4-wire resistance connections on the multimeter, and connect the free ends of the cables to the BNC Tee. Connect the male end of the BNC tee to the channel 1 input of the oscilloscope module.
Page 100: Acquire The Data
Perform an operational accuracy calibration Acquire the data Press the RUN key. The clicking of attenuator relays should be audible. Verify resistance readings on the digital multimeter of 50 Ω ± 0.5 Ω (49.5 to 50.5 Ω). Record the reading in the performance test record. In the Channel menu change the Coupling field to 1MΩ...
Page 101: To Test The Voltage Measurement Accuracy (Oscilloscope)
Equipment Required Equipment Critical Specifications Recommended Model/Part DC Power Supply –14 Vdc to +14 Vdc, 0.1 mV resolution HP 6114A Digital Multimeter Better than 0.1% accuracy HP 3458A Cable BNC (m)(m) 48-inch HP 10503A Adapter (cable to...
Page 102: Set Up The Logic Analyzer
To test the voltage measurement accuracy (oscilloscope) Set up the logic analyzer Set up the Channel menu. a a Press the Config key. In the pop up menu, select Scope Channel. b b Select the Input field, then select C1. c c Move the cursor to the Probe field, then use the RPG knob to dial in 1:1.
Page 103: Connect The Logic Analyzer
To test the voltage measurement accuracy (oscilloscope) Set up the Marker menu. a a Press the Marker key. b b Move the cursor to the V Markers field and press Select. The voltage markers should now be On. c c Select Va on C1. d d Select Vb on C1.
Page 104: Acquire The Data
To test the voltage measurement accuracy (oscilloscope) Acquire the data Use the following table for steps 1 through 5. Oscilloscope Settings Voltage Readings V/Div Offset Supply Upper Limit Lower Limit 4 V/Div -7.0 V -14.0 V -13.7 V -14.3 V 1 V/Div -1.75 V -3.50 V...
Page 105: To Test The Offset Accuracy (Oscilloscope)
Offset accuracy Equipment Required Equipment Critical Specifications Recommended Model/Part − 35.000 to +35.000 Vdc, ± 1 mV resolution DC Power Supply HP 6114A Digital Multimeter Better than 0.1% accuracy HP 3458A Cable BNC (m)(m) 48-inch HP 10503A Adapter (cable to...
Page 106: Set Up The Logic Analyzer
To test the offset accuracy (oscilloscope) Set up the logic analyzer Set up the Configuration menu. a a Press the Config key. At the pop up menu, select Scope Channel. b b Select the Input field, then select C1. c c Move the cursor to the Probe field, then use the RPG knob to dial in 1:1. d d Move the cursor to the V/Div field, then use the PRG knob to dial in 4.00 V.
Page 107: Connect The Logic Analyzer
To test the offset accuracy (oscilloscope) Set up the Trigger menu. a a Press the Trigger key. b b Select the Mode/Arm field, then select Immediate. Set up the Marker menu. a a Press the Marker key. b b Move the cursor to the T Markers field. Press Select, and then press On. c c If the V markers are On, turn the V markers Off by moving the cursor to the V markers field and pressing Select.
Page 108: Acquire The Zero Input Data
To test the offset accuracy (oscilloscope) Acquire the zero input data Disconnect the power supply from the channel input. Press the Chan key. Move the cursor to the V/Div field and press the Select key. Press the blue shift key, then press the Run key. After approximately 15 seconds (averaging complete), press the Stop key.
Page 109: Acquire The Dc Input Data
To test the offset accuracy (oscilloscope) Acquire the DC input data Use the following table for steps 1 through 5. Multimeter Settings Scope Settings Power Supply Scope Readings Settings V/Div Offset Supply Minimum Maximum − 35.00 V − 35.00 V −...
Page 110: To Test The Bandwidth (Oscilloscope)
Equipment Required Equipment Critical Specifications Recommended Model/Part Signal Generator 1 - 250 MHz at approx 170 mV rms HP 8656B 1 - 250 MHz ± 3% accuracy Power Meter/Sensor HP 436/8482A Power Splitter Outputs differ by <0.15 dB HP 11667B...
Page 111: Set Up The Logic Analyzer
To test the bandwidth (oscilloscope) Set up the logic analyzer Set up the Configuration menu. a a Press the Config key. At the pop up menu, select Scope Channel. b b Select the Input field, then select C1. c c Move the cursor to the Probe field, then use the RPG knob to dial in 1:1. d d Move the cursor to the V/Div field.
Page 112 To test the bandwidth (oscilloscope) Set up the Trigger menu. a a Press the Trigger key. b b Select the Mode/Arm field, then select Edge. c c Select the Source field, then select C1. d d Move the cursor to the Level field. Set the trigger level to 0 by typing 0 in the front-panel keyboard, then pressing Select.
Page 113: Connect The Logic Analyzer
To test the bandwidth (oscilloscope) Connect the logic analyzer Using the N cable, connect the signal generator to the power splitter input. Connect the power sensor to one output of the power splitter. Using the N-to-BNC adapter and the BNC cable, connect the other power splitter output to the channel 1 input of the oscilloscope.
Page 114: Acquire The Data
To test the bandwidth (oscilloscope) Acquire the data Obtain the 1 MHz response. a a Set the signal generator for 1 MHz at − 2.4 dBm. b b Press the blue shift key, then press the Run key. The signal on the screen should be two cycles at three divisions amplitude.
Page 115: To Test The Time Measurement Accuracy (Oscilloscope)
Equipment Required Equipment Critical Specifications Recommended Model/Part Signal Generator 200 MHz, timebase accuracy 0.25 ppm HP 8656B Opt. 001 Cable BNC (m)(m) 48-inch HP 10503A Adapter Type N (m) to BNC (f) HP 1250-0780 Set up the equipment Turn on the equipment required and the logic analyzer.
Page 116: Set Up The Logic Analyzer
To test the time measurement accuracy (oscilloscope) Set up the logic analyzer Set up the Configuration menu. 1 1 1 1 a a Press the Config key. At the pop up menu, select Scope Channel. b b Select the Input field, then select C1. c c Move the cursor to the Probe field, then use the RPG knob to dial in 1:1.
Page 117 To test the time measurement accuracy (oscilloscope) Set up the Trigger menu. a a Press the Trigger key. b b Select the Mode/Arm field, then select Edge. c c Select the Source field and set it to C1. d d Move the cursor to the Level field. Set the trigger level to 0 by typing 0 in the front-panel keyboard, then pressing Select.
Page 118: Connect The Logic Analyzer
To test the time measurement accuracy (oscilloscope) Connect the logic analyzer Using the N-to-BNC adapter and the BNC cable, connect the signal generator output to the channel 1 input of the oscilloscope. Acquire the data Determine short time period accuracy. a a Press the blue shift key, then press Run.
Page 119: To Test The Trigger Sensitivity (Oscilloscope)
Equipment Required Equipment Critical Specifications Recommended Model/Part Signal Generator 50 and 225 MHz, 30 - 80 mV RMS output HP 8656B Opt. 001 Cable BNC 48-inch HP 10503B Adapter Type N (m) to BNC (f) HP 1250-0780 Set up the equipment Turn on the equipment required and the logic analyzer.
Page 120: Set Up The Logic Analyzer
To test the trigger sensitivity (oscilloscope) Set up the logic analyzer Set up the Configuration menu. 1 1 1 1 a a Press the Config key. At the pop up menu, select Scope Channel. b b Select the Input field, then select C1. c c Move the cursor to the Probe field, then use the RPG knob to dial in 1:1.
Page 121 To test the trigger sensitivity (oscilloscope) Set up the Trigger menu. a a Press the Trigger key. b b Select the Mode/Arm field, then select Edge. c c Select the Source field and set it to C1. d d Move the cursor to the Level field. Set the trigger level to 0 by typing 0 in the front-panel keyboard, then pressing Select.
Page 122: Connect The Logic Analyzer
To test the trigger sensitivity (oscilloscope) Connect the logic analyzer Using the N-to-BNC adapter and the BNC cable, connect the signal generator output to the channel 1 input of the oscilloscope. Acquire the data Test the upper bandwidth trigger sensitivity. a a Set the signal generator to provide a 225 MHz signal with 70 mV rms amplitude.
Page 123: Performance Test Record (Logic Analyzer)
Performance Test Record (logic analyzer) Performance Test Record (logic analyzer) HP 1660 Ser i es Logi c Anal yzer HP 1660 Ser i es Logi c Anal yzer _______ Serial No.______________________ Work Order No.___________________ Recommended Test Interval - 2 Year/4000 hours...
Page 124 Performance Test Record (logic analyzer) Performance Test Record (continued) Test Settings Results Threshold Accuracy (cont) Limits Measured TTL, ± 145 mV Pod 4 TTL VL +1.355 V ________ TTL VH +1.645 V ________ ECL, ± 139 mV ECL VL -1.439 V ________ ECL VH -1.161 V...
Page 125 Performance Test Record (logic analyzer) Performance Test Record (continued) Test Settings Results Glitch Capture Minimum Pass/Fail Detectable Glitch 3.5 ns Pod 1 ________ Pod 2 ________ Pod 3 ________ Pod 4 ________ Pod 5 ________ Pod 6 ________ Pod 7 ________ Pod 8 ________...
Page 126 Performance Test Record (logic analyzer) Performance Test Record (continued) Test Settings Results Single-Clock, Pass/Fail Pass/Fail Single-Edge Acquisition All Pods, Setup/Hold Time 3.5/0.0 ns J↑ ________ J↓ ________ Channel 3 K↑ ________ K↓ _________ L↑ ________ L↓ ________ M↑ ________ M↓ ________ N↑...
Page 127 Performance Test Record (logic analyzer) Performance Test Record (continued) Test Settings Results Multiple-Clock, Enable pulse generator, channel 2 Disable pulse generator, Multiple-Edge COMP (LED on) channel 2 COMP (LED off) Acquisition Pass/Fail Pass/Fail All Pods, Setup/Hold Time 4.5/0.0 ns J↑ + M↓ + N↑ ________ J↓...
Page 128 Performance Test Record (logic analyzer) Performance Test Record (continued) Test Settings Results Single-Clock, Disable pulse generator, Enable pulse generator, Multiple-Edge channel 1 COMP (LED off) channel 1 COMP (LED on) Acquisition Pass/Fail Pass/Fail All Pods, Setup/Hold Time 4.0/0.0 ns _______ _______ Channel 3 _______...
Page 129 Performance Test Record (logic analyzer) Performance Test Record (continued) Test Settings Results Time Interval Measured Accuracy 94.99-95.00 µs min X-0 _________ 95.00-95.01 µs max X-0 _________ 94.99-95.01 µs avg X-0 _________ 3–100...
Page 130: Performance Test Record (Oscilloscope)
Performance Test Record (oscilloscope) Performance Test Record (oscilloscope) Test Settings Results Self-Tests Pass/Fail ________ 5.000 Vdc ± 10 mV DC CAL Output Limits Measured 4.990 Vdc ________ 5.010 Vdc 0.8 Vp_p ± 10% AC CAL Output 0.72 Vp_p ________ 1.000 KHz ± 10% 0.88 Vp_p 900 Hz ________...
Page 131 Performance Test Record (oscilloscope) Performance Test Record (oscilloscope) Test Settings Results Voltage Limits Measured Measurement Accuracy Channel 1 Zero Input -13.7 V - -14.3 V ________ -3.43 V - -3.57 V ________ -1.37 V - -1.43 V ________ -137.0 mV - -143.0 mV ________ 143.0 mV - 137.0 mV ________...
Page 132 Performance Test Record (oscilloscope) Performance Test Record (oscilloscope) Test Settings Results Bandwidth Limit Measured ≤ − Channel 1 3.0dB ________ ≤ − Channel 2 3.0dB ________ ± Time 5.500ns 150ps MEAN X-O ________ Measurement MIN X-O ________ Accuracy MEAN X-O - MIN X-O ________ MAX X-O ________...
Page 133 3–104...
Page 134: Calibrating And Adjusting
Logic analyzer calibration 4-2 To calibrate the oscilloscope 4-3 Load the Default Calibration Factors 4-4 Self Cal menu calibrations 4-5 To adjust the CRT monitor alignment 4-6 To adjust the CRT intensity 4-8 Calibrating and Adjusting...
Page 135: Logic Analyzer Calibration
Performance" in chapter 3. Logic analyzer calibration The logic analyzer circuitry of the HP 1660A-series and HP 1660AS-series Logic Analyzers does not require an operational accuracy calibration. To test the logic analyzer circuitry against specifications ( full calibration) , refer to chapter 3, Testing Performance.
Page 136: To Calibrate The Oscilloscope
To calibrate the oscilloscope Equipment Required Equipment Critical Specification Recommended Model/Part Cable (2) BNC, 9-inch (equal length) HP 10502A Cable HP 10503A Adapter BNC tee (m)(f)(f) HP 1250-0781 Adapter BNC (f)(f) (ug-914/u) HP 1250-0080 Set up the equipment Turn on the logic analyzer. Let it warm up for 30 minutes if you have not already done so.
Page 137: Load The Default Calibration Factors
Calibrating and Adjusting To calibrate the oscilloscope Load the Default Calibration Factors Note that once the default calibration factors are loaded, all calibrations must be done. This includes all of the calibrations in the Self Cal menu. The calibration must be performed in the exact sequence listed below.
Page 138: Self Cal Menu Calibrations
Calibrating and Adjusting To calibrate the oscilloscope Self Cal menu calibrations Messages will be displayed as each calibration routine is completed to indicate calibration has passed or failed. The resulting calibration factors are automatically stored to nonvolatile RAM at the conclusion of each calibration routine. The Self Cal menu lets you optimize vertical sensitivity ( Vert Cal) for channels 1 and 2 individually or both channels on a board simultaneously.
Page 139: To Adjust The Crt Monitor Alignment
To adjust the CRT monitor alignment Do not touch the CRT monitor sweep board. High voltages exist on the sweep board that W A R N I N G can cause personal injury. Equipment Required Equipment Critical Specification Recommended Model/Part Alignment Tool 8710-1300 Turn off the logic analyzer, then disconnect the power cord.
Page 140 Calibrating and Adjusting To adjust the CRT monitor alignment Enter the Sys PV tests, then enter the Display Test. A grid pattern should appear. If the display is tilted (rotated), adjust the CRT yoke by rotating it to straighten the display.
Page 141: To Adjust The Crt Intensity
To adjust the CRT intensity Do not touch the CRT monitor sweep board. High voltages exist on the sweep board that W A R N I N G can cause personal injury. Equipment Required Equipment Critical Specification Recommended Model/Part Alignment Tool 8710-1300 Light Power Meter United Detector 351...
Page 142 Calibrating and Adjusting To adjust the CRT intensity Do not touch the CRT monitor sweep board. High voltages exist on the sweep board that W A R N I N G can cause personal injury. The light power meter should read 137-154 cd/m .
Page 143 4–10...
Page 144 To use the flowcharts 5-2 To check the power-up tests 5-15 To run the self-tests 5-16 To test the power supply voltages 5-22 To test the CRT monitor signals 5-24 To test the keyboard signals 5-25 To test the disk drive voltages 5-26 To perform the BNC test 5-28 To test the logic analyzer probe cables 5-29 To test the auxiliary power 5-33...
Page 145: To Use The Flowcharts
Troubleshooting This chapter helps you troubleshoot the logic analyzer to find defective assemblies. The troubleshooting consists of flowcharts, self-test instructions, and tests. This information is not intended for component-level repair. If you suspect a problem, start at the top of the first flowchart. During the troubleshooting instructions, the flowcharts will direct you to perform other tests.
Page 146 Troubleshooting To use the flowcharts Troubleshooting Flowchart 1 5–3...
Page 147 Troubleshooting To use the flowcharts Troubleshooting Flowchart 2 5–4...
Page 148 Troubleshooting To use the flowcharts Troubleshooting Flowchart 3 5–5...
Page 149 Troubleshooting To use the flowcharts Troubleshooting Flowchart 4 5–6...
Page 150 Troubleshooting To use the flowcharts Troubleshooting Flowchart 5 5–7...
Page 151 Troubleshooting To use the flowcharts Troubleshooting Flowchart 6 5–8...
Page 152 Troubleshooting To use the flowcharts Troubleshooting Flowchart 7 5–9...
Page 153 Troubleshooting To use the flowcharts Troubleshooting Flowchart 8 5–10...
Page 154 Troubleshooting To use the flowcharts Troubleshooting Flowchart 9 5–11...
Page 155 Troubleshooting To use the flowcharts Troubleshooting Flowchart 10 5–12...
Page 156 Troubleshooting To use the flowcharts Troubleshooting Flowchart 11 5–13...
Page 157 Troubleshooting To use the flowcharts Troubleshooting Flowchart 12 5–14...
Page 158: To Check The Power-Up Tests
Troubleshooting To check the power-up tests To check the power-up tests The logic analyzer automatically performs power-up tests when you apply power to the instrument. The revision number of the operating system shows in the upper-right corner of the screen during these power-up tests. As each test completes, either "passed" or "failed" prints on the screen in front of the name of each test.
Page 159: To Run The Self-Tests
Troubleshooting To run the self-tests To run the self-tests Self-tests identify the correct operation of major functional areas of the instrument. You can run all self-tests without accessing the interior of the instrument. If a self-test fails, the troubleshooting flowcharts instruct you to change a part of the instrument. If you just did the power-up self-tests, go to step 2.
Page 160 Troubleshooting To run the self-tests Select ROM Test. The ROM Test screen is displayed. You can run all tests at one time by running All System Tests. To see more details about each test, you can run each test individually. This example shows how to run an individual test.
Page 161 Troubleshooting To run the self-tests To exit the ROM Test, select Done. Note that the status changes to Passed or Failed. Install a formatted disk that is not write protected into the disk drive. Connect an RS-232C loopback connector onto the RS-232C port. Run the remaining System Tests in the same manner.
Page 162 Troubleshooting To run the self-tests Select Sys PV, then select Analy PV in the pop-up menu. Select Chip 2 Tests. You can run all the analyzer tests at one time by selecting All Analyzer Tests. To see more details about each test, you can run each test individually. This example shows how to run Chip 2 Tests.
Page 163 Select Data Input Inspection. All lines should show activity. Select Done to exit the Data Input Inspection. If you have an HP 1660A-series Logic Analyzer ( no oscilloscope) , go to step 18. If you have an HP 1660AS-series Logic Analyzer, continue with step 15.
Page 164 Troubleshooting To run the self-tests In the Data Memory Test menu, select Run, then select Single. The test runs one time, then the screen shows the results. When the test is finished, select Done. To run a test continuously, select Repetitive. Select Stop to halt a Repetitive Run. To exit the tests, press the System key.
Page 165: To Test The Power Supply Voltages
Troubleshooting To test the power supply voltages To test the power supply voltages To check the voltages, the power supply must be loaded by either the acquisition board or with an added resistor. Refer to chapter 6, "Replacing Assemblies," for instructions to remove or replace covers and assemblies.
Page 166 Troubleshooting To test the power supply voltages Check for the voltages on the power supply cable using the values in the following table. Signals on the Power Supply Cable Signal Signal +5.00 V –5.20 V +5.00 V Ground +5.00 V +12 V +5.00 V Ground...
Page 167: To Test The Crt Monitor Signals
Troubleshooting To test the CRT monitor signals To test the CRT monitor signals Refer to chapter 6, "Replacing Assemblies," for instructions to remove or replace covers and assemblies. Hazard voltages exist on the power supply, the CRT, and the CRT driver board. This W A R N I N G procedure is to be performed by service-trained personnel aware of the hazards involved, such as fire and electrical shock.
Page 168: To Test The Keyboard Signals
Troubleshooting To test the keyboard signals To test the keyboard signals Refer to chapter 6, "Replacing Assemblies," for instructions to remove covers and assemblies. Hazard voltages exist on the power supply, the CRT, and the CRT driver board. This W A R N I N G procedure is to be performed by service-trained personnel aware of the hazards involved, such as fire and electrical shock.
Page 169: To Test The Disk Drive Voltages
Model/Part Digitizing Oscilloscope > 100 MHz Bandwidth HP 54600A Turn off the instrument, then remove the power cable. Remove the instrument cover and the disk drive. Reconnect the disk drive cable to the rear of the disk drive. Turn the disk drive over so that the solder connections of the cable socket are accessible.
Page 170 Troubleshooting To test the disk drive voltages Check for the following voltages and signals using an oscilloscope. Disk Drive Voltages Signal Description Signal Description Disk Change High Density +5 V Index +5 V Drive Select +5 V Ground Ground Motor On Ground Direction Ground...
Page 171: To Perform The Bnc Test
To perform the BNC test Equipment Required Equipment Critical Specification Recommended Model/Part Digitizing Oscilloscope 100 MHz Bandwidth HP 54600A BNC Shorting Cap 1250-0074 BNC Cable HP 10503A BNC-Banana Adapter 1251-2277 Press the Config key. Assign pods 1 and 2 to Machine 1.
Page 172: To Test The Logic Analyzer Probe Cables
Equipment Required Equipment Critical Specification Recommended Model/Part Pulse Generator 100 MHz, 3.5 ns pulse width, HP 8131A Option 020 < 600 ps rise time Adapter (Qty 4) SMA (m) - BNC (f) HP 1250-1200 Coupler (Qty 4) BNC (m)(m) HP 1250-0216 6x2 Test Connectors (Qty 4) Turn on the equipment required and the logic analyzer.
Page 173 Troubleshooting To test the logic analyzer probe cables Set up the Format menu. a a Press the Format key. b b Move the cursor to the field showing the channel assignments for the pod under test. Press the Clear Entry key until the pod channels are all assigned (all asterisks (*)). Press the Done key.
Page 174 Troubleshooting To test the logic analyzer probe cables e e Select the field to the right of the pod being tested, then select TTL. Set up the Trigger menu. a a Press the Trigger key. b b Select Clear Trigger, then select All. Set up the Listing menu.
Page 175 Troubleshooting To test the logic analyzer probe cables Using four 6-by-2 test connectors, four BNC Couplers, and four SMA (m) - BNC (f) Adapters, connect the logic analyzer to the pulse generator channel outputs. To make the test connectors, see chapter 3, "Testing Performance." a a Connect the even-numbered channels of the lower byte of the pod under test to the pulse generator channel 1 Output and J-clock.
Page 176: To Test The Auxiliary Power
1 minute. There should be +5 V after the 1 minute reset time. Equipment Required Equipment Critical Specifications Recommended Model/Part Digital Multimeter 0.1 mV resolution, better HP 3478A than 0.005% accuracy • Using the multimeter, verify the +5 V on pins 1 and 39 of the probe cables. 5–33...
Page 177 5–34...
Page 178 Disk drive 6-6 Power supply 6-7 CPU board 6-7 Switch actuator assembly 6-8 Rear panel assembly 6-9 Acquisition board ( oscilloscope board for HP 1660AS-series) 6-10 Front panel and keyboard 6-11 Intensity adjustment 6-11 Monitor 6-12 Handle plate 6-12 Fan 6-13...
Page 179 Tool s Requi r ed #10 TORX screwdriver #15 TORX screwdriver #1 Posidrive screwdriver 3/16 inch ( 5 mm) nut driver 9/32 inch ( 7 mm) nut driver 5/8 inch ( 16 mm) nut driver ( HP 1660AS series only) 6–2...
Page 180 MP23 Label Jumper cable-orange BNC connector MP24 Label Jumper cable-white Hex nut * Lock washer * Hex nut * Intensity adjustment MP25 Elastomeric keypad Power supply cable Disk drive bracket Cable - 60-conductor * * HP 1660AS series only 6–3...
Page 181 Replacing Assemblies Exploded View of the HP 1660A 6–4...
Page 182: To Remove And Replace The Handle
Replacing Assemblies To remove and replace the handle To remove and replace the handle • Remove the two screws in the endcaps, then lift off the handle. To remove and replace the feet and tilt stand Remove the screws connecting the four rear feet to the instrument. Separate the rear feet from the instrument to remove them.
Page 183: To Remove And Replace The Disk Drive
Replacing Assemblies To remove and replace the disk drive To remove and replace the disk drive Using previous procedures, remove the following assemblies: • Handle • Rear Feet • Cover Disconnect the disk drive cable from the rear of the disk drive. Remove the two screws that attach the disk drive bracket to the power supply.
Page 184: To Remove And Replace The Power Supply
Disconnect the CPU board interface cable from the acquisition board by pressing down on the cable release tabs on the cable socket located on the acquisition board. Disconnect the HP-IB and RS-232C cables from the CPU board. Disconnect the front panel cable from the CPU board.
Page 185: To Remove And Replace The Switch Actuator Assembly
Replacing Assemblies To remove and replace the switch actuator assembly To remove and replace the switch actuator assembly Using previous procedures, remove the following assemblies: • Handle • Rear Feet • Cover • Disk Drive • Power Supply • CPU Board Make sure the power switch is in the off position.
Page 186: To Remove And Replace The Rear Panel Assembly
Disconnect the BNC In/Out and fan cables on the acquisition board. Disconnect the RS-232C an HP-IB cables from the CPU board. For the HP 1660AS-series Logic Analyzers, remove the hex nut and lock washer from the BNC Cal ports. Remove the two screws connecting the keyboard connector socket to the rear panel.
Page 187: To Remove And Replace The Acquisition Board ( Oscilloscope Board For Hp 1660As-Series)
Replacing Assemblies To remove and replace the acquisition board (and oscilloscope board for HP 1660AS-series) To remove and replace the acquisition board (and oscilloscope board for HP 1660AS-series) Using previous procedures, remove the following assemblies: • Handle • Rear Feet •...
Page 188: To Remove And Replace The Front Panel And Keyboard
Replacing Assemblies To remove and replace the front panel and keyboard To remove and replace the front panel and keyboard Using previous procedures, remove the following assemblies: • Handle • Rear Feet • Cover • Disk Drive • Power Supply •...
Page 189: To Remove And Replace The Monitor
• Rear Panel • Acquisition Board • Oscilloscope Board ( HP 1660AS-series only) • Intensity Adjustment Hazardous voltages exist on the CRT and the CRT driver board. To avoid electrical shock, W A R N I N G disconnect the power from the instrument before performing the following procedures.
Page 190: To Remove And Replace The Fan
Replacing Assemblies To remove and replace the fan To remove and replace the fan Using previous procedures, remove the following assemblies: • Handle • Rear Feet • Cover • Disk Drive • Power Supply • Rear Panel Remove the four fan screws. Lift the fan away from the rear panel.
Page 191: To Remove And Replace The Hp-Ib And Rs-232C Cables
Power Supply • Rear Panel Remove the two hex standoffs connecting the HP-IB cable, then slide the HP-IB cable forward and out of the rear panel. Remove the two hex standoffs connecting the RS-232C cable, then slide the RS-232C cable forward and out of the rear panel.
Page 192: To Return Assemblies
Only return accessories to Hewlett-Packard if they are associated with the failure symptoms. Package the logic analyzer. You can use either the original shipping containers, or order materials from an HP sales office. For protection against electrostatic discharge, package the logic analyzer in electrostatic C A U T I O N material.
Page 193 6–16...
Page 194 Replaceable Parts Ordering 7–2 Exploded View 7–3 Replaceable Parts List 7–4 Power Cables and Plug Configurations 7–8 Replaceable Parts...
Page 195: Replaceable Parts Ordering
Within the USA, Hewlett-Packard can supply parts through a direct mail order system. The advantages to the system are direct ordering and shipment from the HP Part Center in Mountain View, California. There is no maximum or minimum on any mail order. ( There is a minimum amount for parts ordered through a local Hewlett-Packard Sales Office when the orders require billing and invoicing.) Transportation costs are prepaid ( there is a small...
Page 196: Exploded View
Replaceable Parts Exploded View Exploded View Exploded view of the HP 1660 logic analyzer. 7–3...
Page 197: Replaceable Parts List
Replaceable Parts Replaceable Parts List Replaceable Parts List The replaceable parts list is organized by reference designation and shows exchange assemblies, electrical assemblies, then other parts. The exploded view does not show all of the parts in the replaceable parts list. Information included for each part on the list consists of the following: •...
Page 198 Description Exchange Board Assembly 01660-69503 Exchange Board Assembly - CPU 01660-69501 Exchange Board Assembly-ACQ 128 CH (HP 1660A, HP 1660AS) 01660-69504 Exchange Board Assembly-ACQ 96 CH (HP 1661A, HP 1661AS) 01660-69505 Exchange Board Assembly-ACQ 64 CH (HP 1662A, HP 1662AS)
Page 199 MSF M3 6 T10 (accessory pouch) 2950-0054 NUTH 1/2-28 .125 (BNC cal ports, HP 1660AS series only) 2190-0068 WIL .505 .630 .02 (BNC cal ports, HP 1660AS series only) 01650-29101 Ground Spring (HP 1660AS series only) 54503-25701 Hex Nut (attenuator, HP 1660AS series only) 0515-1246 MS M3 x 0.5 T10 (attenuator, HP 1660AS series only)
Page 200 01660-61607 Jumper cable assembly-orange 01660-61608 Jumper cable assembly-wht 54503-61606 Power supply cable 01660-61604 Cable - 60 Conductor (HP 1660AS series only) 8120-1521 Power cord - United States (7.5 ft) 8120-1703 Power cord (Option 900-UK) 8120-0696 Power cord (Option 901-Austl) 8120-1692...
Page 201: Power Cables And Plug Configurations
Replaceable Parts Power Cables and Plug Configurations Power Cables and Plug Configurations This instrument is equipped with a three-wire power cable. The type of power cable plug shipped with the instrument depends on the country of destination. The W10 reference designators ( table, previous page) show option numbers of available power cables and plug configurations.
Page 202 Block-Level Theory 8-3 The HP 1660 Series Logic Analyzer 8-3 The Logic Acquisition Board 8-6 The Oscilloscope Board 8-9 Self-Tests Description 8-12 Power-up Self-Tests 8-12 System Tests ( System PV) 8-13 Analyzer Tests ( Analy PV) 8-16 Oscilloscope Tests ( Scope PV) 8-18...
Page 203 Theory of Operation This chapter tells the theory of operation for the logic analyzer and describes the self-tests. The information in this chapter is to help you understand how the logic analyzer operates and what the self-tests are testing. This information is not intended for component-level repair.
Page 204: Block-Level Theory
Block-Level Theory The block-level theory is divided into two parts: theory for the logic analyzer and theory for the acquisition boards. A block diagram is shown with each theory. The HP 1660 Series Logic Analyzer The HP 1660 logic analyzer 8–3...
Page 205 Theory of Operation The HP 1660 Series Logic Analyzer HP 1660 Ser i es Theor y HP 1660 Ser i es Theor y CPU Boar d CPU Boar d The microprocessor is a Motorola 68EC020 running at 25 MHz. The microprocessor controls all of the functions of the logic analyzer including processing and storing data, displaying data, and configuring the acquisition ICs to obtain and store data.
Page 206 Ext er nal Keyboar d I nt er f ace Ext er nal Keyboar d I nt er f ace HP proprietary ICs make up the external keyboard interface. The ICs establish a link with the controller IC on the external keyboard. The keyboard signals are routed through the acquisition circuit board to the CPU board.
Page 207: The Logic Acquisition Board
Theory of Operation The Logic Acquisition Board The Logic Acquisition Board The Logic Acquisition Board 8–6...
Page 208 The clock/data channel is also available as a data channel in timing acquisition mode. Eight ( HP 1660A) , six ( HP 1661A) , four ( HP 1662A) , or two ( 1663A) clock/data channels are available as data channels, however only six clock/data channels can be assigned as clock channels in the HP 1660A and HP 1661A.
Page 209 Theory of Operation The Logic Acquisition Board Clock optimization involves using programmable delays on board the IC to position the master clock transition where valid data is captured. This procedure greatly reduces the effects of channel-to-channel skew and other propagation delays. In the timing acquisition mode, an oscillator-driven clock circuit provides a four-phase, 100-MHz clock signal to each of the acquisition ICs.
Page 210: The Oscilloscope Board
Theory of Operation The Oscilloscope Board The Oscilloscope Board The Oscilloscope Board 8–9...
Page 211 Theory of Operation The Oscilloscope Board Osci l l oscope Boar d Theor y ( HP 1660AS ser i es onl y) Osci l l oscope Boar d Theor y ( HP 1660AS ser i es onl y) At t enuat or /Pr eamp Theor y of Oper at i on...
Page 212 Theory of Operation The Oscilloscope Board Ti me Base The time base provides the sample clocks and timing necessary for data Ti me Base acquisition. It consists of the 100 MHz reference oscillator and time base hybrid. The 100 MHz reference oscillator provides the base sample frequency. The time base hybrid has programmable dividers to provide the rest of the sample frequencies appropriate for the time range selected.
Page 213: Self-Tests Description
The self-tests identify the correct operation of major functional areas in the logic analyzer. The self-tests are not intended for component-level diagnostics. Three types of tests are performed on the HP 1660 series logic analyzers: the power-up self-tests, the functional performance verification self-tests, and the parametric performance verification tests.
Page 214: System Tests (System Pv)
This means that the microprocessor can execute the operating system code and properly service interrupts generated by pressing a front panel key or receiving an HP-IB or RS-232C command. System Tests (System PV) The system tests are functional performance verification tests.
Page 215 HP-I B Test HP-I B Test The HP-IB test performs a write/read operation to each of the registers of the HP-IB IC. A test pattern is written to each register in the HP-IB IC. The pattern is then read and compared with a known value.
Page 216 Theory of Operation System Tests (System PV) Per f or m Test Al l Per f or m Test Al l Selecting Perform Test All will initiate all of the previous functional verification tests in the order they are listed. The failure of any or all of the tests will be reported in the test menu field of each of the tests.
Page 217: Analyzer Tests (Analy Pv)
Theory of Operation Analyzer Tests (Analy PV) Analyzer Tests (Analy PV) The analyzer tests are functional performance verification tests. There are three types of analyzer tests: the Board Test, the Chip Tests, and the Data Input Inspection. The following describes the analyzer self-tests: Boar d Test Boar d Test The Board Test functionally verifies the two oscillators and the 9-channel comparators on the...
Page 218 The data input inspection is not an active part of the performance verification. However, the test is useful for identifying failed channels in order to temporarily work around the problem until the logic analyzer module can be sent to an HP service center for repair. 8–17...
Page 219: Oscilloscope Tests (Scope Pv)
The following self-tests check the major components of the HP 1660AS-series oscilloscope board as well as all associated circuitry. When the self-tests have all been completed with a "PASS" status, the major data and control pipelines in the HP 1660AS-series oscilloscope board are functioning properly.
Page 220: Hp-Ib
The interface makes it possible to transfer messages between two or more HP-IB compatible devices. HP-IB is a parallel bus of 16 active signal lines divided into three functional groups according to function.
Page 221 RS-232C The logic analyzer interfaces with RS-232C communication lines through a standard 25 pin D connector. The logic analyzer is compatible with RS-232C protocol. When a hardwire handshake method is used, the Data Terminal Ready ( DTR) line, pin 20 on the connector, is used to signal if space is available for more data in the logical I/O buffer.
Page 222 • © Copyright Hewlett- Safety Safety Symbols Service instructions are for Packard Company trained service personnel. To avoid This apparatus has been designed 1987–1993 dangerous electric shock, do not and tested in accordance with IEC perform any service unless Publication 348, Safety All Rights Reserved.
Page 223 The remedies provided herein are This is the first edition of the of any changed pages to that a warranty against defects in the buyer’s sole and exclusive HP 1660 Series Logic Analyzer edition. material and workmanship for a remedies. Hewlett-Packard shall Service Guide.

This manual is also suitable for:

1660a series 1660as series1660a1661a 1662a 1663a

HP 1660 Series Service Manual

Quick Links

Related Manuals for HP 1660 Series

Summary of Contents for HP 1660 Series

This manual is also suitable for:

Table of Contents