R0P7727TH003TRKE General Information Manual
5.3.3 Register Map
Tables 5.4 and 5.5 show register maps for the serial interface controller registers. Each of the serial interface
control registers must be accessed in words. If access takes place in words, data in the low order 8 bits
(D7 to D0) will become effective.
Address
H'BA000000
H'BA000002
H'BA000004
H'BA000006
H'BA000008
H'BA00000A
H'BA00000C
H'BA00000E
H'BA000000
H'BA000002
Address
Initial value
H'BB000000
H'BB000002
H'BB000004
H'BB000006
H'BB000008
H'BB00000A
H'BB00000C
H'BB00000E
H'BB000000
H'BB000002
Table 5.4 Serial Interface Controller Register Map (Channel A)
Initial value
Register name (at read)
-
RHR(ReceiveHoldingRegister)
H'00
IER(InterruptEnableRegister)
H'01
ISR(InterruptStatusRegister)
H'00
LCR(LineControlRegister)
H'00
MCR(ModemControlRegister)
H'60
LSR(LineStatusRegister)
H'X0
MSR(ModemStatusRegister)
H'FF
SPR(ScratchpadRegister)
-
DLL(LSB of Divisor Latch)
-
DLM(MSB of Divisor Latch)
Table 5.5 Serial Interface Controller Register Map (Channel B)
Register name (at read)
-
RHR(ReceiveHoldingRegister)
H'00
IER(InterruptEnableRegister)
H'01
ISR(InterruptStatusRegister)
H'00
LCR(LineControlRegister)
H'00
MCR(ModemControlRegister)
H'60
LSR(LineStatusRegister)
H'X0
MSR(ModemStatusRegister)
H'FF
SPR(ScratchpadRegister)
-
DLL(LSB of Divisor Latch)
-
DLM(MSB of Divisor Latch)
Register name (at write)
THR(TransferHoldingRegister)
IER(InterruptEnableRegister)
FCR(FIFOControlRegister)
LCR(LineControlRegister)
MCR(ModemControlRegister)
N.A
N.A
SPR(ScratchpadRegister)
DLL(LSB of Divisor Latch)
DLM(MSB of Divisor Latch)
Register name (at write)
THR(TransferHoldingRegister)
IER(InterruptEnableRegister)
FCR(FIFOControlRegister)
LCR(LineControlRegister)
MCR(ModemControlRegister)
N.A
N.A
SPR(ScratchpadRegister)
DLL(LSB of Divisor Latch)
DLM(MSB of Divisor Latch)
30
Functional Blocks
Remarks
LCR bit7=0
LCR ≠ H'BF
LCR ≠H'BF
LCR bit7=1
LCR ≠H'BF
Remarks
LCR bit7=0
LCR ≠ H'BF
LCR ≠H'BF
LCR bit7=1
LCR ≠H'BF