Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7750, SH7750S, SH7750R Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7750 Series Rev.7.00 Revision Date: Oct. 10, 2008...
Page 2 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4 Rev.7.00 Oct. 10, 2008 Page iv of lxxxiv REJ09B0366-0700...
Page 5 Explanatory Note: Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.renesas.com/) • User manuals for SH7750, SH7750S, and SH7750R Name of Document Document No.
Page 6 • User manuals for development tools Name of Document Document No. SuperH™ RISC engine C/C++ Compiler, Assembler, Optimizing Linkage REJ10J1571-0100 Editor User's Manual SuperH™ RISC engine Simulator/Debugger User's Manual REJ10B0210-0400 High-performance Embedded Workshop User's Manual REJ10J1737-0100 Rev.7.00 Oct. 10, 2008 Page vi of lxxxiv REJ09B0366-0700...
Page 7 Main Revisions for This Edition Item Page Revision (See Manual for Details) ⎯ • Notification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. Description amended Iφ → Ick Bφ → Bck Pφ → Pck 1.1 SH7750, SH7750S,...
Page 8 Item Page Revision (See Manual for Details) 1.2 Block Diagram Figure amended Figure 1.1 Block Diagram of SH7750/ SH7750S/SH7750R Group Functions Lower 32-bit data SH-4 Core Lower 32-bit data Cache and I cache ITLB UTLB O cache controller INTC DMAC (SCIF) External bus interface...
Page 9 Item Page Revision (See Manual for Details) 1.3 Pin Arrangement Figure amended Figure 1.4 Pin Arrangement (264-Pin TRST IRL2 VSS-CPG XTAL EXTAL VDD-CPG TDO MD6/IOIS16 VDDQ VDDQ TCLK VSS-RTC XTAL2 EXTAL2 CSP) RESET IRL3 VDD-PLL2 STATUS0 DACK0 VDDQ MD7/TXD RDY VSS-PLL2 VSS-PLL1 VDD-PLL1 TCK VSSQ VSSQ MD3/CE2A VDDQ...
Page 10 Item Page Revision (See Manual for Details) 1.4.2 Pin Functions 26, 27, Table and notes amended (208-Pin QFP) Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset Table 1.3 Pin CKIO Clock output CKIO CKIO CKIO Functions RD/WR Read/write RD/WR RD/WR RD/WR RD/WR RD/WR...
Page 11 Item Page Revision (See Manual for Details) 4.3.10 Notes on Using 125 to Newly added Cache Enhanced Mode (SH7750R Only) 4.4.1 Configuration Description amended • LRU (SH7750R only) • LRU (SH7750R only) In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address.
Page 12 Item Page Revision (See Manual for Details) 5.6.1 Resets Description amended (3) H-UDI Reset In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK) are set to B'1111.
Page 13 Item Page Revision (See Manual for Details) 5.7 Usage Notes Description amended 2. If a general exception or interrupt occurs when SR.BL = 1 a. General exception When a general exception other than a user break occurs, a manual reset is executed. The value in EXPEVT at this time is H'0000 0020;...
Page 14 Item Page Revision (See Manual for Details) 7.3 Instruction Set Table amended Table 7.12 Floating- Instruction Operation Point Graphics ~FPSCR.FR → FPSCR.FR FRCHG Acceleration Instructions ~FPSCR.SZ → FPSCR.SZ FSCHG 7.4 Usage Notes 227 to Newly added 8.4 Usage Notes Newly added 9.1.1 Types of Power- Description amended Down Modes...
Page 15 Item Page Revision (See Manual for Details) 9.7.2 Exit from Description amended Hardware Standby Setting the CA pin level high after the RESET pin level has Mode been set low and the SCK2 pin high starts the clock to oscillate. The RESET pin level should be kept low until the clock has stabilized, then set high so that the CPU starts the power-on reset exiting procedure.
Page 16 Item Page Revision (See Manual for Details) 10.1.1 Features Description amended • Three clocks The CPG can generate the CPU clock (Ick) used by the CPU, FPU, caches, and TLB, the peripheral module clock (Pck) used by the peripheral modules, and the bus clock (Bck) used by the external bus interface.
Page 17 Item Page Revision (See Manual for Details) 13.1.2 Block Diagram Figure amended Figure 13.1 Block Diagram of BSC RD/FRAME RD/WR WE7–WE0 CAS7–CAS0, CASS Memory control unit ICIORD, ICIOWR IOIS16 13.1.3 Pin Table amended Configuration Name Signals Description Data bus D63−D52, Data input/output Table 13.1 BSC Pins D31−D0...
Page 18 Item Page Revision (See Manual for Details) 13.2.8 Memory Control Description and table amended Register (MCR) Do not set RAS down mode in slave mode or partial-sharing Bit 31—RAS Down mode, or when areas 2 and 3 are both designated as (RASD): synchronous DRAM interface.
Page 19 Item Page Revision (See Manual for Details) 13.3.4 DRAM Interface Description deleted Refresh Timing: After the self-refresh is cleared, the refresh controller immediately generates a refresh request. The RAS precharge • Self-Refresh time immediately after the end of the self-refreshing can be set by bits TRC2–TRC0 in MCR.
Page 20 Item Page Revision (See Manual for Details) 13.3.5 Synchronous Figure amended DRAM Interface SH7750, SH7750S, SH7750R Figure 13.26 Example A12–A3 of 64-Bit Data Width CKIO Synchronous DRAM Connection (Area 3) CASS RD/WR D63–D48 DQM7 DQM6 Figure 13.27 Example Figure amended of 32-Bit Data Width Synchronous DRAM SH7750, SH7750S, SH7750R...
Page 21 Item Page Revision (See Manual for Details) 13.3.5 Synchronous Figure amended DRAM Interface CASS Figure 13.42 (2) Synchronous DRAM Mode Write Timing D63–D0 (Mode Register Set) (High) Connecting a 128- 494, 495 Description amended Mbit/256-Mbit • In the auto-refresh operation, the REF command is issued Synchronous DRAM twice continuously in response to a single refresh request.
Page 22 Item Page Revision (See Manual for Details) 13.3.7 PCMCIA Figure amended Interface ICIOWR Figure 13.54 Basic (write) Timing for PCMCIA I/O Card Interface D15–D0 (write) Figure 13.55 Wait Figure amended Timing for PCMCIA I/O Card Interface ICIOWR (write) D15–D0 (write) 13.3.8 MPX Interface Figure amended Figure 13.57 Example...
Page 23 Item Page Revision (See Manual for Details) 13.3.8 MPX Interface Title amended Figure 13.68 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Figure 13.69 MPX Title amended Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait...
Page 24 Item Page Revision (See Manual for Details) 14.3.2 DMA Transfer Description amended Requests The DS bit in CHCR0/CHCR1 is used to select either falling edge detection or low level detection for the DREQ signal (level detection when DS = 0, edge detection when DS = 1). DREQ is accepted after a power-on reset if TE = 0, NMIF = 0, and AE = 0, but transfer is not executed if DMA transfer is not enabled (DE = 0 or DME = 0).
Page 25 Item Page Revision (See Manual for Details) 14.5.2 Pins in DDT Figure amended Mode DBREQ/DREQ0 Figure 14.24 System BAVL/DRAK0 TR/DREQ1 Configuration in On- TDACK/DACK0 Demand Data Transfer SH7750, SH7750S, SH7750R ID1, ID0/DRAK1, DACK1 External device Mode CKIO D63–D0=DTR A25–A0, RAS, CAS, WE, DQMn, CKE Synchronous DRAM TR: Transfer request...
Page 26 Item Page Revision (See Manual for Details) 15.3.3 Multiprocessor 702 to Description of 1. and 2. added, and figure replaced Communication Function Multiprocessor Serial Data Reception: Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1) Figure 15.16 Example Figure amended of SCI Receive Data Start Stop...
Page 27 Item Page Revision (See Manual for Details) 16.1.3 Pin Note amended Configuration Note: After a power-on reset, these pins function as mode input Table 16.1 SCIF Pins pins MD1, MD2 and MD8. These pins can function as serial pins by setting the SCIF operation with the TE, RE, and CKE1 bits in SCSCR2 and the MCE bit in SCFCR2.
Page 28 Item Page Revision (See Manual for Details) 19.1.2 Block Diagram Figure amended Figure 19.1 Block Diagram of INTC Interrupt request IMASK 19.1.3 Pin Table amended Configuration Pin Name Abbreviation Function Table 19.1 INTC Pins Nonmaskable interrupt Input Input of nonmaskable interrupt request input pin signal IRL3–IRL0...
Page 29 Item Page Revision (See Manual for Details) 19.4.1 Interrupt Description and notes amended Operation Sequence 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (IMASK) in the status register (SR) of the CPU. If the request priority level is higher that the level in bits IMASK, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU.
Page 30 Item Page Revision (See Manual for Details) 20.2.1 Access to UBC Description amended Control Registers 2. Execute instructions requiring 5 states for execution after the memory store instruction that updated the register. As the CPU executes two instructions in parallel and a minimum of 0.5 state is required for execution of one instruction, 11 instructions must be inserted.
Page 31 Item Page Revision (See Manual for Details) 21.2.5 Boundary Scan Description amended Register (SDBSR) The boundary scan register (SDBSR) is a shift register that is (SH7750R Only) placed on the pads to control the chip's I/O pins. This register can perform a boundary scan test equivalent to the JTAG (IEEE Std 1149.1) standard using EXTEST, SAMPLE, and PRELOAD commands.
Page 32 Item Page Revision (See Manual for Details) Section 22 Electrical 895 to Description of lead-free products added Characteristics 1016 HD6417750RBP240 (V) HD6417750RF240 (V) HD6417750RBG240 (V) HD6417750RBP200 (V) HD6417750RF200 (V) HD6417750RBG200 (V) HD6417750SBP200 (V) HD6417750SF200 (V) HD6417750BP200M (V) HD6417750SF167 (V) HD6417750F167 (V) HD6417750SVF133 (V) HD6417750SVBF133 (V) HD6417750VF128 (V)
Page 33 Item Page Revision (See Manual for Details) 22.2 DC 900, 901 Title and table amended Characteristics Item Symbol Test Conditions Table 22.4 DC Output All output = –2 mA Characteristics voltage pins (HD6417750RBP200 = 2 mA (V), HD6417750RBG200 (V)) Table 22.5 DC Table amended Characteristics Item...
Page 34 Item Page Revision (See Manual for Details) 22.2 DC Table amended Characteristics Item Symbol Test Conditions Table 22.10 DC Output All output = –2 mA Characteristics voltage pins (HD6417750F167 (V)) = 2 mA Table 22.12 DC — Deleted Characteristics (HD6417750F167I (V)) Table 22.11 DC Table amended Characteristics...
Page 35 Item Page Revision (See Manual for Details) 22.3 AC Title amended Characteristics Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750RBP200 (V), HD6417750RBG200 (V)) Table 22.20 Clock Title amended Timing (HD6417750F167 (V), HD6417750SF167 (V) 22.3.1 Clock and Title amended Control Signal Timing Table 22.23 Clock and Control Signal Timing (HD6417750RBP240...
Page 36 Item Page Revision (See Manual for Details) 22.3.1 Clock and 936, 937 Description and notes amended Control Signal Timing HD6417750SVBT133 (V): V = 3.0 to 3.6 V, V = 1.5 V , Table 22.30 Clock and = –30 to +70°C, CL = 30 pF Control Signal Timing HD6417750SVF133 (V): V = 3.0 to 3.6 V, V...
Page 37 Item Page Revision (See Manual for Details) 22.3.2 Control Signal Table and notes amended Timing HD6417750 F167 (V) Table 22.32 Control HD6417750 HD6417750 HD6417750 SVF133 (V) SF167 (V) BP200M (V) Signal Timing (2) HD6417750 HD6417750 HD6417750 HD6417750 VF128 (V) SVBT133 (V) SF200 (V) SBP200 (V) Item...
Page 38 Item Page Revision (See Manual for Details) 22.3.3 Bus Timing 952, 953 Table and notes amended Table 22.33 Bus HD6417750S Timing (2) HD6417750S F167 (V) VF133 (V) HD6417750S HD6417750S VBT133 (V) F200 (V) Item Symbol Notes: 1. V = 3.0 to 3.6 V, V 1.5 V, T = –20 to +75°C, = 30 pF, PLL2 on...
Page 39 Item Page Revision (See Manual for Details) 22.3.3 Bus Timing Title amended Figure 22.25 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RASD = 1, RCD[1:0] = 01, CAS Latency = 3) Figure 22.26 Title amended Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst...
Page 40 Item Page Revision (See Manual for Details) 22.3.3 Bus Timing Title amended Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (RASD = 1, TRWL[2:0] = 010) Figure 22.52 PCMCIA Notes amended Memory Bus Cycle Note: *: SH7750S and SH7750R only (1) TED[2:0] = 000, TEH[2:0] = 000, No Wait (2) TED[2:0] = 001,...
Page 41 Item Page Revision (See Manual for Details) 22.3.4 Peripheral 1007 Table and notes amended Module Signal Timing HD6417750 Table 22.34 Peripheral SF167 (V) Module Signal Timing HD6417750S VF133 (V) HD6417750S HD6417750 VBT133 (V) SF200 (V) Module Item Symbol Notes: 1. Pcyc: P clock cycles 2.
Page 42 Item Page Revision (See Manual for Details) 22.3.4 Peripheral 1010 Table and notes amended Module Signal Timing Table 22.34 Peripheral Module Signal Timing HD6417750 F167 (V) HD6417750 VF128 (V) Module Item Symbol Notes: 1. Pcyc: P clock cycles 2. V = 3.0 to 3.6 V, V 1.5 V, T = –20 to +75°C,...
Page 43 Item Page Revision (See Manual for Details) E.1 Pin States 1033 Table and notes amended Reset Reset Table E.1 Pin States in (Power-On) (Manual) Hardware Reset, Power-Down Signal Name Master Slave Master Slave Standby Released Standby State, and Bus- D0–D7 Released State D8–D15 D16–D23...
Page 44 Item Page Revision (See Manual for Details) Reset Reset E.1 Pin States 1034 (Power-On) (Manual) Hardware Table E.1 Pin States in Signal Name Master Slave Master Slave Standby Released Standby WE1/CAS1/DQM1 Reset, Power-Down WE0/CAS0/DQM0 State, and Bus- DACK1–DACK0 Released State PI * PI * MD7/TXD...
Page 45 Item Page Revision (See Manual for Details) PI: Input (Pulled Up) E.1 Pin States 1035, 1036 PZ: High-impedance (Pulled Up) Table E.1 Pin States in Reset, Power-Down Notes: 1. Output when area 2 is used as DRAM. State, and Bus- 2.
Page 46 Item Page Revision (See Manual for Details) E.2 Handling of 1036 Note added Unused Pins Note: To prevent unwanted effects on other pins when using external pull-up or pull-down resistors, use independent pull-up or pull-down resistors for individual pins. Appendix F 1053 Title amended Synchronous DRAM...
Page 47: Table Of Contents
Contents Section 1 Overview ......................SH7750, SH7750S, SH7750R Groups Features ............... Block Diagram ........................Pin Arrangement ....................... 10 Pin Functions ........................14 1.4.1 Pin Functions (256-Pin BGA)................14 1.4.2 Pin Functions (208-Pin QFP)................24 1.4.3 Pin Functions (264-Pin CSP) ................32 1.4.4 Pin Functions (292-Pin BGA)................
Page 48 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode ....85 3.3.7 Address Space Identifier (ASID) ................. 85 TLB Functions ........................86 3.4.1 Unified TLB (UTLB) Configuration ..............86 3.4.2 Instruction TLB (ITLB) Configuration..............90 3.4.3 Address Translation Method................90 MMU Functions........................
Page 49 4.3.6 RAM Mode ......................123 4.3.7 OC Index Mode....................124 4.3.8 Coherency between Cache and External Memory ..........125 4.3.9 Prefetch Operation ....................125 4.3.10 Notes on Using Cache Enhanced Mode (SH7750R Only)........125 Instruction Cache (IC)....................... 128 4.4.1 Configuration ....................... 128 4.4.2 Read Operation ....................
Page 50 5.5.3 Exception Requests and BL Bit ................158 5.5.4 Return from Exception Handling................. 158 Description of Exceptions....................158 5.6.1 Resets........................159 5.6.2 General Exceptions ....................164 5.6.3 Interrupts......................178 5.6.4 Priority Order with Multiple Exceptions.............. 181 Usage Notes ........................182 Restrictions ........................
Page 51 Section 8 Pipelining ......................231 Pipelines..........................231 Parallel-Executability......................238 Execution Cycles and Pipeline Stalling ................242 Usage Notes ........................258 Section 9 Power-Down Modes ..................259 Overview........................... 259 9.1.1 Types of Power-Down Modes ................259 9.1.2 Register Configuration..................261 9.1.3 Pin Configuration....................
Page 52 9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) ......283 Usage Notes ........................286 9.9.1 Note on Current Consumption ................286 Section 10 Clock Oscillation Circuits ................287 10.1 Overview........................... 287 10.1.1 Features........................ 287 10.2 Overview of CPG......................289 10.2.1 Block Diagram of CPG..................289 10.2.2 CPG Pin Configuration ..................
Page 53 11.1.2 Block Diagram ..................... 312 11.1.3 Pin Configuration....................313 11.1.4 Register Configuration..................313 11.2 Register Descriptions ......................315 11.2.1 64 Hz Counter (R64CNT)..................315 11.2.2 Second Counter (RSECCNT) ................316 11.2.3 Minute Counter (RMINCNT) ................316 11.2.4 Hour Counter (RHRCNT)..................317 11.2.5 Day-of-Week Counter (RWKCNT)..............
Page 54 12.2.1 Timer Output Control Register (TOCR) .............. 341 12.2.2 Timer Start Register (TSTR) ................342 12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only) ..........343 12.2.4 Timer Constant Registers (TCOR) ..............344 12.2.5 Timer Counters (TCNT) ..................344 12.2.6 Timer Control Registers (TCR) ................345 12.2.7 Input Capture Register 2 (TCPR2)...............
Page 55 13.2.14 Refresh Count Register (RFCR) ................420 13.2.15 Notes on Accessing Refresh Control Registers............ 420 13.3 Operation........................... 421 13.3.1 Endian/Access Size and Data Alignment............. 421 13.3.2 Areas ........................433 13.3.3 SRAM Interface ....................438 13.3.4 DRAM Interface ....................447 13.3.5 Synchronous DRAM Interface................465 13.3.6 Burst ROM Interface....................
Page 56 14.4.1 Examples of Transfer between External Memory and an External Device with DACK ........................602 14.5 On-Demand Data Transfer Mode (DDT Mode)..............603 14.5.1 Operation ......................603 14.5.2 Pins in DDT Mode....................605 14.5.3 Transfer Request Acceptance on Each Channel ..........608 14.5.4 Notes on Use of DDT Module ................
Page 57 15.2.9 Bit Rate Register (SCBRR1)................676 15.3 Operation........................... 684 15.3.1 Overview......................684 15.3.2 Operation in Asynchronous Mode ............... 686 15.3.3 Multiprocessor Communication Function............698 15.3.4 Operation in Synchronous Mode ................. 707 15.4 SCI Interrupt Sources and DMAC ..................717 15.5 Usage Notes ........................718 Section 16 Serial Communication Interface with FIFO (SCIF) ......
Page 58 17.2 Register Descriptions ......................778 17.2.1 Smart Card Mode Register (SCSCMR1) ............. 778 17.2.2 Serial Mode Register (SCSMR1)................. 779 17.2.3 Serial Control Register (SCSCR1)............... 780 17.2.4 Serial Status Register (SCSSR1)................781 17.3 Operation .......................... 782 17.3.1 Overview......................782 17.3.2 Pin Connections ....................783 17.3.3 Data Format ......................
Page 59 19.3 Register Descriptions ......................835 19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD) ..........835 19.3.2 Interrupt Control Register (ICR)................837 19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)..839 19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only)......840 19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) ....... 841 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only) ....
Page 60 20.3.6 Condition Match Flag Setting ................868 20.3.7 Program Counter (PC) Value Saved ..............868 20.3.8 Contiguous A and B Settings for Sequential Conditions ........869 20.3.9 Usage Notes ......................870 20.4 User Break Debug Support Function ................872 20.5 Examples of Use ....................... 874 20.6 User Break Controller Stop Function................
Page 61 22.3.6 Delay Time Variation Due to Load Capacitance ..........1016 Appendix A Address List ....................1017 Appendix B Package Dimensions ................. 1023 Appendix C Mode Pin Settings ..................1027 Appendix D CKIO2ENB Pin Configuration ............. 1031 Appendix E Pin Functions ....................
Page 62 Rev.7.00 Oct. 10, 2008 Page lxii of lxxxiv REJ09B0366-0700...
Page 63 Figures Section 1 Overview Figure 1.1 Block Diagram of SH7750/SH7750S/SH7750R Group Functions ......Figure 1.2 Pin Arrangement (256-Pin BGA)................10 Figure 1.3 Pin Arrangement (208-Pin QFP) ................11 Figure 1.4 Pin Arrangement (264-Pin CSP) ................12 Figure 1.5 Pin Arrangement (292-Pin BGA)................13 Section 2 Programming Model Figure 2.1 Data Formats ......................
Page 64 Figure 4.2 Configuration of Operand Cache (SH7750, SH7750S).......... 117 Figure 4.3 Configuration of Operand Cache (SH7750R) ............118 Figure 4.4 Configuration of Write-Back Buffer ..............122 Figure 4.5 Configuration of Write-Through Buffer..............122 Figure 4.6 Configuration of Instruction Cache (SH7750, SH7750S) ........128 Figure 4.7 Configuration of Instruction Cache (SH7750R).............
Page 65 STATUS Output in Sleep → Manual Reset Sequence........... 280 Figure 9.8 STATUS Output in Deep Sleep → Interrupt Sequence ......... 281 Figure 9.9 Figure 9.10 STATUS Output in Deep Sleep → Power-On Reset Sequence ......281 Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence ......... 282 Figure 9.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation) ..
Page 66 Figure 13.6 Basic Timing of SRAM Interface................439 Figure 13.7 Example of 64-Bit Data Width SRAM Connection ..........440 Figure 13.8 Example of 32-Bit Data Width SRAM Connection ..........441 Figure 13.9 Example of 16-Bit Data Width SRAM Connection ..........442 Figure 13.10 Example of 8-Bit Data Width SRAM Connection ..........
Page 67 Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle....................483 Figure 13.39 Auto-Refresh Operation ..................485 Figure 13.40 Synchronous DRAM Auto-Refresh Timing............486 Figure 13.41 Synchronous DRAM Self-Refresh Timing ............487 Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL) ........490 Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set).....
Page 68 Figure 13.66 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)..........521 Figure 13.67 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits)........
Page 69 Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) ..............590 Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) ..............591 Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) → External Bus ......................
Page 70 Figure 14.35 Read from Synchronous DRAM Precharge Bank..........618 Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) ...... 618 Figure 14.37 Read from Synchronous DRAM (Row Hit) ............619 Figure 14.38 Write to Synchronous DRAM Precharge Bank............619 Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss)......
Page 71 Section 15 Serial Communication Interface (SCI) Figure 15.1 Block Diagram of SCI.................... 657 Figure 15.2 MD0/SCK Pin ......................674 Figure 15.3 MD7/TxD Pin......................675 Figure 15.4 RxD Pin........................675 Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) ....................
Page 72 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.1 Block Diagram of SCIF..................727 Figure 16.2 MD8/RTS2 Pin....................... 753 Figure 16.3 CTS2 Pin ........................ 754 Figure 16.4 MD1/TxD2 Pin....................... 755 Figure 16.5 MD2/RxD2 Pin ...................... 755 Figure 16.6 Sample SCIF Initialization Flowchart ..............761 Figure 16.7 Sample Serial Transmission Flowchart ..............
Page 73 Figure 18.6 MD1/TxD2 Pin....................... 808 Figure 18.7 MD2/RxD2 Pin ...................... 808 Figure 18.8 CTS2 Pin ........................ 809 Figure 18.9 MD8/RTS2 Pin....................... 810 Section 19 Interrupt Controller (INTC) Figure 19.1 Block Diagram of INTC..................826 Figure 19.2 Example of IRL Interrupt Connection..............829 Figure 19.3 Interrupt Operation Flowchart................
Page 74 Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1) ................. 959 Figure 22.19 Burst ROM Bus Cycle (No Wait) ................960 Figure 22.20 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait)..............
Page 75 Figure 22.38 DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) ..................... 980 Figure 22.39 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001) ..................... 981 Figure 22.40 DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 001) .....................
Page 76 Figure 22.58 MPX Bus Cycle: Burst Write (1) No Internal Wait (2) 1st Data (One Internal Wait), 2nd to 4th Data (No Internal Wait + External Wait Control) ........ 1000 Figure 22.59 Memory Byte Control SRAM Bus Cycles (1) Basic Read Cycle (No Wait) (2) Basic Read Cycle (One Internal Wait) (3) Basic Read Cycle (One Internal Wait + One External Wait)..................
Page 77 Tables Section 1 Overview Table 1.1 LSI Features ......................Table 1.2 Pin Functions......................14 Table 1.3 Pin Functions......................24 Table 1.4 Pin Functions......................32 Table 1.5 Pin Functions......................42 Section 2 Programming Model Table 2.1 Initial Register Values .................... 55 Section 3 Memory Management Unit (MMU) Table 3.1 MMU Registers ......................
Page 78 Table 7.3 Fixed-Point Transfer Instructions................216 Table 7.4 Arithmetic Operation Instructions................218 Table 7.5 Logic Operation Instructions.................. 220 Table 7.6 Shift Instructions ....................221 Table 7.7 Branch Instructions ....................222 Table 7.8 System Control Instructions ................... 223 Table 7.9 Floating-Point Single-Precision Instructions............225 Table 7.10 Floating-Point Double-Precision Instructions ............
Page 79 Section 13 Bus State Controller (BSC) Table 13.1 BSC Pins ........................ 360 Table 13.2 BSC Registers ......................364 Table 13.3 External Memory Space Map................. 366 Table 13.4 PCMCIA Interface Features ................... 368 Table 13.5 PCMCIA Support Interfaces .................. 369 Table 13.6 MPX Interface is Selected (Areas 0 to 6) ...............
Page 80 Table 14.16 Function of BAVL ....................648 Table 14.17 DTR Format for Clearing Request Queues ............649 Table 14.18 DMAC Interrupt-Request Codes................650 Section 15 Serial Communication Interface (SCI) Table 15.1 SCI Pins........................658 Table 15.2 SCI Registers......................659 Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ....
Page 81 Section 18 I/O Ports Table 18.1 20-Bit General-Purpose I/O Port Pins ..............811 Table 18.2 SCI I/O Port Pins....................812 Table 18.3 SCIF I/O Port Pins....................812 Table 18.4 I/O Port Registers ....................813 Section 19 Interrupt Controller (INTC) Table 19.1 INTC Pins.......................
Page 82 Table 22.15 Clock Timing (HD6417750RBP240 (V), HD6417750RBG240 (V)) ....920 Table 22.16 Clock Timing (HD6417750RF240 (V))..............920 Table 22.17 Clock Timing (HD6417750BP200M (V), HD6417750SBP200 (V), HD6417750RBP200 (V), HD6417750RBG200 (V))..........920 Table 22.18 Clock Timing (HD6417750RF200 (V))..............920 Table 22.19 Clock Timing (HD6417750SF200 (V)) ..............921 Table 22.20 Clock Timing (HD6417750F167 (V), HD6417750SF167 (V)) ......
Page 83 Appendix I Product Lineup Table I.1 SH7750/SH7750S/SH7750R Product Lineup ............1065 Appendix J Version Registers Table J.1 Register Configuration ..................1067 Rev.7.00 Oct. 10, 2008 Page lxxxiii of lxxxiv REJ09B0366-0700...
Page 84 Rev.7.00 Oct. 10, 2008 Page lxxxiv of lxxxiv REJ09B0366-0700...
Page 85: Section 1 Overview
Section 1 Overview Section 1 Overview SH7750, SH7750S, SH7750R Groups Features This LSI (SH7750, SH7750S, and SH7750R Groups) is a 32-bit RISC (reduced instruction set computer) microprocessor with a SH-4 CPU core and features upward compatibility with SH-1, SH-2, and SH-3 microcomputers at the instruction set level. It includes an instruction cache, an operand cache with a choice of copy-back or write-through mode, and an MMU (memory management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer).
Page 86 Section 1 Overview Item Features • Renesas Technology original SuperH architecture • 32-bit internal data bus • General register file: ⎯ Sixteen 32-bit general registers (and eight 32-bit shadow registers) ⎯ Seven 32-bit control registers ⎯ Four 32-bit system registers •...
Page 87 Section 1 Overview Item Features • On-chip floating-point coprocessor • Supports single-precision (32 bits) and double-precision (64 bits) • Supports IEEE754-compliant data types and exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754 •...
Page 88 Section 1 Overview Item Features • Clock pulse Choice of main clock: generator (CPG) ⎯ SH7750, SH7750S: 1/2, 1, 3, or 6 times EXTAL ⎯ SH7750R: 1, 6, or 12 times EXTAL • Clock modes: ⎯ CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock ⎯...
Page 89 Section 1 Overview Item Features • Cache memory Instruction cache (IC) [SH7750, SH7750S] ⎯ 8 Kbytes, direct mapping ⎯ 256 entries, 32-byte block length ⎯ Normal mode (8-Kbyte cache) ⎯ Index mode • Operand cache (OC) ⎯ 16 Kbytes, direct mapping ⎯...
Page 90 Section 1 Overview Item Features • Interrupt controller Five independent external interrupts: NMI, IRL3 to IRL0 (INTC) • 15-level encoded external interrupts: IRL3 to IRL0 • On-chip peripheral module interrupts: Priority level can be set for each module • User break Supports debugging by means of user break interrupts controller (UBC) •...
Page 91 Section 1 Overview Item Features • Direct memory Physical address DMA controller: access controller ⎯ SH7750, SH7750S: 4-channel (DMAC) ⎯ SH7750R: 8-channel • Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes • Address modes: ⎯ Single address mode ⎯...
Page 92 Section 1 Overview Item Features Product lineup Abbre- Voltage Operating viation (Internal) Frequency Model No. Package SH7750 1.95 V 200 MHz HD6417750BP200M 256-pin BGA 1.8 V 167 MHz HD6417750F167 208-pin QFP 1.5 V 128 MHz HD6417750VF128 SH7750S 1.95 V 200 MHz HD6417750SBP200 256-pin BGA HD6417750SF200...
Page 93: Block Diagram
Section 1 Overview Block Diagram Figure 1.1 shows an internal block diagram of this LSI. Lower 32-bit data SH-4 Core Lower 32-bit data Cache and I cache ITLB UTLB O cache controller INTC DMAC (SCIF) External bus interface 26-bit 64-bit address data Legend:...
Page 94: Pin Arrangement
Section 1 Overview Pin Arrangement IRL3 RESET IRL2 IRL1 IRL0 MD1/TXD2 MD0/SCK CA * MD2/RXD2 RD/WR2 BGA256 (Top view) DREQ1 BACK/BSREQ DREQ0 BREQ/BSACK VDDQ (IO) VSSQ (IO) VDD (internal) VSS (internal) Notes: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used.
Page 95: Figure 1.3 Pin Arrangement (208-Pin Qfp)
Section 1 Overview RESET IRL3 IRL2 IRL1 IRL0 MD2/RXD2 MD1/TXD2 MD0/SCK QFP208 Top view VDD (internal) VSS (internal) VDDQ (IO) VSSQ (IO) DREQ1 BACK/BSREQ DREQ0 BREQ/BSACK Notes: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used.
Page 96: Figure 1.4 Pin Arrangement (264-Pin Csp)
Section 1 Overview TRST IRL2 VSS-CPG XTAL EXTAL VDD-CPG TDO MD6/IOIS16 VDDQ VDDQ TCLK VSS-RTC XTAL2 EXTAL2 RESET IRL3 VDD-PLL2 STATUS0 DACK0 VDDQ MD7/TXD RDY VSS-PLL2 VSS-PLL1 VDD-PLL1 TCK VSSQ VSSQ MD3/CE2A VDDQ VDDQ VDD-RTC MD1/TXD2 NMI CKIO2ENB CTS2 IRL0 IRL1 VSSQ MD5/RAS2...
Page 97: Figure 1.5 Pin Arrangement (292-Pin Bga)
Section 1 Overview XTAL2 VSS-RTC RESET IRL1 IRL2 MD2/RXD2 IRL0 RD/WR2 MD0/SCK BGA292 (Top view) MD1/TXD2 WE2/CAS2/ WE4/CAS4/DQM4 DQM2/ICIORD DREQ1 BACK/ BSREQ BREQ/ WE7/CAS7/DQM7/ BSACK VDDQ (IO) VDD (internal) Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL circuits, crystal oscillation circuit, and RTC are used.
Page 98: Pin Functions
Section 1 Overview Pin Functions 1.4.1 Pin Functions (256-Pin BGA) Table 1.2 Pin Functions Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Bus ready RESET RESET Reset Chip select 0 Chip select 1 Chip select 4 CE1A Chip select 5 CE1B Chip select 6...
Page 99 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Data/port...
Page 100 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data BACK/ BSREQ acknowledge/ bus request BREQ/ BSACK request/bus acknowledge Data Data Clock output enable VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) WE5/CAS5/ CAS5 D47–D40 select...
Page 101 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Address VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Address Address Address CKIO Clock output CKIO CKIO CKIO VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) CKIO *...
Page 102 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX WE2/CAS2/ CAS2 ICIORD 116 Y17 D23–D16 select DQM2 DQM2/ signal ICIORD WE3/CAS3/ CAS3 ICIOWR 117 W17 D31–D24 select DQM3 DQM3/ signal ICIOWR WE6/CAS6/ CAS6 118 Y18 D55–D48 select DQM6 DQM6...
Page 103 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 143 N18 VDDQ Power IO VDD (3.3 V) 144 N17 VSSQ Power IO GND (0 V) 145 P19 Data 146 P20 Data 147 N19 Data 148 N20 Data 149 M18 VDDQ...
Page 104 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 176 F17 VSSQ Power IO GND (0 V) 177 E17 VSSQ Power IO GND (0 V) 178 E18 RD/WR2 RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR 179 D20 MD0/SCK Mode/SCI clock...
Page 105 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX MRESET SCK2 200 A16 SCK2/ SCIF clock/ SCK2 SCK2 SCK2 SCK2 MRESET manual reset 201 C14 Power Internal VDD 202 D14 Power Internal GND (0 V) 203 A15 Address 204 B14...
Page 106 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX IOIS16 228 A7 MD6/ Mode/IOIS16 IOIS16 (PCMCIA) 229 C9 VDDQ Power IO VDD (3.3 V) 230 D9 VSSQ Power IO GND (0 V) ASEBRK/ 231 B7 Pin break/ BRKACK acknowledge...
Page 107 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 250 D16 251 H17 252 H18 253 N3 254 N4 255 U4 256 V18 Legend: Input Output I/O: Input/output Power: Power supply Notes: Supply power to all power pins. For the SH7750S, supply power to RTC at a minimum in hardware standby mode.
Page 108: Pin Functions (208-Pin Qfp)
Section 1 Overview 1.4.2 Pin Functions (208-Pin QFP) Table 1.3 Pin Functions Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset Bus ready RESET RESET Reset Chip select 0 Chip select 1 Chip select 4 CE1A Chip select 5 CE1B Chip select 6 Bust start...
Page 109 Section 1 Overview Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset Data/port (Port) (Port) (Port) (Port) (Port) VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Data Data Data Data Data Data Power Internal VDD (1.8 V) Power Internal GND...
Page 110 Section 1 Overview Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset WE5/CAS5/ CAS5 D47–D40 select DQM5 DQM5 signal WE4/CAS4/ CAS4 D39–D32 select DQM4 DQM4 signal WE1/CAS1/ CAS1 D15–D8 select DQM1 DQM1 signal WE0/CAS0/ CAS0 D7–D0 select DQM0 DQM0 signal Address...
Page 111 Section 1 Overview Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset DRAK0 DMAC0 request acknowledge VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Chip select 3 (CS3) Chip select 2 (CS2) Power Internal VDD Power Internal GND (0 V)
Page 112 Section 1 Overview Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset Data VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Data Data Power Internal VDD Power Internal GND (0 V) Data Data Data Data Data Data...
Page 113 Section 1 Overview Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset Power Internal GND (0 V) Data/port (Port) (Port) (Port) (Port) (Port) Data ACCSIZE2 VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) MD0/SCK Mode/SCI clock MD1/TXD2 Mode SCIF data...
Page 114 Section 1 Overview Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset MRESET SCK2 SCK2/ SCIF clock/ SCK2 SCK2 SCK2 SCK2 MRESET manual reset Power Internal VDD Power Internal GND (0 V) Address Address Address Address Address Address VDDQ Power IO VDD (3.3 V)
Page 115 Section 1 Overview Memory Interface SRAM DRAM SDRAM PCMCIA MPX Pin Name Function Reset Data out (H-UDI) Power Internal VDD Power Internal GND (0 V) Mode (H-UDI) Clock (H-UDI) Data in (H-UDI) TRST Reset (H-UDI) VDD-PLL2 Power PLL2 VDD (3.3V) VSS-PLL2 Power PLL2 GND (0V)
Page 116: Pin Functions (264-Pin Csp)
Section 1 Overview 1.4.3 Pin Functions (264-Pin CSP) Table 1.4 Pin Functions Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Bus ready RESET RESET Reset Chip select 0 Chip select 1 Chip select 4 CE1A Chip select 5 CE1B Chip select 6 Bus start...
Page 117 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data/port (Port) (Port) (Port) (Port) (Port) VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port)
Page 118 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX BACK/ BSREQ acknowledge/ bus request BREQ/ Bus request/bus BSACK acknowledge Data Data Clock output enable VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) WE5/CAS5/ CAS5 D47–D40 select...
Page 119 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX VSSQ Power IO GND (0 V) Address Address Address CKIO Clock output CKIO CKIO CKIO VDDQ Power IO VDD (3.3 V) VSSQ Power IO GND (0 V) CKIO2 CKIO* CKIO...
Page 120 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 115 R13 WE3/CAS3/ CAS3 ICIOWR D31–D24 select DQM3 DQM3/ signal ICIOWR 116 R14 WE6/CAS6/ CAS6 D55–D48 select DQM6 DQM6 signal 117 U14 VDDQ Power IO VDD (3.3 V) 118 U17 VSSQ Power IO GND (0 V) 119 U15 WE7/CAS7/...
Page 121 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 143 L17 Data 144 L12 Data 145 K15 Data 146 K14 Data 147 K17 VDDQ Power IO VDD (3.3 V) 148 K13 VSSQ Power IO GND (0 V) 149 K16 Data 150 K12...
Page 122 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 175 E14 RD/WR2 RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR 176 F16 MD0/SCK Mode/SCI1 clock 177 C15 MD1/TXD2 Mode/SCIF TXD2 TXD2 TXD2 TXD2 TXD2 data output 178 E15 MD2/RXD2 I Mode/SCIF RXD2...
Page 123 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 198 D11 VSS Power Internal GND (0 V) 199 C11 A18 Address 200 F12 Address 201 B11 VDDQ Power IO VDD (3.3 V) 202 E11 VSSQ Power IO GND (0 V) 203 A11 Address...
Page 124 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX ASEBRK/ 227 E6 Pin break/ BRKACK acknowledge (H-UDI 228 A6 Data out (H-UDI) 229 D7 Power Internal VDD (1.5 V) 230 B7 Power Internal GND (0 V) 231 E5 Mode (H-UDI) 232 C6...
Page 125 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 256 M7 NC-13 257 N2 NC-14 258 P2 NC-15 259 P16 NC-16 260 R17 NC-17 261 T4 NC-18 262 T14 NC-19 263 U3 NC-20 264 U4 NC-21 Legend: Input...
Page 126: Pin Functions (292-Pin Bga)
Section 1 Overview 1.4.4 Pin Functions (292-Pin BGA) Table 1.5 Pin Functions Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Bus ready RESET RESET Reset Chip select 0 Chip select 1 Chip select 4 CE1A Chip select 5 CE1B Chip select 6 Bus start...
Page 127 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX Data/port (Port) (Port) (Port) (Port) (Port) VDDQ Power IO VDD (3.3 V) Power GND (0 V) Data/port (Port) (Port) (Port) (Port) (Port) Data/port (Port) (Port) (Port) (Port) (Port) Data/port...
Page 128 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX BREQ/ Bus request/ BSACK bus acknowledge Data Data Clock output enable VDDQ Power IO VDD (3.3 V) Power GND (0 V) WE5/CAS5/ CAS5 D47–D40 select DQM5 DQM5 signal WE4/CAS4/...
Page 129 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX W10 A7 Address CKIO Clock output CKIO CKIO CKIO VDDQ Power IO VDD (3.3 V) U10 VSS Power GND (0 V) CKIO2 CKIO* CKIO CKIO CKIO W11 A6 Address Address...
Page 130 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 119 V16 VDDQ Power IO VDD (3.3 V) 120 U16 VSS Power GND (0 V) WE7/CAS7/ CAS7 121 V18 D63–D56 select DQM7 DQM7/REG signal 122 W18 D23 Data 123 Y18 Data...
Page 131 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 150 M17 VSS Power GND (0 V) 151 M19 D55 Data 152 M20 D56 Data 153 L19 Data 154 L20 Data 155 L18 VDDQ Power IO VDD (3.3 V) 156 L17 Power GND (0 V) 157 K18...
Page 132 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 182 D20 IRL0 Interrupt 0 183 C19 IRL1 Interrupt 1 184 C20 IRL2 Interrupt 2 IRL3 185 B19 Interrupt 3 186 B20 Nonmaskable interrupt 187 A20 XTAL2 RTC crystal resonator pin...
Page 133 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 210 A13 Address 211 C12 VDDQ Power IO VDD (3.3 V) 212 D12 VSS Power GND (0 V) 213 B12 Address 214 A12 Address CE2A 215 B11 MD3/CE2A I/O Mode/ PCMCIA-CE...
Page 134 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX TRST 238 B5 Reset (H-UDI) CKIO2ENB I CKIO2, RD2, 239 C4 RD/WR2 enable 240 D6 Power GND (0 V) 241 A5 VDD-PLL2 Power PLL2 VDD (3.3 V) 242 B4 VSS-PLL2 Power PLL2 GND (0 V)
Page 135 Section 1 Overview Memory Interface Pin Name Function Reset SRAM DRAM SDRAM PCMCIA MPX 269 L13 Power GND (0 V) 270 K13 Power GND (0 V) 271 J13 Power GND (0 V) 272 H13 VSS Power GND (0 V) 273 H12 VSS Power GND (0 V) 274 H11 VSS Power GND (0 V)
Page 136 Section 1 Overview Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on- chip RTC is used. NC pins must be left completely open, and not connected to a power supply, GND, etc. CKIO2 is not connected to PLL2. Rev.7.00 Oct.
Page 137: Section 2 Programming Model
Section 2 Programming Model Section 2 Programming Model Data Formats The data formats handled by the SH-4 are shown in figure 2.1. Byte (8 bits) Word (16 bits) Longword (32 bits) 31 30 Single-precision floating-point (32 bits) fraction 63 62 Double-precision floating-point (64 bits) fraction Figure 2.1 Data Formats...
Page 138: Register Configuration
Section 2 Programming Model Register Configuration 2.2.1 Privileged Mode and Banks Processor Modes: The SH-4 has two processor modes, user mode and privileged mode. The SH-4 normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted.
Page 139: Table 2.1 Initial Register Values
Section 2 Programming Model Floating-Point Registers: There are thirty-two floating-point registers, FR0–FR15 and XF0– XF15. FR0–FR15 and XF0–XF15 can be assigned to either of two banks (FPR0_BANK0– FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1). FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating- point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0–...
Page 140: Figure 2.2 Cpu Register Configuration In Each Processor Mode
Section 2 Programming Model R0 _ BANK0 R0 _ BANK1 R0 _ BANK0 *1 *4 *1 *2 *1 *3 R1 _ BANK0 R1 _ BANK0 R1 _ BANK1 R2 _ BANK0 R2 _ BANK0 R2 _ BANK1 R3 _ BANK0 R3 _ BANK1 R3 _ BANK0 R4 _ BANK0...
Page 141: General Registers
Section 2 Programming Model 2.2.2 General Registers Figure 2.3 shows the relationship between the processor modes and general registers. The SH-4 has twenty-four 32-bit general registers (R0_BANK0–R7_BANK0, R0_BANK1–R7_BANK1, and R8–R15). However, only 16 of these can be accessed as general registers R0–R15 in one processor mode.
Page 142: Figure 2.3 General Registers
Section 2 Programming Model SR.MD = 0 or (SR.MD = 1, SR.RB = 0) (SR.MD = 1, SR.RB = 1) R0_BANK0 R0_BANK0 R1_BANK0 R1_BANK0 R2_BANK0 R2_BANK0 R3_BANK0 R3_BANK0 R4_BANK0 R4_BANK0 R5_BANK0 R5_BANK0 R6_BANK0 R6_BANK0 R7_BANK0 R7_BANK0 R0_BANK1 R0_BANK1 R1_BANK1 R1_BANK1 R2_BANK1 R2_BANK1 R3_BANK1...
Page 143: Floating-Point Registers
Section 2 Programming Model 2.2.3 Floating-Point Registers Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers, divided into two banks (FPR0_BANK0–FPR15_BANK0 and FPR0_BANK1–FPR15_BANK1). These 32 registers are referenced as FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0–XF15, XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference name is determined by the FR bit in FPSCR (see figure 2.4).
Page 144 Section 2 Programming Model • Single-precision floating-point extended register pairs, XDi (8 registers): An XD register comprises two XF registers XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} •...
Page 145: Figure 2.4 Floating-Point Registers
Section 2 Programming Model FPSCR.FR = 0 FPSCR.FR = 1 FPR0_BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 DR10 FR10 XF10 XD10 FPR11_BANK0 FR11 XF11 FPR12_BANK0 FV12 DR12 FR12 XF12 XD12 FPR13_BANK0 FR13 XF13 FPR14_BANK0 DR14 FR14 XF14 XD14...
Page 146: Control Registers
Section 2 Programming Model 2.2.4 Control Registers Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000 00XX 1111 00XX (X: undefined)) 31 30 29 28 27 16 15 14 — MD RB BL — —...
Page 147: System Registers
Section 2 Programming Model Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current contents of SR are saved to SSR in the event of an exception or interrupt. Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The address of an instruction at which an interrupt or exception occurs is saved to SPC.
Page 148 Section 2 Programming Model Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. •...
Page 149: Memory-Mapped Registers
Section 2 Programming Model When an FPU operation instruction is executed, the FPU exception cause field is cleared to zero first. When the next FPU exception is occured, the corresponding bits in the FPU exception cause field and FPU exception flag field are set to 1. The FPU exception flag field holds the status of the exception generated after the field was last cleared.
Page 150: Data Format In Registers
Section 2 Programming Model Note: Do not access undefined locations in either area The operation of an access to an undefined location is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined. Data Format in Registers Register operands are always longwords (32 bits).
Page 151: Processor States
Section 2 Programming Model A + 1 A + 2 A + 3 A + 11 A + 10 A + 9 A + 8 Address A Address A + 8 Byte 0 Byte 1 Byte 2 Byte 3 Byte 3 Byte 2 Byte 1 Byte 0 0 15 Address A + 4...
Page 152: Figure 2.6 Processor State Transitions
Section 2 Programming Model contents of the vector base address and the vector offset. See section 5, Exceptions, for more information on resets, general exceptions, and interrupts. Program Execution State: In this state the CPU executes program instructions in sequence. Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced.
Page 153: Processor Modes
Section 2 Programming Model Processor Modes There are two processor modes: user mode and privileged mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset state or exception state is entered, the MD bit is set to 1.
Page 154 Section 2 Programming Model Rev.7.00 Oct. 10, 2008 Page 70 of 1074 REJ09B0366-0700...
Page 155: Section 3 Memory Management Unit (Mmu)
Section 3 Memory Management Unit (MMU) Section 3 Memory Management Unit (MMU) Overview 3.1.1 Features The SH-4 can handle 29-bit external memory space from an 8-bit address space identifier and 32- bit logical (virtual) address space. Address translation from virtual address to physical address is performed using the memory management unit (MMU) built into the SH-4.
Page 156 Section 3 Memory Management Unit (MMU) of the MMU is to map a number of virtual memory areas onto physical memory in an efficient manner. It is also provided with memory protection functions to prevent a process from inadvertently accessing another process's physical memory. When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake.
Page 157: Figure 3.1 Role Of The Mmu
Section 3 Memory Management Unit (MMU) Virtual memory Physical Process 1 memory Physical Physical Process 1 memory memory Process 1 Virtual Physical Process 1 Process 1 memory memory Physical memory Process 2 Process 2 Process 3 Process 3 Figure 3.1 Role of the MMU Rev.7.00 Oct.
Page 158: Register Configuration
Section 3 Memory Management Unit (MMU) 3.1.3 Register Configuration The MMU registers are shown in table 3.1. Table 3.1 MMU Registers Abbrevia- Initial Area 7 Access Value * Address * Address * Name tion Size Page table entry high PTEH Undefined H'FF00 0000 H'1F00 0000 32 register...
Page 159: Register Descriptions
Section 3 Memory Management Unit (MMU) Register Descriptions There are six MMU-related registers. 1. PTEH 10 9 — — ASID 2. PTEL 31 30 29 28 10 9 — — — — V SZ SZ C D SH WT 3. PTEA 4.
Page 160 Section 3 Memory Management Unit (MMU) 1. Page table entry high register (PTEH): Longword access to PTEH can be performed from H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID).
Page 161 Section 3 Memory Management Unit (MMU) URC: UTLB replace counter SQMD: Store queue mode bit Single virtual mode bit TLB invalidate Address translation bit Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00 0010 in area 7.
Page 162 Section 3 Memory Management Unit (MMU) LRUI ITLB entry 0 is updated ITLB entry 1 is updated ITLB entry 2 is updated ITLB entry 3 is updated Other than the above Setting prohibited Ensure that values for which “Setting prohibited” is indicated in the above table are not set at the discretion of software.
Page 163: Address Space
Section 3 Memory Management Unit (MMU) MMU exceptions are not generated when the AT bit is 0. In the case of software that does not use the MMU, therefore, the AT bit should be cleared to 0. Address Space 3.3.1 Physical Address Space The SH-4 supports a 32-bit physical address space, and can access a 4-Gbyte address space.
Page 164 Section 3 Memory Management Unit (MMU) In the SH7750, the CPU cannot access a PCMCIA interface area. When performing access from the CPU to a PCMCIA interface area in the SH7750S or the SH7750R, access is always performed using the values of the SA and TC bits set in the PTEA register. The PCMCIA interface area is always accessed by the DMAC with the values of CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC in the DMAC.
Page 165: Figure 3.4 P4 Area
Section 3 Memory Management Unit (MMU) H'E000 0000 Store queue H'E400 0000 Reserved area H'F000 0000 Instruction cache address array H'F100 0000 Instruction cache data array H'F200 0000 Instruction TLB address array H'F300 0000 Instruction TLB data arrays 1 and 2 H'F400 0000 Operand cache address array H'F500 0000...
Page 166: External Memory Space
Section 3 Memory Management Unit (MMU) The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2. The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address array.
Page 167: Virtual Address Space
Section 3 Memory Management Unit (MMU) 3.3.3 Virtual Address Space Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in the SH-4 to be mapped onto any external memory space in 1-, 4-, or 64-Kbyte, or 1-Mbyte, page units.
Page 168: On-Chip Ram Space
Section 3 Memory Management Unit (MMU) 0 for the C bit on that page. At that time, the regions are accessed by the values of SA and TC set in page units of the TLB. Here, access to the PCMCIA interface area by accessing an area of P1, P2, or P4 from the CPU is disabled.
Page 169: Address Translation
Section 3 Memory Management Unit (MMU) 3.3.5 Address Translation When the MMU is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. The address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes.
Page 170: Tlb Functions
Section 3 Memory Management Unit (MMU) Note: In single virtual memory mode, entries with the same virtual page number (VPN) but different ASIDs cannot be set in the TLB simultaneously. TLB Functions 3.4.1 Unified TLB (UTLB) Configuration The unified TLB (UTLB) is so called because of its use for the following two purposes: 1.
Page 171: Figure 3.8 Relationship Between Page Size And Address Format
Section 3 Memory Management Unit (MMU) • 1-Kbyte page Virtual address Physical address 10 9 10 9 Offset Offset • 4-Kbyte page Virtual address Physical address 12 11 12 11 Offset Offset • 64-Kbyte page Virtual address Physical address 16 15 16 15 Offset Offset...
Page 172 Section 3 Memory Management Unit (MMU) • SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. • SZ: Page size bits Specify the page size. 00: 1-Kbyte page 01: 4-Kbyte page 10: 64-Kbyte page 11: 1-Mbyte page •...
Page 173 Section 3 Memory Management Unit (MMU) • C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1.
Page 174: Instruction Tlb (Itlb) Configuration
Section 3 Memory Management Unit (MMU) 3.4.2 Instruction TLB (ITLB) Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 3.9 shows the overall configuration of the ITLB.
Page 175: Figure 3.10 Flowchart Of Memory Access Using Utlb
Section 3 Memory Management Unit (MMU) Data access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area On-chip I/O access CCR.OCE? MMUCR.AT = 1 CCR.CB? CCR.WT? SH = 0...
Page 176: Figure 3.11 Flowchart Of Memory Access Using Itlb
Section 3 Memory Management Unit (MMU) Instruction access to virtual address (VA) VA is VA is VA is VA is in P0, U0, in P4 area in P2 area in P1 area or P3 area Access prohibited CCR.ICE? MMUCR.AT = 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)
Page 177: Mmu Functions
Section 3 Memory Management Unit (MMU) MMU Functions 3.5.1 MMU Hardware Management The SH-4 supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2.
Page 178: Hardware Itlb Miss Handling
Section 3 Memory Management Unit (MMU) issued by a program in the P1 or P2 area. The operation of the LDTLB instruction is shown in figure 3.12. MMUCR 26 25 24 23 18 17 16 15 10 9 8 7 3 2 1 0 LRUI —...
Page 179: Avoiding Synonym Problems
Section 3 Memory Management Unit (MMU) procedure is known as hardware ITLB miss handling. If the necessary address translation information is not found in the UTLB search, an instruction TLB miss exception is generated and processing passes to software. 3.5.5 Avoiding Synonym Problems When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise.
Page 180: Mmu Exceptions
Section 3 Memory Management Unit (MMU) MMU Exceptions There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception.
Page 181 Section 3 Memory Management Unit (MMU) Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3.
Page 182: Instruction Tlb Protection Violation Exception
Section 3 Memory Management Unit (MMU) 3.6.3 Instruction TLB Protection Violation Exception An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below.
Page 183: Data Tlb Miss Exception
Section 3 Memory Management Unit (MMU) Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3.
Page 184: Data Tlb Protection Violation Exception
Section 3 Memory Management Unit (MMU) Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry.
Page 185: Initial Page Write Exception
Section 3 Memory Management Unit (MMU) 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the data TLB protection violation exception handling routine. Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow.
Page 186: Memory-Mapped Tlb Configuration
Section 3 Memory Management Unit (MMU) Software Processing (Initial Page Write Exception Handling Routine): The following processing should be carried out as the responsibility of software: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3.
Page 187: Itlb Address Array
Section 3 Memory Management Unit (MMU) 3.7.1 ITLB Address Array The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 188: Itlb Data Array 1
Section 3 Memory Management Unit (MMU) 3.7.2 ITLB Data Array 1 ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 189: Itlb Data Array 2
Section 3 Memory Management Unit (MMU) 3.7.3 ITLB Data Array 2 ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 190: Utlb Address Array
Section 3 Memory Management Unit (MMU) 3.7.4 UTLB Address Array The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing).
Page 191: Utlb Data Array 1
Section 3 Memory Management Unit (MMU) 14 13 2 1 0 Address field 1 1 1 1 0 1 1 0 30 29 28 10 9 8 7 Data field ASID Legend: VPN: Virtual page number ASID: Address space identifier Association bit Validity bit Entry...
Page 192: Utlb Data Array 2
Section 3 Memory Management Unit (MMU) 14 13 Address field 1 1 1 1 0 1 1 1 0 30 29 28 10 9 8 7 2 1 0 Data field Legend: SH WT PPN: Physical page number Protection key data Validity bit Cacheability bit Entry...
Page 193: Usage Notes
Section 3 Memory Management Unit (MMU) Address field 1 1 1 1 0 1 1 1 1 Data field Legend: Timing control bit Space attribute bits Entry Reserved bits (0 write value, undefined read value) Figure 3.18 Memory-Mapped UTLB Data Array 2 Usage Notes 1.
Page 194 Section 3 Memory Management Unit (MMU) Rev.7.00 Oct. 10, 2008 Page 110 of 1074 REJ09B0366-0700...
Page 195: Section 4 Caches
Section 4 Caches Section 4 Caches Overview 4.1.1 Features An SH7750 or SH7750S has an on-chip 8-Kbyte instruction cache (IC) for instructions and 16- Kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 Kbytes) may alternatively be used as on-chip RAM.
Page 196: Table 4.2 Cache Features (Sh7750R)
Section 4 Caches Table 4.2 Cache Features (SH7750R) Item Instruction Cache Operand Cache Capacity 16-Kbyte cache 32-Kbyte cache or 16-Kbyte cache + 16-Kbyte RAM Type 2-way set-associative 2-way set-associative Line size 32 bytes 32 bytes Entries 256 entries/way 512 entries/way Write method Copy-back/write-through selectable Replacement method...
Page 197: Register Configuration
Section 4 Caches 4.1.2 Register Configuration Table 4.4 shows the cache control registers. Table 4.4 Cache Control Registers Initial Area 7 Access Value * Address * Address * Name Abbreviation R/W Size Cache control H'0000 0000 H'FF00 001C H'1F00 001C register Queue address QACR0...
Page 198: Register Descriptions
Section 4 Caches Register Descriptions There are three cache and store queue related control registers, as shown in figure 4.1. 31 30 16 15 12 11 10 9 8 7 6 5 4 3 2 EMODE * ICI ICE WT OCE QACR0 2 1 0 AREA...
Page 199 Section 4 Caches an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or U0 area should be located at least eight instructions after the CCR update instruction. •...
Page 200: Operand Cache (Oc)
Section 4 Caches • CB: Copy-back bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode • WT: Write-through bit Indicates the P0, U0, and P3 area cache write mode. When address translation is performed, the value of the WT bit in the page management information has priority. 0: Copy-back mode 1: Write-through mode •...
Page 201: Figure 4.2 Configuration Of Operand Cache (Sh7750, Sh7750S)
Section 4 Caches Figure 4.3 shows the configuration of the operand cache for the SH7750R. Effective address 26 25 13 12 11 10 9 5 4 3 2 1 RAM area determination [11:5] [13] [12] Longword (LW) selection Address array Data array 19 bits 1 bit 1 bit...
Page 202: Figure 4.3 Configuration Of Operand Cache (Sh7750R)
Section 4 Caches Effective address 26 25 13 12 RAM area judgment Longword (LW) selection [12:5] [13] Entry selection Address array (way 0, way 1) Data array (way 0, way 1) Tag address 19 bits 1 bit 1 bit 32 bits 32 bits 32 bits 32 bits...
Page 203 Section 4 Caches • Tag Stores the upper 19 bits of the 29-bit external memory address of the data line to be cached. The tag is not initialized by a power-on or manual reset. • V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid.
Page 204: Read Operation
Section 4 Caches 4.3.2 Read Operation When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2.
Page 205: Write Operation
Section 4 Caches 4.3.3 Write Operation When the OC is enabled (CCR.OCE = 1) and data is written by means of an effective address to a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2.
Page 206: Write-Back Buffer
Section 4 Caches 3e. Cache miss (with copy-back/write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are first saved in the write-back buffer, and then a data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective address of the data field of the cache line indexed by effective address bits [13:5].
Page 207: Ram Mode
Section 4 Caches 4.3.6 RAM Mode Setting CCR.ORA to 1 enables half of the operand cache to be used as RAM. In the SH7750 or SH7750S, the 8 Kbytes of operand cache entries 128 to 255 and 384 to 511 are used as RAM. In the SH7750/SH7750S-compatible mode of the SH7750R, the 8-Kbyte area otherwise used for OC entries 256 to 511 is designated as a RAM area.
Page 208: Oc Index Mode
Section 4 Caches As the distinction between RAM areas 1 and 2 is indicated by address bit [25], the area from H'7DFF F000 to H'7E00 0FFF should be used to secure a continuous 8-Kbyte RAM area. Examples of RAM usage with the SH7750R is shown below. •...
Page 209: Coherency Between Cache And External Memory
Section 4 Caches 4.3.8 Coherency between Cache and External Memory Coherency between cache and external memory should be assured by software. In this LSI, the following four new instructions are supported for cache operations. Details of these instructions are given in the Programming Manual. Invalidate instruction: OCBI @Rn Cache invalidation (no write-back)
Page 210 Section 4 Caches Note: This includes a break triggered by a debugging tool swapping an instruction (a break occurring when a TRAPA instruction or undefined instruction code H'FFFD is swapped for an instruction). Condition 4: A store instruction (MOV, FMOV, AND.B, OR, B, XOR.B, MOVCA.L, STC.L, or STS.L) that accesses internal RAM (H'7C000000 to H'7FFFFFFF) exists within four instructions after the instruction associated with the exception or interrupt described in condition 3.
Page 211 Section 4 Caches Example 3 A debugging tool generates a break to swap an instruction. Original Instruction String After Instruction Swap Break MOV.L #H'C000000, R0 MOV.L #H'7C000000, R0 Contains address corresponding to R0. ADD R0, R0 TRAPA #H'01 R0 address is not a problem in original instruction string.
Page 212: Instruction Cache (Ic)
Section 4 Caches Instruction Cache (IC) 4.4.1 Configuration The instruction cache of the SH7750 or SH7750S is of the direct-mapping type and consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32-byte data (16 instructions). The SH7750R's instruction cache is 2-way set associative.
Page 213: Figure 4.7 Configuration Of Instruction Cache (Sh7750R)
Section 4 Caches Effective address 13 12 11 10 [11:5] [12] Entry Longword (LW) selection selection Address array (way 0, way1) Data array (way 0, way 1) Tag address 19 bits 1 bit 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits...
Page 214: Read Operation
Section 4 Caches • Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU (SH7750R only) In a 2-way set-associative cache, up to 2 items of data can be registered in the cache at each entry address.
Page 215: Ic Index Mode
Section 4 Caches 4.4.3 IC Index Mode Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is performed using bits [12:5] of the effective address.
Page 216: Ic Data Array
Section 4 Caches 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0.
Page 217: Oc Address Array
Section 4 Caches In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0].
Page 218 Section 4 Caches is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed.
Page 219: Oc Data Array
Section 4 Caches 5 4 3 2 1 0 Address field 1 1 1 1 0 1 0 0 Entry 10 9 Data field Legend: V: Validity bit U: Dirty bit A: Association bit : Reserved bits (0 write value, undefined read value) Figure 4.10 Memory-Mapped OC Address Array 4.5.4 OC Data Array...
Page 220: Memory-Mapped Cache Configuration (Sh7750R)
Section 4 Caches 2 1 0 Address field 1 1 1 1 0 1 0 1 Entry Data field Longword data Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.11 Memory-Mapped OC Data Array Memory-Mapped Cache Configuration (SH7750R) To enable the management of the IC and OC by software, a program running in the privileged mode is allowed to access their contents.
Page 221: Ic Address Array
Section 4 Caches 4.6.1 IC Address Array The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 222: Ic Data Array
Section 4 Caches 5 4 3 2 1 0 Address field 1 1 1 1 0 0 0 0 Entry 10 9 Data field Legend: V: Validity bit A: Association bit : Reserved bits (0 write value, undefined read value Figure 4.12 Memory-Mapped IC Address Array 4.6.2 IC Data Array...
Page 223: Oc Address Array
Section 4 Caches 2 1 0 Address field 1 1 1 1 0 0 0 1 Entry Data field Longword data Legend: L: Longword specification bits : Reserved bits (0 write value, undefined read value) Figure 4.13 Memory-Mapped IC Data Array 4.6.3 OC Address Array The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area.
Page 224: Figure 4.14 Memory-Mapped Oc Address Array
Section 4 Caches 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the way and the entry set in the address field. The A bit in the address field should be cleared to 0.
Page 225: Oc Data Array
Section 4 Caches 4.6.4 OC Data Array The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification.
Page 226: Summary Of The Memory-Mapping Of The Oc
Section 4 Caches 4.6.5 Summary of the Memory-Mapping of the OC The address ranges to which the OC is memory-mapped in the double-sized cache mode of the SH7750R are summarized below, using examples of data-array access. • In normal mode (CCR.ORA = 0) H'F500 0000 to H'F500 3FFF (16 KB ): Way 0 (entries 0 to 511) H'F500 4000 to H'F500 7FFF (16 KB ): Way 1 (entries 0 to 511) In the same pattern, shadows of the cache area are created in 32-Kbyte blocks until H'F5FF...
Page 227: Sq Writes
Section 4 Caches SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7] SQ1[0] SQ1[1] SQ1[2] SQ1[3] SQ1[4] SQ1[5] SQ1[6] SQ1[7] Figure 4.16 Store Queue Configuration 4.7.2 SQ Writes A write to the SQs can be performed using a store instruction (MOV) on P4 area H'E000 0000 to H'E3FF FFFC.
Page 228 Section 4 Caches When a prefetch instruction is issued for the SQ area, address translation is performed and external memory address bits [28:10] are generated in accordance with the SZ bit specification. For external memory address bits [9:5], the address prior to address translation is generated in the same way as when the MMU is off.
Page 229: Sq Protection
Section 4 Caches 4.7.4 SQ Protection Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is on or off. In the SH7750 or SH7750S, if an exception occurs in an SQ write, the SQ contents may be corrupted.
Page 230: Sq Usage Notes
Section 4 Caches 4.7.6 SQ Usage Notes If an exception occurs within the three instructions preceding an instruction that writes to an SQ in the SH7750 and SH7750S, a branch may be made to the exception handling routine after execution of the SQ write that should be suppressed when an exception occurs. This may be due to the bug described in (1) or (2) below.
Page 231 Section 4 Caches Example 2: When an instruction that generates an exception branches using a branch instruction Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs. Instruction 2 ; May be executed if instruction 1 is a delay slot instruction and an instruction to store data to SQ. Instruction 3 Instruction 4 Instruction 5...
Page 232 Section 4 Caches 2. If the instruction at the address referred to by SPC is a branch instruction the two instructions at the branch destination may be affected. Rev.7.00 Oct. 10, 2008 Page 148 of 1074 REJ09B0366-0700...
Page 233: Section 5 Exceptions
Section 5 Exceptions Section 5 Exceptions Overview 5.1.1 Features Exception handling is processing handled by a special routine, separate from normal program processing, that is executed by the CPU in case of abnormal events. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing.
Page 234: Register Descriptions
Section 5 Exceptions Register Descriptions There are three registers related to exception handling. Addresses are allocated to these registers, and they can be accessed by specifying the P4 address or area 7 address. 1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12- bit exception code.
Page 235: Exception Handling Functions
Section 5 Exceptions Exception Handling Functions 5.3.1 Exception Handling Flow In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15(SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address.
Page 236: Exception Types And Priorities
Section 5 Exceptions Exception Types and Priorities Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 5.2 Exceptions Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Reset Abort type Power-on reset...
Page 237 Section 5 Exceptions Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Nonmaskable interrupt — (VBR) H'600 H'1C0 type External IRL3–IRL0 (VBR) H'600 H'200 interrupts H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360...
Page 238 Section 5 Exceptions Exception Execution Priority Priority Vector Exception Category Mode Exception Level Order Address Offset Code Interrupt Completion Peripheral DMAC DMTE0 (VBR) H'600 H'640 type module DMTE1 H'660 interrupt DMTE2 H'680 (module/ source) DMTE3 H'6A0 DMTE4 H'780 DMTE5 H'7A0 DMTE6 H'7C0 DMTE7...
Page 239: Exception Flow
Section 5 Exceptions Exception Flow 5.5.1 Exception Flow Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different kinds of exceptions (reset/general exception/interrupt).
Page 240: Exception Source Acceptance
Section 5 Exceptions 5.5.2 Exception Source Acceptance A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions—the general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception—are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline.
Page 241: Figure 5.3 Example Of General Exception Acceptance Order
Section 5 Exceptions Pipeline flow: TLB miss (data access) Instruction n Instruction n+1 General illegal instruction exception TLB miss (instruction access) Instruction n+2 Legend: IF: Instruction fetch ID: Instruction decode Instruction n+3 EX: Instruction execution MA: Memory access WB: Write-back Order of detection: General illegal instruction exception (instruction n+1) and TLB miss (instruction n+2) are detected simultaneously...
Page 242: Exception Requests And Bl Bit
Section 5 Exceptions 5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, general exception and interrupts are accepted. When the BL bit in SR is 1 and a general exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A000 0000).
Page 243: Resets
Section 5 Exceptions 5.6.1 Resets (1) Power-On Reset • Sources: ⎯ SCK2 pin high level and RESET pin low level ⎯ When the watchdog timer overflows while the WT/IT bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits. •...
Page 244 Section 5 Exceptions (2) Manual Reset • Sources: ⎯ SCK2 pin low level and RESET pin low level ⎯ When a general exception other than a user break occurs while the BL bit is set to 1 in SR ⎯ When the watchdog timer overflows while the WT/IT bit and RSTS bit are both set to 1 in WTCSR.
Page 245: Table 5.3 Types Of Reset
Section 5 Exceptions Table 5.3 Types of Reset Reset State Transition Conditions Internal States RESET Type SCK2 On-Chip Peripheral Modules Power-on reset High Initialized See Register Configuration in each section Manual reset Initialized (3) H-UDI Reset • Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion) •...
Page 246 Section 5 Exceptions (4) Instruction TLB Multiple-Hit Exception • Source: Multiple ITLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 247 Section 5 Exceptions (5) Operand TLB Multiple-Hit Exception • Source: Multiple UTLB address matches • Transition address: H'A000 0000 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred.
Page 248: General Exceptions
Section 5 Exceptions 5.6.2 General Exceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 249 Section 5 Exceptions (2) Instruction TLB Miss Exception • Source: Address mismatch in ITLB address comparison • Transition address: VBR + H'0000 0400 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 250 Section 5 Exceptions (3) Initial Page Write Exception • Source: TLB is hit in a store access, but dirty bit D = 0 • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 251 Section 5 Exceptions (4) Data TLB Protection Violation Exception • Source: The access does not accord with the UTLB protection information (PR bits) shown below. Privileged Mode User Mode Only read access possible Access not possible Read/write access possible Access not possible Only read access possible Only read access possible Read/write access possible...
Page 252 Section 5 Exceptions (5) Instruction TLB Protection Violation Exception • Source: The access does not accord with the ITLB protection information (PR bits) shown below. Privileged Mode User Mode Access possible Access not possible Access possible Access possible • Transition address: VBR + H'0000 0100 •...
Page 253 Section 5 Exceptions (6) Data Address Error • Sources: ⎯ Word data access from other than a word boundary (2n +1) ⎯ Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) ⎯...
Page 254 Section 5 Exceptions (7) Instruction Address Error • Sources: ⎯ Instruction fetch from other than a word boundary (2n +1) ⎯ Instruction fetch from area H'8000 0000–H'FFFF FFFF in user mode • Transition address: VBR + H'0000 0100 • Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10].
Page 255 Section 5 Exceptions (8) Unconditional Trap • Source: Execution of TRAPA instruction • Transition address: VBR + H'0000 0100 • Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The values of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR.
Page 256 Section 5 Exceptions (9) General Illegal Instruction Exception • Sources: ⎯ Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD ⎯ Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR •...
Page 257 Section 5 Exceptions (10) Slot Illegal Instruction Exception • Sources: ⎯ Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD ⎯ Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR ⎯...
Page 258 Section 5 Exceptions (11) General FPU Disable Exception • Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR.
Page 259 Section 5 Exceptions (12) Slot FPU Disable Exception • Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 • Transition address: VBR + H'0000 0100 • Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR.
Page 260 Section 5 Exceptions (13) User Breakpoint Trap • Source: Fulfilling of a break condition set in the user break controller • Transition address: VBR + H'0000 0100, or DBR • Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC.
Page 261 Section 5 Exceptions (14) FPU Exception • Source: Exception due to execution of a floating-point operation • Transition address: VBR + H'0000 0100 • Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR, and the contents of R15 are saved in SGR.
Page 262: Interrupts
Section 5 Exceptions 5.6.3 Interrupts (1) NMI • Source: NMI pin edge detection • Transition address: VBR + H'0000 0600 • Transition operations: The contents of PC and SR immediately after the instruction at which this interrupt was accepted are saved in SPC and SSR, and the contents of R15 are saved in SGR. Exception code H'1C0 is set in INTEVT.
Page 263 Section 5 Exceptions (2) IRL Interrupts • Source: The interrupt mask bit setting in SR is smaller than the IRL (3–0) level, and the BL bit in SR is 0 (accepted at instruction boundary). • Transition address: VBR + H'0000 0600 •...
Page 264 Section 5 Exceptions (3) Peripheral Module Interrupts • Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI, GPIO, DMAC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in SR is 0 (accepted at instruction boundary).
Page 265: Priority Order With Multiple Exceptions
Section 5 Exceptions 5.6.4 Priority Order with Multiple Exceptions With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order.
Page 266: Usage Notes
Section 5 Exceptions If the delay slot instruction has a second data transfer, two checks are performed in step b, as in 1 above. If the accepted exception (the highest-priority exception) is a delay slot instruction re- execution type exception, the branch instruction PR register write operation (PC → PR operation performed in BSR, BSRF, JSR) is inhibited.
Page 267: Restrictions
Section 5 Exceptions 4. An exception must not be generated in an RTE instruction delay slot, as the operation will be undefined in this case. Restrictions 1. Restrictions on first instruction of exception handling routine • Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR + H'400, or VBR + H'600.
Page 268 Section 5 Exceptions Rev.7.00 Oct. 10, 2008 Page 184 of 1074 REJ09B0366-0700...
Page 269: Section 6 Floating-Point Unit (Fpu)
Section 6 Floating-Point Unit (FPU) Section 6 Floating-Point Unit (FPU) Overview The floating-point unit (FPU) has the following features: • Conforms to IEEE754 standard • 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) • Two rounding modes: Round to Nearest and Round to Zero •...
Page 270: Figure 6.2 Format Of Double-Precision Floating-Point Number
Section 6 Floating-Point Unit (FPU) 52 51 Figure 6.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows: e = E + bias The range of unbiased exponent E is E – 1 to E + 1.
Page 271: Non-Numbers (Nan)
Section 6 Floating-Point Unit (FPU) Table 6.2 Floating-Point Ranges Type Single-Precision Double-Precision Signaling non-number H'7FFFFFFF to H'7FC00000 H'7FFFFFFF FFFFFFFF to H'7FF80000 00000000 Quiet non-number H'7FBFFFFF to H'7F800001 H'7FF7FFFF FFFFFFFF to H'7FF00000 00000001 Positive infinity H'7F800000 H'7FF00000 00000 Positive normalized H'7F7FFFFF to H'00800000 H'7FEFFFFF FFFFFFFF to number H'00100000 00000000...
Page 272: Denormalized Numbers
Section 6 Floating-Point Unit (FPU) 23 22 11111111 Nxxxxxxxxxxxxxxxxxxxxxx N = 1: sNaN N = 0: qNaN Figure 6.3 Single-Precision NaN Bit Pattern An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point value. •...
Page 273: Registers
Section 6 Floating-Point Unit (FPU) Registers 6.3.1 Floating-Point Registers Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating- point registers, referenced by specifying FR0–FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0– XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) FPR0_BANK0–FPR15_BANK0 FPR0_BANK1–FPR15_BANK1 2.
Page 274: Figure 6.4 Floating-Point Registers
Section 6 Floating-Point Unit (FPU) 7. Single-precision floating-point extended register matrix: XMTRX XMTRX comprises all 16 XF registers XMTRX = XF12 XF13 XF10 XF14 XF11 XF15 FPSCR.FR = 0 FPSCR.FR = 1 FPR0 _BANK0 XMTRX FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0...
Page 275: Floating-Point Status/Control Register (Fpscr)
Section 6 Floating-Point Unit (FPU) 6.3.2 Floating-Point Status/Control Register (FPSCR) Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001) 22 21 20 19 18 17 12 11 — FR SZ PR DN Cause Enable Flag Note: —: Reserved. These bits are always read as 0, and should only be written with 0. •...
Page 276: Floating-Point Communication Register (Fpul)
Section 6 Floating-Point Unit (FPU) • Flag: FPU exception flag field Invalid Division Overflow Underflow Inexact Error (E) Operation (V) by Zero (Z) Cause FPU exception Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 cause field Enable FPU exception None...
Page 277: Rounding
Section 6 Floating-Point Unit (FPU) Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC, FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB, or FMUL.
Page 278 Section 6 Floating-Point Unit (FPU) The FPSCR cause field contains bits corresponding to all of above sources E, V, Z, O, U, and I, and the FPSCR flag and enable fields contain bits corresponding to sources V, Z, O, U, and I, but not E.
Page 279: Graphics Support Functions
Section 6 Floating-Point Unit (FPU) ⎯ Overflow (O): When rounding mode = RZ, the maximum normalized number, with the same sign as the unrounded value, is generated. When rounding mode = RN, infinity with the same sign as the unrounded value is generated.
Page 280: Pair Single-Precision Data Transfer
Section 6 Floating-Point Unit (FPU) Since approximate-value computations are performed to enable high-speed computation, the inexact exception (I) bit in the cause field and flag field is always set to 1 when an FIPR instruction is executed. Therefore, if the corresponding bit is set in the enable field, enable exception handling will be executed.
Page 281: Usage Notes
Section 6 Floating-Point Unit (FPU) These instructions enable two single-precision (2 × 32-bit) data items to be transferred; that is, the transfer performance of these instructions is doubled. • FSCHG This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use and non-use of pair single-precision data transfer.
Page 282: Setting Of Overflow Flag By Fipr Or Ftrv Instruction
Section 6 Floating-Point Unit (FPU) a. According to IEEE754 standard Operation result: H'00800000 FPSCR: H'0004300C b. FPU Operation result: H'00800000 FPSCR: H'00041004 • Double-precision When FPSCR.RM = 00 (Round to Nearest) and FPSCR.PR = 1 (double-precision), and the FDIV instruction (H'001FFFFF FFFFFFFF / H'40000000 00000000) is executed. a.
Page 283: Sign Of Operation Result When Using Fipr Or Ftrv Instruction
Section 6 Floating-Point Unit (FPU) 6.7.3 Sign of Operation Result when Using FIPR or FTRV Instruction When two or more data items used in an operation by the FIPR or FTRV instruction are infinity, and all of the infinity items in the multiplication results have the same sign, the sign of the operation result may be incorrect.
Page 284: Notes On Fpu Double-Precision Operation Instructions (Sh7750 Only)
Section 6 Floating-Point Unit (FPU) Example: If the double-precision FSUB instruction (FSUB DR0, DR2) is executed with input data DR0 = H'C1F00000 80000000, DR2 = H'C4B250D2 0CC1FB74, and FPSCR = H'000C0001, the correct operation result is DR2 = H'C4B250D2 0CC1F973, and FPSCR.Flag.I and FPSCR.Cause.I should be set to 1.
Page 285 Section 6 Floating-Point Unit (FPU) This problem affects applications in science and engineering where extreme precision is required. It is limited to cases where double-precision floating-point instructions are used to handle denormalized numbers. The problem does not affect cases where double-precision floating-point instructions are used but denormalized numbers are treated as zero, or cases where only single- precision floating-point instructions are used.
Page 286 Section 6 Floating-Point Unit (FPU) Details Definitions: The data patterns that cause the problem are defined below. Item (A) to (D) in the tables correspond to the following data patterns. • Double-precision denormalized number (A) H'00000000_XXXXXXXX or H'80000000_XXXXXXXX (X: 0 or 1) However, H'XXXXXXXX != H'00000000 •...
Page 287: Table 6.3 Incorrect Operation Result
Section 6 Floating-Point Unit (FPU) Table 6.3 Incorrect Operation Result Input Expected Problem Type Instruction SH-4 Value FDIV +0/–0 (A) DENORM +0/–0 FDIV (A) DENORM +0/–0 +0/–0 FPU Error (A) DENORM (A) DENORM FDIV (A) DENORM +INF/–INF +INF/–INF FPU Error qNaN * FDIV (C) qNaN...
Page 288: Table 6.4 Fdiv Drm, Drn (Drn/Drm → Drn)
Section 6 Floating-Point Unit (FPU) Special cases involving double-precision FDIV, FADD, FSUB, and FMUL instructions are summarized below. : Shaded portion indicates normal operation. : Unshaded portion indicates incorrect operation result, and FPU output values are listed FDIV DRm, DRn (DRn/DRm → DRn) Table 6.4 Positive Negative...
Page 289: Table 6.5 Fadd Drm, Drn (Drn + Drm → Drn) Fsub Drm, Drn (Drn − Drm → Drn)
Section 6 Floating-Point Unit (FPU) FADD DRm, DRn (DRn + DRm → DRn) Table 6.5 FSUB DRm, DRn (DRn − DRm → DRn) Positive Negative −0 −INF NORM +INF DENORM DENORM DENORM qNaN qNaN sNaN −INF NORM +INF Error −0 −0 +INF Invalid...
Page 290 Section 6 Floating-Point Unit (FPU) Modifying Software Problem types (1), (2), and (3): Deal with problem types (1), (2), and (3) in table 6.3 using software based on the flowchart below. 1536 Adjust the source operands by multiplying them by 2 , then calculate them as normalized numbers.
Page 291: Table 6.7 Trap Routine Processing
Section 6 Floating-Point Unit (FPU) Modifying a TRAP Routine: For problem types (4), (5), and (6) in table 6.3, add code to the TRAP routine to check the instruction and input data as indicated in table 6.7 and to write the contents of qNaN to the destination register.
Page 292 Section 6 Floating-Point Unit (FPU) Rev.7.00 Oct. 10, 2008 Page 208 of 1074 REJ09B0366-0700...
Page 293: Section 7 Instruction Set
Section 7 Instruction Set Section 7 Instruction Set Execution Environment PC: At the start of instruction execution, PC indicates the address of the instruction itself. Data sizes and data types: The SH-4's instruction set is implemented with 16-bit fixed-length instructions. The SH-4 can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64- bit) data sizes for memory access.
Page 294 Section 7 Instruction Set ADD #1, R0 ; T bit is not changed by ADD operation CMP/EQ R1, R0 ; If R0 = R1, T bit is set to 1 BT TARGET ; Branches to TARGET if T bit = 1 (R0 = R1) In an RTE delay slot, status register (SR) bits are referenced as follows.
Page 295: Addressing Modes
Section 7 Instruction Set Addressing Modes Addressing modes and effective address calculation methods are shown in table 7.1. When a location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (MMUCR.SV = 0), the least significant bit of PTEH is also referenced as the access ASID.
Page 296 Section 7 Instruction Set Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @(disp:4, Rn) Effective address is register Rn contents with Byte: Rn + disp → EA indirect with 4-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 (word), Word: Rn + or 4 (longword), according to the operand size.
Page 297 Section 7 Instruction Set Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative @(disp:8, PC) Effective address is PC+4 with 8-bit displacement Word: PC + 4 + disp × 2 → with disp added. After disp is zero-extended, it is displacement multiplied by 2 (word), or 4 (longword), according to the operand size.
Page 298 Section 7 Instruction Set Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC-relative disp:12 Effective address is PC+4 with 12-bit displacement PC + 4 + disp × 2 → Branch- disp added after being sign-extended and multiplied by 2. Target PC + 4 + disp ×...
Page 299: Instruction Set
Section 7 Instruction Set Instruction Set Table 7.2 shows the notation used in the following SH instruction list. Table 7.2 Notation Used in Instruction List Item Format Description Instruction OP.Sz SRC, DEST Operation code mnemonic Size SRC: Source DEST: Source and/or destination operand →, ←: Summary of Transfer direction...
Page 300: Table 7.3 Fixed-Point Transfer Instructions
Section 7 Instruction Set Table 7.3 Fixed-Point Transfer Instructions Instruction Operation Instruction Code Privileged T Bit imm → sign extension → Rn #imm,Rn 1110nnnniiiiiiii — — (disp × 2 + PC + 4) → sign MOV.W @(disp,PC),Rn 1001nnnndddddddd — — extension →...
Page 301 Section 7 Instruction Set Instruction Operation Instruction Code Privileged T Bit (R0 + Rm) → Rn MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110 — — R0 → (disp + GBR) MOV.B R0,@(disp,GBR) 11000000dddddddd — — R0 → (disp × 2 + GBR) MOV.W R0,@(disp,GBR) 11000001dddddddd —...
Page 302: Table 7.4 Arithmetic Operation Instructions
Section 7 Instruction Set Table 7.4 Arithmetic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn + Rm → Rn Rm,Rn 0011nnnnmmmm1100 — — Rn + imm → Rn #imm,Rn 0111nnnniiiiiiii — — Rn + Rm + T → Rn, carry → T ADDC Rm,Rn 0011nnnnmmmm1110 —...
Page 303 Section 7 Instruction Set Instruction Operation Instruction Code Privileged T Bit EXTS.B Rm,Rn Rm sign-extended from 0110nnnnmmmm1110 — — byte → Rn EXTS.W Rm,Rn Rm sign-extended from 0110nnnnmmmm1111 — — word → Rn EXTU.B Rm,Rn Rm zero-extended from 0110nnnnmmmm1100 — —...
Page 304: Table 7.5 Logic Operation Instructions
Section 7 Instruction Set Table 7.5 Logic Operation Instructions Instruction Operation Instruction Code Privileged T Bit Rn & Rm → Rn Rm,Rn 0010nnnnmmmm1001 — — R0 & imm → R0 #imm,R0 11001001iiiiiiii — — AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + 11001101iiiiiiii —...
Page 305: Table 7.6 Shift Instructions
Section 7 Instruction Set Table 7.6 Shift Instructions Instruction Operation Instruction Code Privileged T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 — LSB → Rn → T ROTR 0100nnnn00000101 — T ← Rn ← T ROTCL 0100nnnn00100100 — T → Rn → T ROTCR 0100nnnn00100101 —...
Page 306: Table 7.7 Branch Instructions
Section 7 Instruction Set Table 7.7 Branch Instructions Instruction Operation Instruction Code Privileged T Bit When T = 0, disp × 2 + PC + label 10001011dddddddd — — 4 → PC When T = 1, nop BF/S label Delayed branch; when T = 0, 10001111dddddddd —...
Page 307: Table 7.8 System Control Instructions
Section 7 Instruction Set Table 7.8 System Control Instructions Instruction Operation Instruction Code Privileged T Bit 0 → MACH, MACL CLRMAC 0000000000101000 — — 0 → S CLRS 0000000001001000 — — 0 → T CLRT 0000000000001000 — Rm → SR Rm,SR 0100mmmm00001110 Privileged Rm →...
Page 308 Section 7 Instruction Set Instruction Operation Instruction Code Privileged T Bit Delayed branch, SSR/SPC → 0000000000101011 Privileged — SR/PC 1 → S SETS 0000000001011000 — — 1 → T SETT 0000000000011000 — SLEEP Sleep or standby 0000000000011011 Privileged — SR → Rn SR,Rn 0000nnnn00000010 Privileged —...
Page 309: Table 7.9 Floating-Point Single-Precision Instructions
Section 7 Instruction Set Table 7.9 Floating-Point Single-Precision Instructions Instruction Operation Instruction Code Privileged T Bit H'00000000 → FRn FLDI0 1111nnnn10001101 — — H'3F800000 → FRn FLDI1 1111nnnn10011101 — — FRm → FRn FMOV FRm,FRn 1111nnnnmmmm1100 — — (Rm) → FRn FMOV.S @Rm,FRn 1111nnnnmmmm1000 —...
Page 310: Table 7.10 Floating-Point Double-Precision Instructions
Section 7 Instruction Set Table 7.10 Floating-Point Double-Precision Instructions Instruction Operation Instruction Code Privileged T Bit FABS DRn & H'7FFF FFFF FFFF FFFF 1111nnn001011101 — — → DRn DRn + DRm → DRn FADD DRm,DRn 1111nnn0mmm00000 — — When DRn = DRm, 1 → T FCMP/EQ DRm,DRn 1111nnn0mmm00100 —...
Page 311: Usage Notes
Section 7 Instruction Set Table 7.12 Floating-Point Graphics Acceleration Instructions Instruction Operation Instruction Code Privileged T Bit DRm → XDn FMOV DRm,XDn 1111nnn1mmm01100 — — XDm → DRn FMOV XDm,DRn 1111nnn0mmm11100 — — XDm → XDn FMOV XDm,XDn 1111nnn1mmm11100 — —...
Page 312 Section 7 Instruction Set b. A TRAPA instruction or undefined instruction code H'FFFD in a cache-enabled area is executed. c. The four words of data following the TRAPA instruction or undefined instruction code H'FFFD mentioned in b. contain code that can be interpreted as an instruction to access (read or write) an address (H'F0000000 to H'F7FFFFFF) mapped to the internal cache or internal TLB.
Page 313 Section 7 Instruction Set executed in 4xIck. The maximum number of instructions that can be executed in 2xIck or 4xIck is four or eight, respectively. Therefore, the affected codes are those occurring in “the four words (or eight words) of data following the instruction.” Workarounds: To prevent the problem, use either of workarounds a.
Page 314 Section 7 Instruction Set Rev.7.00 Oct. 10, 2008 Page 230 of 1074 REJ09B0366-0700...
Page 315: Section 8 Pipelining
Section 8 Pipelining Section 8 Pipelining This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. Definitions in this section may not be applicable to SH-4 Series products other than this LSI.
Page 316: Figure 8.1 Basic Pipelines
Section 8 Pipelining 1. General Pipeline • Instruction fetch • Instruction • Operation • Non-memory • Write-back decode data access • Issue • Register read • Destination address calculation for PC-relative branch 2. General Load/Store Pipeline • Instruction fetch • Instruction •...
Page 317: Figure 8.2 Instruction Execution Patterns
Section 8 Pipelining 1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG 2.
Page 318 Section 8 Pipelining 10. OCBI: 1 issue cycle 11. OCBP, OCBWB: 1 issue cycle 12. MOVCA.L: 1 issue cycle 13. TRAPA: 7 issue cycles 14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle 15. LDC to GBR: 3 issue cycles 16. LDC to SR: 4 issue cycles 17.
Page 319 Section 8 Pipelining 19. LDC.L to SR: 4 issue cycles 20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 21. STC.L from SGR: 3 issue cycles 22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles 23. STC.L from SGR: 3 issue cycles 24. LDS to PR, JSR, BSRF: 2 issue cycles 25.
Page 320 Section 8 Pipelining 31. STS.L from MACH/L: 1 issue cycle 32. LDS to FPSCR: 1 issue cycle 33. LDS.L to FPSCR: 1 issue cycle 34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W (CPU) (FPU) 35. MAC.W, MAC.L: 2 issue cycles (CPU) (FPU) 36.
Page 321 Section 8 Pipelining 40. Double-precision FCMP: 2 issue cycles FCMP/EQ,FCMP/GT 41. Double-precision FDIV/SQRT: 1 issue cycle FDIV, FSQRT 42. FIPR: 1 issue cycle 43. FTRV: 1 issue cycle : Cannot overlap a stage of the same kind, except when two instructions are Notes: executed in parallel.
Page 322: Parallel-Executability
Section 8 Pipelining Parallel-Executability Instructions are categorized into six groups according to the internal function blocks used, as shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 8.1 Instruction Groups 1.
Page 323 Section 8 Pipelining 3. BR Group disp disp disp BF/S disp disp BT/S disp 4. LS Group FABS FMOV.S @Rm+,FRn MOV.L R0,@(disp,GBR) FABS FMOV.S FRm,@(R0,Rn) MOV.L Rm,@(disp,Rn) FLDI0 FMOV.S FRm,@-Rn MOV.L Rm,@(R0,Rn) FLDI1 FMOV.S FRm,@Rn MOV.L Rm,@-Rn FLDS FRm,FPUL FNEG MOV.L Rm,@Rn FMOV...
Page 324 Section 8 Pipelining 5. FE Group FADD DRm,DRn FIPR FVm,FVn FSQRT FADD FRm,FRn FLOAT FPUL,DRn FSQRT FCMP/EQ FRm,FRn FLOAT FPUL,FRn FSUB DRm,DRn FCMP/GT FRm,FRn FMAC FR0,FRm,FRn FSUB FRm,FRn FCNVDS DRm,FPUL FMUL DRm,DRn FTRC DRm,FPUL FCNVSD FPUL,DRn FMUL FRm,FRn FTRC FRm,FPUL FDIV DRm,DRn FRCHG...
Page 325 Section 8 Pipelining 6. CO Group AND.B #imm,@(R0,GBR) LDS Rm,FPSCR SR,Rn BRAF Rm,MACH SSR,Rn BSRF Rm,MACL VBR,Rn CLRMAC Rm,PR STC.L DBR,@-Rn CLRS LDS.L @Rm+,FPSCR STC.L GBR,@-Rn DMULS.L Rm,Rn LDS.L @Rm+,FPUL STC.L Rp_BANK,@-Rn DMULU.L Rm,Rn LDS.L @Rm+,MACH STC.L SGR,@-Rn FCMP/EQ DRm,DRn LDS.L @Rm+,MACL STC.L...
Page 326: Execution Cycles And Pipeline Stalling
Section 8 Pipelining Table 8.2 Parallel-Executability 2nd Instruction Instruction Legend: O: Can be executed in parallel X: Cannot be executed in parallel Execution Cycles and Pipeline Stalling There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware unit operates on one of these clocks, as follows: •...
Page 327 Section 8 Pipelining The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 8.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction;...
Page 328 Section 8 Pipelining operation, never occurs. For example, when FADD follows FDIV with no dependency between FP registers, FADD is not stalled even if both instructions update the cause field of FPSCR. Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS.
Page 329: Figure 8.3 Examples Of Pipelined Execution
Section 8 Pipelining (a) Serial execution: non-parallel-executable instructions 1 issue cycle SHAD R0,R1 EX-group SHAD and EX-group ADD R2,R3 cannot be executed in parallel. Therefore, next SHAD is issued first, and the following 1 stall cycle ADD is recombined with the next instruction.
Page 330 Section 8 Pipelining (e) Flow dependency Zero-cycle latency The following instruction, ADD, is not R0,R1 stalled when executed after an instruction R2,R1 with zero-cycle latency, even if there is dependency. 1-cycle latency ADD and MOV.L are not executed in R2,R1 parallel, since MOV.L references the result MOV.L @R1,R1 of ADD as its destination address.
Page 331 Section 8 Pipelining (e) Flow dependency (cont) Effectively 1-cycle latency for consecutive LDS/FLOAT instructions R0,FPUL FLOAT FPUL,FR0 R1,FPUL FLOAT FPUL,R1 Effectively 1-cycle latency for consecutive FTRC FR0,FPUL FTRC/STS instructions FPUL,R0 FTRC FR1,FPUL FPUL,R1 (f) Output dependency 11-cycle latency FSQRT FR4 FMOV FR0,FR4 10 stall cycles = latency (11) - 1...
Page 332 Section 8 Pipelining (h) Resource conflict ..........Latency 1 cycle/issue FDIV FR6,FR7 F1 stage locked for 1 cycle FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13 1 stall cycle (F1 stage resource conflict) FIPR FV8,FV0 FADD FR15,FR4 1 stall cycle LDS.L @R15+,PR GBR,R2 3 stall cycles FADD DR0,DR2...
Page 333: Table 8.3 Execution Cycles
Section 8 Pipelining Table 8.3 Execution Cycles Instruc- Execu- Lock Functional tion Issue tion Category Instruction Group Rate Latency Pattern Stage Start Cycles Data transfer EXTS.B Rm,Rn — — — instructions EXTS.W Rm,Rn — — — EXTU.B Rm,Rn — — —...
Page 334 Section 8 Pipelining Instruc- Execu- Lock tion tion Functional Issue Category Instruction Group Rate Latency Pattern Stage Start Cycles Data transfer MOV.W R0,@(disp,Rn) — — — instructions MOV.L Rm,@(disp,Rn) — — — MOV.B Rm,@(R0,Rn) — — — MOV.W Rm,@(R0,Rn) — —...
Page 335 Section 8 Pipelining Instruc- Execu- Lock tion tion Functional Issue Category Instruction Group Rate Latency Pattern Stage Start Cycles Fixed-point DIV0U — — — arithmetic DIV1 Rm,Rn — — — instructions DMULS.L Rm,Rn DMULU.L Rm,Rn — — — MAC.L @Rm+,@Rn+ 2/2/4/4 MAC.W @Rm+,@Rn+...
Page 336 Section 8 Pipelining Instruc- Execu- Lock tion tion Functional Issue Category Instruction Group Rate Latency Pattern Stage Start Cycles Shift ROTL — — — instructions ROTR — — — ROTCL — — — ROTCR — — — SHAD Rm,Rn — —...
Page 337 Section 8 Pipelining Instruc- Execu- Lock tion tion Functional Issue Category Instruction Group Rate Latency Pattern Stage Start Cycles System — — — control CLRMAC instructions CLRS — — — CLRT — — — SETS — — — SETT — —...
Page 338 Section 8 Pipelining Instruc- Execu- Lock tion tion Functional Issue Category Instruction Group Rate Latency Pattern Stage Start Cycles System GBR,Rn — — — control Rp_BANK,Rn — — — instructions SR,Rn — — — SSR,Rn — — — SPC,Rn — —...
Page 339 Section 8 Pipelining Instruc- Execu- Lock tion tion Functional Issue Category Instruction Group Rate Latency Pattern Stage Start Cycles Single- FABS — — — precision FADD FRm,FRn — — — floating-point FCMP/EQ FRm,FRn — — — instructions FCMP/GT FRm,FRn — —...
Page 340 Section 8 Pipelining Instruc- Execu- Lock tion tion Functional Issue Category Instruction Group Rate Latency Pattern Stage Start Cycles Double- FNEG — — — precision FSQRT (23, 24)/ floating-point instructions FSUB DRm,DRn (7, 8)/9 FTRC DRm,FPUL FPU system Rm,FPUL — —...
Page 341 Section 8 Pipelining 4. Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement, and 1 for a zero displacement. 5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR [n+1], L2 that for FR [n], and L3 that for FPSCR. 6.
Page 342: Usage Notes
Section 8 Pipelining Usage Notes The following are additional notes on pipeline operation and the method of calculating the number of clock cycles. The number of states (I clock cycles) required for stages where an external bus access, etc., occurs may include an increased number of cycles, in addition to the number of memory access cycles set by the bus state controller (BSC), etc.
Page 343: Section 9 Power-Down Modes
Section 9 Power-Down Modes Section 9 Power-Down Modes Overview In the power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. 9.1.1 Types of Power-Down Modes The following power-down modes and functions are provided: •...
Page 344: Table 9.1 Status Of Cpu And Peripheral Modules In Power-Down Modes
Section 9 Power-Down Modes Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes Status Power- On-chip Down Entering On-Chip Peripheral External Exiting Mode Conditions CPG Memory Modules Pins Memory Method Refreshing • Interrupt Sleep SLEEP Operating Halted Held Operating Held •...
Page 345: Register Configuration
Section 9 Power-Down Modes 9.1.2 Register Configuration Table 9.2 shows the registers used for power-down mode control. Table 9.2 Power-Down Mode Registers Area 7 Access Name Abbreviation Initial Value P4 Address Address Size Standby control STBCR H'00 H'FFC00004 H'1FC00004 register Standby control STBCR2 H'00...
Page 346: Register Descriptions
Section 9 Power-Down Modes Register Descriptions 9.2.1 Standby Control Register (STBCR) The standby control register (STBCR) is an 8-bit readable/writable register that specifies the power-down mode status. It is initialized to H'00 by a power-on reset via the RESET pin or due to watchdog timer overflow.
Page 347 Section 9 Power-Down Modes Bit 4—Module Stop 4 (MSTP4): Specifies stopping of the clock supply to the DMAC among the on-chip peripheral modules. The clock supply to the DMAC is stopped when the MSTP4 bit is set to 1. When DMA transfer is used, stop the transfer before setting the MSTP4 bit to 1. When DMA transfer is performed after clearing the MSTP4 bit to 0, DMAC settings must be made again.
Page 348: Peripheral Module Pin High Impedance Control
Section 9 Power-Down Modes Bit 0—Module Stop 0 (MSTP0): Specifies stopping of the clock supply to serial communication interface channel 1 (SCI) among the on-chip peripheral modules. The clock supply to the SCI is stopped when the MSTP0 bit is set to 1. Bit 0: MSTP0 Description SCI operates...
Page 349: Peripheral Module Pin Pull-Up Control
Section 9 Power-Down Modes 9.2.3 Peripheral Module Pin Pull-Up Control When bit 5 in the standby control register (STBCR) is cleared to 0, peripheral module related pins are pulled up when in the input or high-impedance state. • Relevant Pins SCI related pins MD0/SCK MD1/TXD2...
Page 350 Section 9 Power-Down Modes Bit 7—Deep Sleep (DSLP): Specifies a transition to deep sleep mode Bit 7: DSLP Description Transition to sleep mode or standby mode on execution of SLEEP instruction, according to setting of STBY bit in STBCR register (Initial value) Transition to deep sleep mode on execution of SLEEP instruction* Note: When the STBY bit in the STBCR register is 0...
Page 351: Clock-Stop Register 00 (Clkstp00) (Sh7750R Only)
Section 9 Power-Down Modes 9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only) Clock-stop register 00 (CLKSTP00) controls the operation clock for peripheral modules. To resume supply of the clock signal, write a 1 to the corresponding bit in the CLKSTPCLR00 register. Writing a 0 to the CLKSTP00 register does not affect the register's value. The CLKSTP00 register is a 32-bit register that can be read from or written to.
Page 352: Clock-Stop Clear Register 00 (Clkstpclr00) (Sh7750R Only)
Section 9 Power-Down Modes 9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only) The clock-stop clear register 00 (CLKSTPCLR00) is a 32-bit write-only register that clears the corresponding bits of the CLKSTP00 register. Bit: Initial value: R/W: Bit: Initial value: R/W: Bits 31 to 0⎯Clock-Stop Clear: Specify whether or not to clear the corresponding bit of the clock-stop setting.
Page 353: Exit From Sleep Mode
Section 9 Power-Down Modes 9.3.2 Exit from Sleep Mode Sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset. In sleep mode, interrupts are accepted even if the BL bit in the SR register is 1. If necessary, SPC and SSR should be saved to the stack before executing the SLEEP instruction.
Page 354: Standby Mode
Section 9 Power-Down Modes Standby Mode 9.5.1 Transition to Standby Mode If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches from the program execution state to standby mode. In standby mode, the on-chip peripheral modules halt as well as the CPU.
Page 355: Exit From Standby Mode
Section 9 Power-Down Modes 9.5.2 Exit from Standby Mode Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a reset via the RESET pin. Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI, IRL* , RTC, or GPIO* interrupt is detected, the WDT starts counting.
Page 356: Module Standby Function
Section 9 Power-Down Modes Module Standby Function 9.6.1 Transition to Module Standby Function Setting the MSTP6–MSTP0, CSTP1, and CSTP0 bits in the standby control register to 1 enables the clock supply to the corresponding on-chip peripheral modules to be halted. Use of this function allows power consumption in sleep mode to be further reduced.
Page 357: Exit From Module Standby Function
Section 9 Power-Down Modes Description CSTP1 * Peripheral clock is supplied to TMU channels 3 and 4 Peripheral clock supplied to TMU channels 3 and 4 is stopped CSTP0 * INTC detects interrupts on TMU channels 3 and 4 INTC does not detect interrupts on TMU channels 3 and 4 MSTP6 * SQ operates Clock supplied to SQ is stopped...
Page 358: Hardware Standby Mode (Sh7750S, Sh7750R Only)
Section 9 Power-Down Modes Hardware Standby Mode (SH7750S, SH7750R Only) 9.7.1 Transition to Hardware Standby Mode Setting the CA pin level low effects a transition to hardware standby mode. In this mode, all modules other than the RTC stop, as in the standby mode selected using the SLEEP command. Hardware standby mode differs from standby mode as follows: 1.
Page 359: Usage Notes
Section 9 Power-Down Modes 9.7.3 Usage Notes 1. The CA pin level must be kept high when the RTC power supply is started (figure 9.15). 2. On the SH7750R, power must be supplied to the other power supply pins (V −...
Page 360: In Reset
Section 9 Power-Down Modes 9.8.1 In Reset Power-On Reset CKIO PLL stabilization time RESET SCK2 Normal Reset Normal STATUS 0–30 Bcyc 0–5 Bcyc Figure 9.1 STATUS Output in Power-On Reset Manual Reset CKIO Must be asserted for or longer RESET * RESW SCK2 Normal...
Page 361: In Exit From Standby Mode
Section 9 Power-Down Modes 9.8.2 In Exit from Standby Mode Standby → Interrupt Oscillation stops Interrupt request WDT overflow CKIO WDT count Normal Standby Normal STATUS Figure 9.3 STATUS Output in Standby → Interrupt Sequence Standby → Power-On Reset Oscillation stops Reset CKIO RESET...
Page 362: Figure 9.5 Status Output In Standby → Manual Reset Sequence
Section 9 Power-Down Modes Standby → Manual Reset Oscillation stops Reset CKIO RESET SCK2 Normal Standby Reset Normal STATUS 0–30 Bcyc 0–10 Bcyc Notes: 1. When standby mode is exited by means of a manual reset, a WDT count is not performed.
Page 363: In Exit From Sleep Mode
Section 9 Power-Down Modes 9.8.3 In Exit from Sleep Mode Sleep → Interrupt Interrupt request CKIO STATUS Normal Sleep Normal Figure 9.6 STATUS Output in Sleep → Interrupt Sequence Sleep → Power-On Reset Reset CKIO RESET SCK2 Normal Sleep Reset Normal STATUS 0–30 Bcyc...
Page 364: Figure 9.8 Status Output In Sleep → Manual Reset Sequence
Section 9 Power-Down Modes Sleep → Manual Reset Reset CKIO RESET* SCK2 Normal Sleep Reset Normal STATUS 0–30 Bcyc 0–30 Bcyc Note: * Hold RESET low until STATUS = reset. Figure 9.8 STATUS Output in Sleep → Manual Reset Sequence Rev.7.00 Oct.
Page 365: In Exit From Deep Sleep Mode
Section 9 Power-Down Modes 9.8.4 In Exit from Deep Sleep Mode Deep Sleep → Interrupt Interrupt request CKIO Sleep STATUS Normal Normal Figure 9.9 STATUS Output in Deep Sleep → Interrupt Sequence Deep Sleep → Power-On Reset Reset CKIO RESET SCK2 Normal Sleep...
Page 366: Figure 9.11 Status Output In Deep Sleep → Manual Reset Sequence
Section 9 Power-Down Modes Deep Sleep → Manual Reset Reset CKIO RESET * SCK2 Sleep Normal Reset Normal STATUS 0–30 Bcyc 0–30 Bcyc Note: * Hold RESET low until STATUS = reset. Figure 9.11 STATUS Output in Deep Sleep → Manual Reset Sequence Rev.7.00 Oct.
Page 367: Hardware Standby Mode Timing (Sh7750S, Sh7750R Only)
Section 9 Power-Down Modes 9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only) Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode. The CA pin level must be kept low while in hardware standby mode. After setting the RESET pin level low, the clock starts when the CA pin level is switched to high.
Page 368: Figure 9.13 Hardware Standby Mode Timing (When Ca = Low In Wdt Operation)
Section 9 Power-Down Modes Interrupt request WDT overflow CKIO RESET (High) SCK2 (High) Standby * Standby Normal STATUS 0–10 Bcyc WDT count Note: * High impedance when STBCR2. STHZ = 0 Figure 9.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation) Rev.7.00 Oct.
Page 369: Figure 9.14 Timing When Power Other Than Vdd-Rtc Is Off
Section 9 Power-Down Modes RESET SCK2 Min 0s Min 0s Max 50 μs Note: * V DD-CPG DD-PLL1 DD-PLL2 Figure 9.14 Timing When Power Other than VDD-RTC Is Off DD-RTC Power-on oscillation setting time Min 0s RESET SCK2 Note: * V DD-PLL1/2 DD-CPG Figure 9.15 Timing When VDD-RTC Power Is Off →...
Page 370: Usage Notes
Section 9 Power-Down Modes Usage Notes 9.9.1 Note on Current Consumption After a power-on reset, the current consumption may exceed the maximum value for sleep mode or standby mode during the period until one or more of the arithmetic operation or floating-point operation instructions listed below is executed.
Page 371: Section 10 Clock Oscillation Circuits
Section 10 Clock Oscillation Circuits Section 10 Clock Oscillation Circuits 10.1 Overview The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer (WDT). The CPG generates the clocks supplied inside the processor and performs power-down mode control.
Page 372 Section 10 Clock Oscillation Circuits The WDT has the following features • Can be used to secure clock stabilization time Used when exiting standby mode or a temporary standby state when the clock frequency is changed. • Can be switched between watchdog timer mode and interval timer mode •...
Page 373: Overview Of Cpg
Section 10 Clock Oscillation Circuits 10.2 Overview of CPG 10.2.1 Block Diagram of CPG Figure 10.1 (1) shows a block diagram of the CPG in the SH7750 and SH7750S, and figure 10.1 (2) a block diagram of the CPG in the SH7750R. Oscillator circuit Frequency divider 2...
Page 374: Figure 10.1 (2) Block Diagram Of Cpg (Sh7750R)
Section 10 Clock Oscillation Circuits Oscillator circuit Frequency divider 2 ×1 PLL circuit 1 ×1/2 ×6 ×1/3 ×12 CPU clock (Ick) ×1/4 cycle Icyc ×1/6 ×1/8 Crystal oscillation XTAL Peripheral module circuit clock (Pck) cycle Pcyc EXTAL Bus clock (Bck) cycle Bcyc PLL circuit 2 ×1...
Page 375 Section 10 Clock Oscillation Circuits The function of each of the CPG blocks is described below. PLL Circuit 1: PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL pin or crystal oscillation circuit by 6 with the SH7750 and SH7750S, and by 6 or 12 with the SH7750R.
Page 376: Cpg Pin Configuration
Section 10 Clock Oscillation Circuits 10.2.2 CPG Pin Configuration Table 10.1 shows the CPG pins and their functions. Table 10.1 CPG Pins Pin Name Abbreviation Function Mode control pins Input Set clock operating mode Crystal I/O pins XTAL Output Connects crystal resonator (clock input pins) EXTAL Input...
Page 377: Clock Operating Modes
Section 10 Clock Oscillation Circuits 10.3 Clock Operating Modes Tables 10.3 (1) and 10.3 (2) show the clock operating modes corresponding to various combinations of mode control pin (MD2–MD0) settings (initial settings such as the frequency division ratio). Table 10.4 shows FRQCR settings and internal clock frequencies. Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S) External Frequency...
Page 378: Table 10.4 Frqcr Settings And Internal Clock Frequencies
Section 10 Clock Oscillation Circuits Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (f ) and CKIO clock output (f ) in section 22.3.1, Clock and Control Signal Timing.
Page 379: Cpg Register Description
Section 10 Clock Oscillation Circuits 10.4 CPG Register Description 10.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU clock, bus clock, and peripheral module clock frequency division ratios.
Page 380 Section 10 Clock Oscillation Circuits Bit 10—PLL Circuit 1 Enable (PLL1EN): Specifies whether PLL circuit 1 is on or off. Bit 10: PLL1EN Description PLL circuit 1 is not used PLL circuit 1 is used (Initial value) Bit 9—PLL Circuit 2 Enable (PLL2EN): Specifies whether PLL circuit 2 is on or off. Bit 9: PLL2EN Description PLL circuit 2 is not used...
Page 381 Section 10 Clock Oscillation Circuits Bits 5 to 3—Bus Clock Frequency Division Ratio (BFC): These bits specify the bus clock frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1 output frequency. Bit 5: BFC2 Bit 4: BFC1 Bit 3: BFC0 Description...
Page 382: Changing The Frequency
Section 10 Clock Oscillation Circuits 10.5 Changing the Frequency There are two methods of changing the internal clock frequency: by changing stopping and starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases, control is performed by software by means of the frequency control register.
Page 383: Changing Bus Clock Division Ratio (When Pll Circuit 2 Is On)
Section 10 Clock Oscillation Circuits 10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On) If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2 oscillation stabilization time is required. 1.
Page 384: Overview Of Watchdog Timer
Section 10 Clock Oscillation Circuits 10.7 Overview of Watchdog Timer 10.7.1 Block Diagram Figure 10.2 shows a block diagram of the WDT. Standby Standby Standby mode release control Frequency divider 2 ×1 clock Internal reset Frequency divider Reset request control Clock selection Clock selector Interrupt...
Page 385: Register Configuration
Section 10 Clock Oscillation Circuits 10.7.2 Register Configuration The WDT has the two registers summarized in table 10.5. These registers control clock selection and timer mode switching. Table 10.5 WDT Registers Initial Area 7 Name Abbreviation Value P4 Address Address Access Size Watchdog timer WTCNT...
Page 386: Watchdog Timer Control/Status Register (Wtcsr)
Section 10 Clock Oscillation Circuits 10.8.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register containing bits for selecting the count clock and timer mode, and overflow flags. WTCSR is initialized to H'00 only by a power-on reset via the RESET pin. It retains its value in an internal reset due to WDT overflow.
Page 387 Section 10 Clock Oscillation Circuits Bit 5—Reset Select (RSTS): Specifies the kind of reset to be performed when WTCNT overflows in watchdog timer mode. This setting is ignored in interval timer mode. Bit 5: RSTS Description Power-on reset (Initial value) Manual reset Bit 4—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in watchdog timer mode.
Page 388 Section 10 Clock Oscillation Circuits Bits 2 to 0—Clock Select 2 to 0 (CKS2–CKS0): These bits select the clock used for the WTCNT count from eight clocks obtained by dividing the frequency divider 2 input clock*. The overflow periods shown in the following table are for use of a 33 MHz input clock, with frequency divider 1 off, and PLL circuit 1 on (×6).
Page 389: Notes On Register Access
Section 10 Clock Oscillation Circuits 10.8.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) differ from other registers in being more difficult to write to. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written to with a word transfer instruction.
Page 390: Frequency Changing Procedure
Section 10 Clock Oscillation Circuits overflows is at least as long as the clock oscillation stabilization time. For details of the clock oscillation stabilization time, see section 22.3.1, Clock and Control Signal Timing. 3. Make a transition to standby mode, and stop the clock, by executing a SLEEP instruction. 4.
Page 391: Using Interval Timer Mode
Section 10 Clock Oscillation Circuits 4. When the counter overflows, the WDT sets the WOVF flag in the WTCSR register to 1, and generates a reset of the type specified by the RSTS bit. The counter then continues counting. 10.9.4 Using Interval Timer Mode When the WDT is operating in interval timer mode, an interval timer interrupt is generated each time the counter overflows.
Page 392: Figure 10.5 Points For Attention When Using Pll Oscillator Circuit
Section 10 Clock Oscillation Circuits When Using a PLL Oscillator Circuit: Separate VDD-CPG and VSS-CPG from the other VDD and VSS lines at the board power supply source, and insert resistors RCB and RB and bypass capacitors CPB and CB close to the pins as noise filters. RCB1 VDD-PLL1 CPB1...
Page 393: Usage Notes
Section 10 Clock Oscillation Circuits 10.11 Usage Notes 10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7750 and SH7750S) Under certain conditions the watchdog timer (WDT) may trigger an invalid manual reset. Conditions Under which Problem Occurs: The internal WDT triggers an invalid manual reset when all of the following four conditions are satisfied.
Page 394 Section 10 Clock Oscillation Circuits Rev.7.00 Oct. 10, 2008 Page 310 of 1074 REJ09B0366-0700...
Page 395: Section 11 Realtime Clock (Rtc)
Section 11 Realtime Clock (RTC) Section 11 Realtime Clock (RTC) 11.1 Overview This LSI includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillation circuit for use by the RTC. 11.1.1 Features The RTC has the following features. •...
Page 396: Block Diagram
Section 11 Realtime Clock (RTC) 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the RTC. RTCCLK RESET, STBY, etc 16.384 kHz RTC crystal RTC operation 32.768 kHz oscillation Prescaler control unit circuit 128 Hz RCR1 RCR2 Counter unit RCR3 Interrupt R64CNT...
Page 397: Pin Configuration
Section 11 Realtime Clock (RTC) 11.1.3 Pin Configuration Table 11.1 shows the RTC pins. Table 11.1 RTC Pins Pin Name Abbreviation I/O Function RTC oscillation circuit crystal pin EXTAL2 Input Connects crystal to RTC oscillation circuit RTC oscillation circuit crystal pin XTAL2 Output Connects crystal to RTC oscillation circuit Clock input/clock output TCLK...
Page 398 Section 11 Realtime Clock (RTC) Initialization Abbrevia- Power-On Manual Standby Initial Area 7 Access Name tion Reset Reset Mode Value P4 Address Address Size Month RMONCNT R/W Counts Counts Counts Undefined H'FFC80018 H'1FC80018 8 counter Year RYRCNT Counts Counts Counts Undefined H'FFC8001C H'1FC8001C 16 counter...
Page 399: Register Descriptions
Section 11 Realtime Clock (RTC) 11.2 Register Descriptions 11.2.1 64 Hz Counter (R64CNT) R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC frequency divider. If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7 (CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the carry and the 64 Hz counter read.
Page 400: Second Counter (Rseccnt)
Section 11 Realtime Clock (RTC) 11.2.2 Second Counter (RSECCNT) RSECCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded second value in the RTC. It counts on the carry (transition of the R64CNT.1Hz bit from 0 to 1) generated once per second by the 64 Hz counter.
Page 401: Hour Counter (Rhrcnt)
Section 11 Realtime Clock (RTC) 11.2.4 Hour Counter (RHRCNT) RHRCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded hour value in the RTC. It counts on the carry generated once per hour by the minute counter.
Page 402: Day Counter (Rdaycnt)
Section 11 Realtime Clock (RTC) Day-of-week code Day of week 11.2.6 Day Counter (RDAYCNT) RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour counter.
Page 403: Year Counter (Ryrcnt)
Section 11 Realtime Clock (RTC) Bits 7 to 5 are always read as 0. A write to these bits is invalid, but the write value should always be 0. Bit: — — — 10-month 1-month units unit Initial value: Undefined Undefined Undefined Undefined Undefined R/W: 11.2.8 Year Counter (RYRCNT)
Page 404: Second Alarm Register (Rsecar)
Section 11 Realtime Clock (RTC) 11.2.9 Second Alarm Register (RSECAR) RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared with the RSECCNT value.
Page 405: Hour Alarm Register (Rhrar)
Section 11 Realtime Clock (RTC) 11.2.11 Hour Alarm Register (RHRAR) RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with the RHRCNT value.
Page 406: Day Alarm Register (Rdayar)
Section 11 Realtime Clock (RTC) Bit: — — — — Day of week code Initial value: Undefined Undefined Undefined R/W: Day-of-week code Day of week 11.2.13 Day Alarm Register (RDAYAR) RDAYAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD- coded day value counter, RDAYCNT.
Page 407: Month Alarm Register (Rmonar)
Section 11 Realtime Clock (RTC) 11.2.14 Month Alarm Register (RMONAR) RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD- coded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is compared with the RMONCNT value.
Page 408 Section 11 Realtime Clock (RTC) Bit 7—Carry Flag (CF): This flag is set to 1 on generation of a second counter carry, or a 64 Hz counter carry when the 64 Hz counter is read. The count register value read at this time is not guaranteed, and so the count register must be read again.
Page 409: Rtc Control Register 2 (Rcr2)
Section 11 Realtime Clock (RTC) Bit 0—Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1 matches the respective counter values. Bit 0: AF Description Alarm registers and counter values do not match...
Page 410 Section 11 Realtime Clock (RTC) Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated. Bit 7: PEF Description Interrupt is not generated at interval specified by bits PES2–PES0 [Clearing condition] When 0 is written to PEF Interrupt is generated at interval specified by bits PES2–PES0...
Page 411: Rtc Control Register 3 (Rcr3) And Year-Alarm Register (Ryrar)
Section 11 Realtime Clock (RTC) Bit 2—30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is rounded up to 1 minute.
Page 412 Section 11 Realtime Clock (RTC) RCR3 is initialized by a power-on reset, but RYRAR will not be initialized by a power-on or manual reset, or by the device entering standby mode. Bits 6 to 0 of RCR3 are always read as 0. Writing to these bits is invalid. If a value is written to these bits, it should always be 0.
Page 413: Operation
Section 11 Realtime Clock (RTC) 11.3 Operation Examples of the use of the RTC are shown below. 11.3.1 Time Setting Procedures Figure 11.2 shows examples of the time setting procedures. Set RCR2.RESET to 1 Stop clock Clear RCR2.START to 0 Reset frequency divider Set second/minute/hour/day/ In any order...
Page 414: Time Reading Procedures
Section 11 Realtime Clock (RTC) The procedure for setting the time while the clock is running is shown in (b). This method is useful for modifying only certain counter values (for example, only the second data or hour data). If a carry occurs during the write operation, the write data is automatically updated and there will be an error in the set data.
Page 415: Figure 11.3 Examples Of Time Reading Procedures
Section 11 Realtime Clock (RTC) Clear RCR1.CIE to 0 Disable carry interrupts Clear RCR1.CF to 0 Clear carry flag (Write 1 to RCR1.AF so that alarm flag is not cleared) Read counter register Carry flag = 1? Read RCR1 register and check CF bit (a) Reading time without using interrupts Clear carry flag Set RCR1.CIE to 1...
Page 416: Alarm Function
Section 11 Realtime Clock (RTC) 11.3.3 Alarm Function The use of the alarm function is illustrated in figure 11.4. Clock running Disable alarm interrupts Clear RCR1.AIE to prevent erroneous interrupts Set alarm time Be sure to reset the flag as it may have been Clear alarm flag set during alarm time setting Set RCR1.AIE to 1...
Page 417: Interrupts
Section 11 Realtime Clock (RTC) 11.4 Interrupts There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts. An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while the alarm interrupt enable bit (AIE) is also set to 1.
Page 418: Rtc Register Settings (Sh7750 Only)
Section 11 Realtime Clock (RTC) SH7750 SH7750S SH7750R EXTAL2 XTAL2 VDD-RTC VSS-RTC XTAL Noise filter 3.3 V Notes: 1. Select either the C or C side for the frequency adjustment variable capacitor according to requirements such as the adjustment range, degree of stability, etc. 2.
Page 419 Section 11 Realtime Clock (RTC) 1. Disable the DMAC channels used to access peripheral registers before writing to an RTC register, and write to the RTC register while the exception/interrupt block bit (SR.BL) in the status register is set to 1. Then use the next instruction to read from the same register. 2.
Page 420 Section 11 Realtime Clock (RTC) 3. Use the following method to write to an RTC register. Read all writeable counter registers (1) Write 0 to RCR2.RTCEN Read all writeable counter registers (2) Compare the values of (1) and (2) Are the compared values valid? Write the valid value Write to the register whose value is to be changed...
Page 421: Section 12 Timer Unit (Tmu)
Section 12 Timer Unit (TMU) Section 12 Timer Unit (TMU) 12.1 Overview This LSI of microprocessors includes an on-chip 32-bit timer unit (TMU). The TMU of the SH7750 or SH7750S has three 32-bit timer channels (channels 0 to 2), and the TMU of the SH7750R has five channels (channels 0 to 4).
Page 422: Block Diagram
Section 12 Timer Unit (TMU) 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the TMU. RESET, STBY, TUNE0,TUNE1 Pck/4,16, 64 TUNI2 ICPI2 TCLK RTCCLK TUNI3, 4 etc. TCLK Prescaler control unit control unit To each To channels TOCR channel 0 to 2 TSTR...
Page 423: Register Configuration
Section 12 Timer Unit (TMU) 12.1.4 Register Configuration Table 12.2 summarizes the TMU registers. Table 12.2 TMU Registers Initialization Power- Stand- Chan- Abbre- Manual Area 7 Access Name viation R/W Reset Reset Mode Initial Value P4 Address Address Size Com- Timer TOCR R/W Ini-...
Page 424 Section 12 Timer Unit (TMU) Initialization Power- Stand- Chan- Abbre- Manual Area 7 Access Name viation R/W Reset Reset Mode Initial Value P4 Address Address Size Timer TCOR2 R/W Ini- Ini- Held H'FFFFFFFF H'FFD80020 H'1FD80020 32 constant tialized tialized register 2 Held * Timer TCNT2 R/W Ini-...
Page 425: Register Descriptions
Section 12 Timer Unit (TMU) 12.2 Register Descriptions 12.2.1 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that specifies whether external pin TCLK is used as the external clock or input capture control input pin, or as the on-chip RTC output clock output pin.
Page 426: Timer Start Register (Tstr)
Section 12 Timer Unit (TMU) 12.2.2 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that specifies whether the channel 0–2 timer counters (TCNT) are operated or stopped. TSTR is initialized to H'00 by a power-on or manual reset, or standby mode. In module standby mode, TSTR is not initialized when the input clock selected by each channel is the on-chip RTC output clock (RTCCLK), and is initialized only when the input clock is the external clock (TCLK) or internal clock (Pck).
Page 427: Timer Start Register 2 (Tstr2) (Sh7750R Only)
Section 12 Timer Unit (TMU) Bit 0—Counter Start 0 (STR0): Specifies whether timer counter 0 (TCNT0) is operated or stopped. Bit 0: STR0 Description TCNT0 count operation is stopped (Initial value) TCNT0 performs count operation 12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only) TSTR2 is an 8-bit readable/writable register that specifies whether the channels 3−4 timer counters (TSTR2) run or are stopped.
Page 428: Timer Constant Registers (Tcor)
Section 12 Timer Unit (TMU) 12.2.4 Timer Constant Registers (TCOR) The TCOR registers are 32-bit readable/writable registers. There are TCOR registers, one for each channel. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value.
Page 429: Timer Control Registers (Tcr)
Section 12 Timer Unit (TMU) The TCNT registers for channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual reset, but are not initialized and retain their contents in standby mode. The TCNT registers for channels 3 and 4 of the SH7750R are initialized to H'FFFFFFFF by a power-on reset, but are not initialized and retain their contents on a manual reset and in standby mode.
Page 430 Section 12 Timer Unit (TMU) 1. Channel 0 and 1 TCR bit configuration Bit: — — — — — — — Initial value: R/W: Bit: — — UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value: R/W: 2. Channel 2 TCR bit configuration Bit: —...
Page 431 Section 12 Timer Unit (TMU) 3. TCR bit configuration for channels 3 and 4 (SH7750R only) Bit: — — — — — — — Initial value: R/W: Bit: — — UNIE — — TPSC2 TPSC1 TPSC0 Initial value: R/W: Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)—Reserved: These bits are always read as 0.
Page 432 Section 12 Timer Unit (TMU) Bit 8—Underflow Flag (UNF): Status flag that indicates the occurrence of underflow. Bit 8: UNF Description TCNT has not underflowed (Initial value) [Clearing condition] When 0 is written to UNF TCNT has underflowed [Setting condition] When TCNT underflows* Note: Writing 1 does not change the value.
Page 433 Section 12 Timer Unit (TMU) Bit 5—Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1, indicating TCNT underflow. Bit 5: UNIE Description Interrupt due to underflow (TUNI) is not enabled (Initial value) Interrupt due to underflow (TUNI) is enabled Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the external clock input...
Page 434: Input Capture Register 2 (Tcpr2)
Section 12 Timer Unit (TMU) 12.2.7 Input Capture Register 2 (TCPR2) TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in channel 2. The input capture function is controlled by means of the input capture control bits (ICPE) and clock edge bits (CKEG) in TCR2.
Page 435: Figure 12.2 Example Of Count Operation Setting Procedure
Section 12 Timer Unit (TMU) Example of Count Operation Setting Procedure: Figure 12.2 shows an example of the count operation setting procedure. 1. Select the count clock, for channel 0, 1, or 2, with bits TPSC2–TPSC0 in the timer control register (TCR).
Page 436: Figure 12.3 Tcnt Auto-Reload Operation
Section 12 Timer Unit (TMU) Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation. TCNT value TCOR value set in TCNT on underflow TCOR H'00000000 Time STR0–STR2 Figure 12.3 TCNT Auto-Reload Operation TCNT Count Timing: • Operating on internal clock Any of five count clocks (Pck/4, Pck/16, Pck/64, Pck/256, or Pck/1024) scaled from the peripheral module clock can be selected as the count clock by means of the TPSC2–TPSC0 bits in TCR.
Page 437: Input Capture Function
Section 12 Timer Unit (TMU) • Operating on external clock For channels 0 to 2, external clock pin (TCLK) input can be selected as the timer clock by means of the TPSC2–TPSC0 bits in TCR. The rising edge, falling edge, or both edges can be selected as the detected edge of the external clock with the CKEG1 and CKEG0 bits in TCR.
Page 438: Figure 12.7 Operation Timing When Using Input Capture Function
Section 12 Timer Unit (TMU) 3. Use bits IPCE1 and IPCE0 in TCR to specify use of the input capture function, and whether interrupts are to generated when this function is used. 4. Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK signal is to be used to set the timer counter (TCNT) value in the input capture register (TCPR2).
Page 439: Interrupts
Section 12 Timer Unit (TMU) 12.4 Interrupts There are four TMU interrupt sources, comprising underflow interrupts and the input capture interrupt (when the input capture function is used). Underflow interrupts are generated on each of the channels, and input capture interrupts on channel 2 only. An underflow interrupt request is generated (for each channel) when the UNF bit in TCR is 1 and the interrupt enable bit for the corresponding channel is 1.
Page 440: Underflow Flag Writes (Sh7750 Only)
Section 12 Timer Unit (TMU) 12.5.2 Underflow Flag Writes (SH7750 only) If 1 is written to the UNF bit in TCR when the UNF bit is already set to 1, the UNF bit may be cleared to 0. The following workarounds can be used to avoid this problem. 1.
Page 441: Section 13 Bus State Controller (Bsc)
Section 13 Bus State Controller (BSC) Section 13 Bus State Controller (BSC) 13.1 Overview The functions of the bus state controller (BSC) include division of the external memory space, and output of control signals in accordance with various types of memory and bus interface specifications.
Page 442 Section 13 Bus State Controller (BSC) ⎯ 8-CAS byte control for power-down operation ⎯ DRAM control signal timing can be controlled by register settings ⎯ Consecutive accesses to the same row address Connectable areas: 2, 3 Settable bus widths: 64, 32, 16 •...
Page 443: Block Diagram
Section 13 Bus State Controller (BSC) Note: * SH7750R only 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the BSC. interface WCR1 Wait control unit WCR2 WCR3 BCR1 CS6–CS0 Area CE2A–CE2B control unit BCR2 BCR3 * RD/FRAME RD/WR WE7–WE0 BCR4 * CAS7–CAS0, CASS...
Page 444: Pin Configuration
Section 13 Bus State Controller (BSC) 13.1.3 Pin Configuration Table 13.1 shows the BSC pin configuration. Table 13.1 BSC Pins Name Signals Description Address bus A25−A0 Address output Data bus D63−D52, Data input/output D31−D0 When port functions are used and DDT mode is selected, input the DTR format.
Page 445 Section 13 Bus State Controller (BSC) Name Signals Description WE0/CAS0/ Data enable 0 When setting synchronous DRAM interface: DQM0 selection signal for D7–D0 When setting DRAM interface: CAS signal for D7–D0 When setting MPX interface: high-level output In other cases: write strobe signal for D7–D0 WE1/CAS1/ Data enable 1 When setting synchronous DRAM interface:...
Page 446 Section 13 Bus State Controller (BSC) Name Signals Description WE5/CAS5/ Data enable 5 When setting synchronous DRAM interface: DQM5 selection signal for D47–D40 When setting DRAM interface: CAS signal for D47–D40 When setting MPX interface: high-level output In other cases: write strobe signal for D47–D40 WE6/CAS6/ Data enable 6 When setting synchronous DRAM interface:...
Page 447 Section 13 Bus State Controller (BSC) Name Signals Description Indicates master/slave status in a power-on reset. * Master/slave MD7/TXD switchover Serial interface TXD DMAC0 DACK0 DMAC channel 0 data acknowledge acknowledge signal DMAC1 DACK1 DMAC channel 1 data acknowledge acknowledge signal Same signal as RD/CASS/FRAME Read/column...
Page 448: Register Configuration
Section 13 Bus State Controller (BSC) 13.1.4 Register Configuration The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode register incorporated in synchronous DRAM can also be accessed as this LSI's register. The functions of these registers include control of interfaces to various types of memory, wait states, and refreshing.
Page 449: Overview Of Areas
Section 13 Bus State Controller (BSC) 13.1.5 Overview of Areas Space Divisions: The architecture of this LSI provides a 32-bit virtual address space. The virtual address is divided into five areas according to the upper address value. External memory space comprises a 29-bit address space, divided into eight areas.
Page 450: Table 13.3 External Memory Space Map
Section 13 Bus State Controller (BSC) Table 13.3 External Memory Space Map External Connectable Settable Bus Area Addresses Size Memory Widths Access Size 8, 16, 32, 64 * H'00000000– 64 Mbytes SRAM 8, 16, 32, 64 * H'03FFFFFF bits, 8, 16, 32 * , 64 * Burst ROM 32 bytes...
Page 451: Figure 13.3 External Memory Space Allocation
Section 13 Bus State Controller (BSC) 6. 64-bit access applies only to transfer by the DMAC. (CHCRn. TS = 000) In a transfer to an external memory by FMOV (FPSCR.SZ = 1), two transfer operations, each with an access size of 32 bits, are conducted. 7.
Page 452: Pcmcia Support
Section 13 Bus State Controller (BSC) memory control register (MCR). When the DRAM interface is used for area 2 or 3, a bus width of 16 or 32 bits should be set. For the synchronous DRAM interface, set a bus width of 32 or 64 bits in the MCR register.
Page 453: Table 13.5 Pcmcia Support Interfaces
Section 13 Bus State Controller (BSC) Table 13.5 PCMCIA Support Interfaces IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name I/O Function Name I/O Function LSI Pin Ground Ground — I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data...
Page 454 Section 13 Bus State Controller (BSC) IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name I/O Function Name I/O Function LSI Pin Address Address Address Address I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data WP * IOIS16 IOIS16...
Page 455 Section 13 Bus State Controller (BSC) IC Memory Card Interface I/O Card Interface Signal Signal Corresponding Name I/O Function Name I/O Function LSI Pin Address Address Reserved Reserved — RESET Reset RESET Reset Output from port WAIT WAIT RDY* Wait request Wait request INPACK Reserved...
Page 456: Register Descriptions
Section 13 Bus State Controller (BSC) 13.2 Register Descriptions 13.2.1 Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus cycle status, etc., of each area. BCR1 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 457 Section 13 Bus State Controller (BSC) Bit 31—Endian Flag (ENDIAN): Samples the value of the endian specification external pin (MD5) in a power-on reset by the RESET pin. The endian mode of all spaces is determined by this bit. ENDIAN is a read-only bit. Bit 31: ENDIAN Description In a power-on reset, the endian setting external pin (MD5) is low,...
Page 458 Section 13 Bus State Controller (BSC) Bit 26—Data pin Pullup Resistor Control (DPUP) (SH7750R only): Controls the pullup resistance of the data pins (D63 to D0). It is initialized at a power-on reset. The pins are not pulled up when access is performed or when the bus is released, even if the ON setting is selected. Bit 26: DPUP Description Sets pullup resistance of data pins (D63 to D0) ON...
Page 459 Section 13 Bus State Controller (BSC) Bit 20—Area 4 SRAM Byte Control Mode (A4MBC): MPX interface has priority when an MPX interface is set. This bit is initialized by a power-on reset. Bit 20: A4MBC Description Area 4 SRAM is set to normal mode (Initial value) Area 4 SRAM is set to byte control mode Bit 19—BREQ Enable (BREQEN): Indicates whether external requests can be accepted.
Page 460 Section 13 Bus State Controller (BSC) Bit 16—DMAC Burst Mode Transfer Priority Setting (DMABST) (SH7750R Only): Specifies the priority of burst mode transfers by the DMAC. When OFF, the priority is as follows: bus privilege released, refresh, DMAC, CPU. When ON, the bus privileges are released and refresh operations are not performed until the end of the DMAC's burst transfer.
Page 461 Section 13 Bus State Controller (BSC) Bits 13 to 11—Area 0 Burst ROM Control (A0BST2–A0BST0): These bits specify whether burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 0 is an MPX interface area, these bits are ignored. Bit 13: A0BST2 Bit 12: A0BST1 Bit 11: A0BST0...
Page 462 Section 13 Bus State Controller (BSC) Bits 10 to 8—Area 5 Burst Enable (A5BST2–A5BST0): These bits specify whether burst ROM interface is used in area 5. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 5 is an MPX interface area, these bits are ignored. Bit 10: A5BST2 Bit 9: A5BST1 Bit 8: A5BST0...
Page 463 Section 13 Bus State Controller (BSC) Bits 7 to 5—Area 6 Burst Enable (A6BST2–A6BST0): These bits specify whether burst ROM interface is used in area 6. When burst ROM interface is used, they also specify the number of accesses in a burst. If area 6 is an MPX interface area, these bits are ignored. Bit 7: A6BST2 Bit 6: A6BST1 Bit 5: A6BST0...
Page 464 Section 13 Bus State Controller (BSC) Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as SRAM interface. DRAM and synchronous DRAM can also be connected. Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description Areas 2 and 3 are SRAM interface or MPX interface *...
Page 465: Bus Control Register 2 (Bcr2)
Section 13 Bus State Controller (BSC) 13.2.2 Bus Control Register 2 (BCR2) Bus control register 2 (BCR2) is a 16-bit readable/writable register that specifies the bus width for each area, and whether a 16-bit port is used. BCR2 is initialized to H'3FFC by a power-on reset, but is not initialized by a manual reset or in standby mode.
Page 466 Section 13 Bus State Controller (BSC) Bits 2n + 1, 2n—Area n (1 to 6) Bus Width Specification (AnSZ1, AnSZ0): These bits specify the bus width of area n (n = 1 to 6). (Bit 0): PORTEN Bit 2n + 1: AnSZ1 Bit 2n: AnSZ0 Description Bus width is 64 bits...
Page 467: Bus Control Register 3 (Bcr3) (Sh7750R Only)
Section 13 Bus State Controller (BSC) 13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only) Bus control register 3 (BCR3) is a 16-bit readable/writable register that specifies the selection of either the MPX interface or the SRAM interface and specifies the burst length when the synchronous DRAM interface is used.
Page 468: Bus Control Register 4 (Bcr4) (Sh7750R Only)
Section 13 Bus State Controller (BSC) Bits 14 and 13⎯MPX-Interface Specification for Area 1 and 4 (A1MPX, A4MPX): These bits specify the types of memory connected to areas 1 and 4. These settings are validated by MEMMODE. Bit 14: A1MPX Description SRAM/byte control SRAM interface is selected for area 1 (Initial value)
Page 469: Figure 13.4 Example Of Rdy Sampling Timing At Which Bcr4 Is Set
Section 13 Bus State Controller (BSC) CKIO (BCR4.ASYNC0 = 0) (BCR4.ASYNC0 = 1) Figure 13.4 Example of RDY Sampling Timing at which BCR4 Is Set (Two Wait Cycles Are Inserted by WCR2) Rev.7.00 Oct. 10, 2008 Page 385 of 1074 REJ09B0366-0700...
Page 470 Section 13 Bus State Controller (BSC) Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — — — — Initial value: R/W: Bit: —...
Page 471 Section 13 Bus State Controller (BSC) Bits 31 to 5⎯Reserved: These bits are always read as 0, and should only be written with 0. Bits 4 to 0⎯Asynchronous Input: These bits enable asynchronous input to the corresponding pin. Bits 4 to 0: ASYNCn Description Input to corresponding pin is synchronous with CKIO (Initial value)
Page 472: Wait Control Register 1 (Wcr1)
Section 13 Bus State Controller (BSC) 13.2.5 Wait Control Register 1 (WCR1) Wait control register 1 (WCR1) is a 32-bit readable/writable register that specifies the number of idle state insertion cycles for each area. With some kinds of memory, data bus drive does not go off immediately after the read signal from off-chip goes off.
Page 473 Section 13 Bus State Controller (BSC) Bits 31, 27, 23, 19, 15, 11, 7, and 3—Reserved: These bits are always read as 0, and should only be written with 0. Bits 30 to 28— DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2– DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when switching from a DACK device to another space, or from a read access to a write access on the same device.
Page 474 Section 13 Bus State Controller (BSC) • Idle Insertion between Accesses Following Cycle Same Different Same Area Different Area Area Area Read Write Read Write Preceding Address Address Cycle CPU DMA CPU DMA CPU DMA CPU DMA Output Output Read M (1) M (1) Write...
Page 475: Wait Control Register 2 (Wcr2)
Section 13 Bus State Controller (BSC) 13.2.6 Wait Control Register 2 (WCR2) Wait control register 2 (WCR2) is a 32-bit readable/writable register that specifies the number of wait states to be inserted for each area. It also specifies the data access pitch when performing burst memory access.
Page 476 Section 13 Bus State Controller (BSC) Bits 31 to 29—Area 6 Wait Control (A6W2—A6W0): These bits specify the number of wait states to be inserted for area 6. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description First Cycle RDY Pin...
Page 477 Section 13 Bus State Controller (BSC) Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait states to be inserted for area 5. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description First Cycle RDY Pin...
Page 478 Section 13 Bus State Controller (BSC) Bits 19 to 17—Area 4 Wait Control (A4W2–A4W0): These bits specify the number of wait states to be inserted for area 4. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6). Description RDY Pin Bit 19: A4W2...
Page 479 Section 13 Bus State Controller (BSC) • When DRAM or Synchronous DRAM Interface is Set* Description DRAM CAS Synchronous DRAM CAS Latency Cycles Bit 15: A3W2 Bit 14: A3W1 Bit 13: A3W0 Assertion Width Inhibited Inhibited Inhibited Notes: 1. External wait input is always ignored. 2.
Page 480 Section 13 Bus State Controller (BSC) • When DRAM or Synchronous DRAM Interface is Set* Description DRAM CAS Synchronous DRAM CAS Latency Cycles Bit 11: A2W2 Bit 10: A2W1 Bit 9: A2W0 Assertion Width Inhibited Inhibited Inhibited Notes: 1. External wait input is always ignored. 2.
Page 481 Section 13 Bus State Controller (BSC) Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait states to be inserted for area 0. For details on MPX interface setting, see table 13.6, MPX Interface is Selected (Areas 0 to 6).
Page 482: Table 13.6 Mpx Interface Is Selected (Areas 0 To 6)
Section 13 Bus State Controller (BSC) Table 13.6 MPX Interface is Selected (Areas 0 to 6) Description Inserted Wait States 1st Data 2nd Data RDY Pin Onward AnW2 AnW1 AnW0 Read Write Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Note: n = 6 to 0 Rev.7.00 Oct.
Page 483: Wait Control Register 3 (Wcr3)
Section 13 Bus State Controller (BSC) 13.2.7 Wait Control Register 3 (WCR3) Wait control register 3 (WCR3) is a 32-bit readable/writable register that specifies the cycles inserted in the setup time from the address until assertion of the write strobe, and the data hold time from negation of the strobe, for each area.
Page 484 Section 13 Bus State Controller (BSC) Bit 4n + 2—Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles inserted in the setup time from the address until assertion of the read/write strobe. Valid only for SRAM interface, byte control SRAM interface, and burst ROM interface.
Page 485: Memory Control Register (Mcr)
Section 13 Bus State Controller (BSC) 13.2.8 Memory Control Register (MCR) The memory control register (MCR) is a 32-bit readable/writable register that specifies RAS and CAS timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address multiplexing, and refresh control.
Page 486 Section 13 Bus State Controller (BSC) Bit 31—RAS Down (RASD): Sets RAS down mode. When DRAM/RAS down mode is used, set BE to 1. Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3 are both designated as synchronous DRAM interface.
Page 487 Section 13 Bus State Controller (BSC) Bits 26 to 24, 22, and 18—Reserved: These bits are always read as 0, and should only be written with 0. Bit 23—CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set. Bit 23: TCAS CAS Negation Period (Initial value)
Page 488 Section 13 Bus State Controller (BSC) Bits 17 and 16—RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits set the RAS-CAS assertion delay time. When the synchronous DRAM interface is set, these bits set the bank active-read/write command delay time. Description Bit 17: RCD1 Bit 16: RCD0...
Page 489 Section 13 Bus State Controller (BSC) Bits 12 to 10—CAS-Before-RAS Refresh RAS Assertion Period (TRAS2–TRAS0): When the DRAM interface is set, these bits set the RAS assertion period in CAS-before-RAS refreshing. When the synchronous DRAM interface is set, the bank active command is not issued for the period set by the TRC[2:0]* and TRAS[2:0] bits after an auto-refresh command is issued.
Page 490 Section 13 Bus State Controller (BSC) Bits 8 and 7—Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and synchronous DRAM. This setting has priority over the BCR2 register setting. Description Bit 8: SZ1 Bit 7: SZ0 DRAM SDRAM 64 bits...
Page 491 Section 13 Bus State Controller (BSC) • For Synchronous DRAM Interface: BANK * AMXEXT Example of Synchronous DRAM (16M: 512K × 16 bits × 2) × 4 a[22] * (16M: 512K × 16 bits × 2) × 2 a[21] * (16M: 512K ×...
Page 492 Section 13 Bus State Controller (BSC) Bit 2—Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is performed for DRAM and synchronous DRAM. When the refresh function is not used, the refresh request cycle generation timer can be used as an interval timer. Bit 2: RFSH Description Refreshing is not performed...
Page 493: Pcmcia Control Register (Pcr)
Section 13 Bus State Controller (BSC) 13.2.9 PCMCIA Control Register (PCR) The PCMCIA control register (PCR) is a 16-bit readable/writable register that specifies the OE and WE signal assertion/negation timing for the PCMCIA interface connected to areas 5 and 6. The OE and WE signal assertion width is set by the wait control bits in the WCR2 register.
Page 494 Section 13 Bus State Controller (BSC) Bits 13 and 12—PCMCIA Wait (A6PCW1, A6PCW0): These bits specify the number of waits to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The setting of these bits is selected when the PCMCIA interface access TC bit is set to 1. Bit 13: A6PCW1 Bit 12: A6PCW0 Waits Inserted...
Page 495 Section 13 Bus State Controller (BSC) Bits 8 to 6—Address-OE/WE Assertion Delay (A6TED2–A6TED0): These bits set the delay time from address output to OE/WE assertion on the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is set to 1. Bit 8: A6TED2 Bit 7: A6TED1 Bit 6: A6TED0...
Page 496 Section 13 Bus State Controller (BSC) Bits 2 to 0—OE/WE Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address hold delay time from OE/WE negation in a write on the connected PCMCIA interface or in an I/O card read. In the case of a memory card read, the address hold delay time from the data sampling timing is set.
Page 497: Synchronous Dram Mode Register (Sdmr)
Section 13 Bus State Controller (BSC) 13.2.10 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is a write-only virtual 16-bit register that is written to via the synchronous DRAM address bus, and sets the mode of the area 2 and area 3 synchronous DRAM.
Page 498 Section 13 Bus State Controller (BSC) Bus Width Burst Length CAS Latency Area 2 Area 3 H'FF900048 H'FF940048 H'FF900088 H'FF940088 H'FF9000C8 H'FF9400C8 H'FF90004C H'FF94004C H'FF90008C H'FF94008C H'FF9000CC H'FF9400CC H'FF900090 H'FF940090 H'FF900110 H'FF940110 H'FF900190 H'FF940190 For a 32-bit bus: Address WT BL2 BL1 BL0 ←⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯→...
Page 499: Refresh Timer Control/Status Register (Rtcsr)
Section 13 Bus State Controller (BSC) LMODE 000: Reserved 000: Reserved 001: Reserved 001: 1 010: 4 010: 2 011: 8 011: 3 100: Reserved 100: Reserved 101: Reserved 101: Reserved 110: Reserved 110: Reserved 111: Reserved 111: Reserved Note: * SH7750R only. 13.2.11 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that specifies the refresh cycle and whether interrupts are to be generated.
Page 500 Section 13 Bus State Controller (BSC) Bit 7—Compare-Match Flag (CMF): Status flag that indicates a match between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR) values. Bit 7: CMF Description RTCNT and RTCOR values do not match (Initial value) [Clearing condition] When 0 is written to CMF...
Page 501 Section 13 Bus State Controller (BSC) Bit 2—Refresh Count Overflow Flag (OVF): Status flag that indicates that the number of refresh requests indicated by the refresh count register (RFCR) has exceeded the number specified by the LMTS bit in RTCSR. Bit 2: OVF Description RFCR has not overflowed the count limit indicated by LMTS...
Page 502: Refresh Timer Counter (Rtcnt)
Section 13 Bus State Controller (BSC) 13.2.12 Refresh Timer Counter (RTCNT) The refresh timer counter (RTCNT) is an 8-bit readable/writable counter that is incremented by the input clock (selected by bits CKS2–CKS0 in the RTCSR register). When the RTCNT counter value matches the RTCOR register value, the CMF bit is set in the RTCSR register and the RTCNT counter is cleared.
Page 503: Refresh Time Constant Register (Rtcor)
Section 13 Bus State Controller (BSC) 13.2.13 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) is a readable/writable register that specifies the upper limit of the RTCNT counter. The RTCOR register and RTCNT counter values (lower 8 bits) are constantly compared, and when they match the CMF bit is set in the RTCSR register and the RTCNT counter is cleared to 0.
Page 504: Refresh Count Register (Rfcr)
Section 13 Bus State Controller (BSC) 13.2.14 Refresh Count Register (RFCR) The refresh count register (RFCR) is a 10-bit readable/writable counter that counts the number of refreshes by being incremented each time the RTCOR register and RTCNT counter values match. If the RFCR register value exceeds the count limit specified by the LMTS bit in the RTCSR register, the OVF flag is set in the RTCSR register and the RFCR register is cleared.
Page 505: Operation
Section 13 Bus State Controller (BSC) RTCSR, RTCNT, Write data RTCOR Write data RFCR Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR Reading RTCSR, RTCNT, RTCOR, and RFCR: A 16-bit access must always be used when reading RTCSR, RTCNT, RTCOR, or RFCR. Undefined bits are read as 0. 13.3 Operation 13.3.1...
Page 506 Section 13 Bus State Controller (BSC) Data Configuration Byte Data 7 to 0 Word Data 15 to 8 Data 7 to 0 Longword Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Quadword Data Data Data...
Page 507: Table 13.7 (1) 64-Bit External Device/Big-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Access Size Address No. D63–56 D55–48 D47–40 D39–32 D31–24 D23–16 D15–8 D7–0 Byte Data — — — — — — — 7–0 8n + 1 —...
Page 508: Table 13.7 (2) 64-Bit External Device/Big-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment Operation Strobe Signals WE7, WE6, WE5, WE4, WE3, WE2, WE1, WE0, CAS7, CAS6, CAS5, CAS4, CAS3, CAS2, CAS1, CAS0, Access Size Address No. DQM7 DQM6 DQM5 DQM4...
Page 509: Table 13.8 32-Bit External Device/Big-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3, CAS2, CAS1, CAS0, Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1 DQM0 Byte Data —...
Page 510: Table 13.9 16-Bit External Device/Big-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3, CAS2, CAS1, CAS0, Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1 DQM0 Byte —...
Page 511: Table 13.10 8-Bit External Device/Big-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3, CAS2, CAS1, CAS0, Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1 DQM0 Byte —...
Page 512: Table 13.11 (1) 64-Bit External Device/Little-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Access Size Address No. D63–56 D55–48 D47–40 D39–32 D31–24 D23–16 D15–8 D7–0 Byte — — — — — — — Data 7–0 8n + 1 —...
Page 513: Table 13.11 (2) 64-Bit External Device/Little-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment Operation Strobe Signals WE7, WE6, WE5, WE4, WE3, WE2, WE1, WE0, CAS7, CAS6, CAS5, CAS4, CAS3, CAS2, CAS1, CAS0, Access Size Address No. DQM7 DQM6 DQM5 DQM4...
Page 514: Table 13.12 32-Bit External Device/Little-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3, CAS2, CAS1, CAS0, Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1 DQM0 Byte —...
Page 515: Table 13.13 16-Bit External Device/Little-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3, CAS2, CAS1, CAS0, Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1 DQM0 Byte —...
Page 516: Table 13.14 8-Bit External Device/Little-Endian Access And Data Alignment
Section 13 Bus State Controller (BSC) Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment Operation Data Bus Strobe Signals WE3, WE2, WE1, WE0, CAS3, CAS2, CAS1, CAS0, Access Size Address No. D31–D24 D23–D16 D15–D8 D7–D0 DQM3 DQM2 DQM1 DQM0 Byte —...
Page 517: Areas
Section 13 Bus State Controller (BSC) 13.3.2 Areas Area 0: For area 0, external address bits A28 to A26 are 000. SRAM, MPX, and burst ROM can be set to this area. A bus width of 8, 16, 32, or 64 bits can be selected in a power-on reset by means of external pins MD4 and MD3.
Page 518 Section 13 Bus State Controller (BSC) Area 2: For area 2, external address bits A28 to A26 are 010. SRAM, MPX, DRAM, and synchronous DRAM can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A2SZ1 and A2SZ0 in the BCR2 register.
Page 519 Section 13 Bus State Controller (BSC) When area 3 is accessed, the CS3 signal is asserted. When SRAM interface is set, the RD signal, which can be used as OE, and write control signals WE0 to WE7, are asserted. As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A3W2 to A3W0 in the WCR2 register.
Page 520 Section 13 Bus State Controller (BSC) Area 5: For area 5, external address bits A28 to A26 are 101. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A5SZ1 and A5SZ0 in the BCR2 register.
Page 521 Section 13 Bus State Controller (BSC) Area 6: For area 6, external address bits A28 to A26 are 110. SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area. When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A6SZ1 and A6SZ0 in the BCR2 register.
Page 522: Sram Interface
Section 13 Bus State Controller (BSC) 13.3.3 SRAM Interface Basic Timing: The SRAM interface of this LSI uses strobe signal output in consideration of the fact that mainly SRAM will be connected. Figure 13.6 shows the basic timing of normal space accesses.
Page 523: Figure 13.6 Basic Timing Of Sram Interface
Section 13 Bus State Controller (BSC) CKIO A25–A0 RD/WR D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Legend: SA: Single address DMA DA: Dual address DMA Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.6 Basic Timing of SRAM Interface Rev.7.00 Oct.
Page 524: Figure 13.7 Example Of 64-Bit Data Width Sram Connection
Section 13 Bus State Controller (BSC) Figures 13.7 to 13.10 show examples of connection to 64-, 32-, 16-, and 8-bit data width SRAM. × 128K 8-bit SH7750, SH7750S, SH7750R SRAM A19–A3 A16–A0 D63–D56 I/O7–I/O0 A16–A0 D55–D48 I/O7–I/O0 A16–A0 D47–D40 I/O7–I/O0 A16–A0 D39–D32 I/O7–I/O0...
Page 525: Figure 13.8 Example Of 32-Bit Data Width Sram Connection
Section 13 Bus State Controller (BSC) 128K × 8-bit SH7750, SH7750S, SH7750R SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 13.8 Example of 32-Bit Data Width SRAM Connection Rev.7.00 Oct. 10, 2008 Page 441 of 1074 REJ09B0366-0700...
Page 526: Figure 13.9 Example Of 16-Bit Data Width Sram Connection
Section 13 Bus State Controller (BSC) 128K × 8-bit SH7750, SH7750S, SH7750R SRAM I/O7 I/O0 I/O7 I/O0 Figure 13.9 Example of 16-Bit Data Width SRAM Connection Rev.7.00 Oct. 10, 2008 Page 442 of 1074 REJ09B0366-0700...
Page 527: Figure 13.10 Example Of 8-Bit Data Width Sram Connection
Section 13 Bus State Controller (BSC) 128K × 8-bit SH7750, SH7750S, SH7750R SRAM I/O7 I/O0 Figure 13.10 Example of 8-Bit Data Width SRAM Connection Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2 settings.
Page 528: Figure 13.11 Sram Interface Wait Timing (Software Wait Only)
Section 13 Bus State Controller (BSC) CKIO A25–A0 RD/WR D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.11 SRAM Interface Wait Timing (Software Wait Only) Rev.7.00 Oct.
Page 529: Figure 13.12 Sram Interface Wait State Timing (Wait State Insertion By Rdy Signal)
Section 13 Bus State Controller (BSC) When software wait insertion is specified by WCR2, the external wait input RDY signal is also sampled. RDY signal sampling is shown in figure 13.12. A single-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, the RDY signal has no effect if asserted in the T1 cycle or the first Tw cycle.
Page 530: Figure 13.13 Sram Interface Read-Strobe Negate Timing (Ans = 1, Anw = 4, Anh = 2)
Section 13 Bus State Controller (BSC) Read-Strobe Negate Timing (Setting Only Possible in the SH7750R): When the SRAM interface is used, timing for the negation of the strobe during read operations can be specified by the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this setting, see the description of the WCR3 register.
Page 531: Dram Interface
Section 13 Bus State Controller (BSC) 13.3.4 DRAM Interface Direct Connection of DRAM: When the memory type bits (DRAMTP2–0) in BCR1 are set to 100, area 3 becomes DRAM space; when set to 101, area 2 and area 3 become DRAM space. The DRAM interface function can then be used to connect DRAM to this LSI.
Page 532: Figure 13.14 Example Of Dram Connection (64-Bit Data Width, Area 3)
Section 13 Bus State Controller (BSC) 1M × 16-bit SH7750, SH7750S, SH7750R DRAM A12–A3 A9–A0 RD/WR I/O15–I/O0 D63–D48 UCAS LCAS A9–A0 D47–D32 I/O15–I/O0 UCAS LCAS A9–A0 D31–D16 I/O15–I/O0 UCAS LCAS A9–A0 D15–D0 I/O15–I/O0 UCAS LCAS Figure 13.14 Example of DRAM Connection (64-Bit Data Width, Area 3) Rev.7.00 Oct.
Page 533: Figure 13.15 Example Of Dram Connection (32-Bit Data Width, Area 3)
Section 13 Bus State Controller (BSC) 256K × 16-bit SH7750, SH7750S, SH7750R DRAM RD/WR I/O15 I/O0 CAS3 UCAS CAS2 LCAS CAS1 CAS0 I/O15 I/O0 UCAS LCAS Figure 13.15 Example of DRAM Connection (32-Bit Data Width, Area 3) Rev.7.00 Oct. 10, 2008 Page 449 of 1074 REJ09B0366-0700...
Page 534: Figure 13.16 Example Of Dram Connection (16-Bit Data Width, Areas 2 And 3)
Section 13 Bus State Controller (BSC) 256K × 16-bit SH7750, SH7750S, SH7750R DRAM Area 3 RAS2 RD/WR I/O15 I/O0 CAS1 UCAS CAS0 LCAS CAS5 CAS4 Area 2 I/O15 I/O0 UCAS LCAS Figure 13.16 Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3) Rev.7.00 Oct.
Page 535: Table 13.15 Relationship Between Amxext And Amx2-0 Bits And Address Multiplexing
Section 13 Bus State Controller (BSC) Address Multiplexing: When area 2 or area 3 is designated as DRAM space, address multiplexing is always performed in accesses to DRAM. This enables DRAM, which requires row and column address multiplexing, to be connected to this LSI without using an external address multiplexer circuit.
Page 536: Figure 13.17 Basic Dram Access Timing
Section 13 Bus State Controller (BSC) Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in figure 13.17. Tpc is the precharge cycle, Tr the RAS assert cycle, Tc1 the CAS assert cycle, and Tc2 the read data latch cycle.
Page 537: Figure 13.18 Dram Wait State Timing
Section 13 Bus State Controller (BSC) Wait State Control: As the clock frequency increases, it becomes impossible to complete all states in one cycle as in basic access. Therefore, provision is made for state extension by using the setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in figure 13.18.
Page 538: Figure 13.19 Dram Burst Access Timing
Section 13 Bus State Controller (BSC) Burst Access: In addition to the normal DRAM access mode in which a row address is output in each data access, a fast page mode is also provided for the case where consecutive accesses are made to the same row.
Page 539: Figure 13.20 Dram Bus Cycle (Edo Mode, Rcd = 0, Anw = 0, Tpc = 1)
Section 13 Bus State Controller (BSC) EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only while the CAS signal is asserted in a data read cycle, an EDO (extended data out) mode is also provided in which, once the CAS signal is asserted while the RAS signal is asserted, even if the CAS signal is negated, data is output to the data bus until the CAS signal is next asserted.
Page 540: Figure 13.21 Burst Access Timing In Dram Edo Mode
Section 13 Bus State Controller (BSC) CKIO A25–A0 RD/WR D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.21 Burst Access Timing in DRAM EDO Mode RAS Down Mode: This LSI has an address comparator for detecting row address matches in burst mode.
Page 541: Figure 13.22 (1) Dram Burst Bus Cycle, Ras Down Mode Start (Fast Page Mode, Rcd = 0, Anw = 0)
Section 13 Bus State Controller (BSC) CKIO A25–A0 RD/WR D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start (Fast Page Mode, RCD = 0, AnW = 0) Rev.7.00 Oct.
Page 542: Figure 13.22 (2) Dram Burst Bus Cycle, Ras Down Mode Continuation (Fast Page Mode, Rcd = 0, Anw = 0)
Section 13 Bus State Controller (BSC) Tnop CKIO A25–A0 RD/WR End of RAS down mode CASn D63–D0 (read) D63–D0 (write) DACKn (SA: IO ← memory) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation (Fast Page Mode, RCD = 0, AnW = 0) Rev.7.00 Oct.
Page 543: Figure 13.22 (3) Dram Burst Bus Cycle, Ras Down Mode Start (Edo Mode, Rcd = 0, Anw = 0)
Section 13 Bus State Controller (BSC) CKIO A25–A0 RD/WR D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start (EDO Mode, RCD = 0, AnW = 0) Rev.7.00 Oct.
Page 544: Figure 13.22 (4) Dram Burst Bus Cycle, Ras Down Mode Continuation (Edo Mode, Rcd = 0, Anw = 0)
Section 13 Bus State Controller (BSC) CKIO A25–A0 RD/WR End of RAS down mode D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation (EDO Mode, RCD = 0, AnW = 0) Rev.7.00 Oct.
Page 545: Figure 13.23 Cas-Before-Ras Refresh Operation
Section 13 Bus State Controller (BSC) Refresh Timing: The bus state controller includes a function for controlling DRAM refreshing. Distributed refreshing using a CAS-before-RAS cycle can be performed for DRAM by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. Self-refresh mode is also supported. •...
Page 546: Figure 13.24 Dram Cas-Before-Ras Refresh Cycle Timing (Tras = 0, Trc = 1)
Section 13 Bus State Controller (BSC) Figure 13.24 shows the timing of the CAS-before-RAS refresh cycle. The number of RAS assert cycles in the refresh cycle is specified by bits TRAS2–TRAS0 in MCR. The specification of the RAS precharge time in the refresh cycle is determined by the setting of bits TRC2–TRC0 in MCR.
Page 547 Section 13 Bus State Controller (BSC) • Self-Refresh The self-refreshing supported by this LSI is shown in figure 13.25. After the self-refresh is cleared, the refresh controller immediately generates a refresh request. The RAS precharge time immediately after the end of the self-refreshing can be set by bits TRC2–TRC0 in MCR.
Page 548: Figure 13.25 Dram Self-Refresh Cycle Timing
Section 13 Bus State Controller (BSC) TRr1 TRr2 TRr3 TRr4 TRr5 CKIO A25–A0 RD/WR D63–D0 Figure 13.25 DRAM Self-Refresh Cycle Timing Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time (at least 100 μs or 200 μs) during which no access can be performed be provided, followed by at least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles.
Page 549: Synchronous Dram Interface
Section 13 Bus State Controller (BSC) 13.3.5 Synchronous DRAM Interface Connection of Synchronous DRAM: Since synchronous DRAM can be selected by the CS signal, it can be connected to physical space areas 2 and 3 using RAS and other control signals in common.
Page 550: Figure 13.26 Example Of 64-Bit Data Width Synchronous Dram Connection (Area 3)
Section 13 Bus State Controller (BSC) Byte specification is performed by DQM0 to DQM7. A read/write is performed for the byte for which the corresponding DQM signal is low. When the bus width is 64 bits, in big-endian mode DQM7 specifies an access to address 8n, and DQM0 specifies an access to address 8n + 7. In little-endian mode, DQM7 specifies an access to address 8n + 7, and DQM0 specifies an access to address 8n.
Page 551: Figure 13.27 Example Of 32-Bit Data Width Synchronous Dram Connection (Area 3)
Section 13 Bus State Controller (BSC) 512K × 16-bit × 2-bank SH7750, SH7750S, SH7750R synchronous DRAM A11–A2 A9–A0 CKIO CASS RD/WR D31–D16 I/O15–I/O0 DQM3 DQMU DQM2 DQML A9–A0 I/O15–I/O0 D15–D0 DQM1 DQMU DQML DQM0 Figure 13.27 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) Address Multiplexing: Synchronous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2–...
Page 552: Table 13.16 Example Of Correspondence Between This Lsi And Synchronous Dram Address Pins (64-Bit Bus Width, Amx2-Amx0 = 011, Amxext = 0)
Section 13 Bus State Controller (BSC) Table 13.16 Example of Correspondence between this LSI and Synchronous DRAM Address Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0) LSI Address Pin Synchronous DRAM Address Pin RAS Cycle CAS Cycle Function BANK select bank address Address precharge setting —...
Page 553: Figure 13.28 Basic Timing For Synchronous Dram Burst Read
Section 13 Bus State Controller (BSC) command output cycle Tc1 to the first read data latch cycle, Td1, can be specified as 1 to 5 cycles independently for areas 2 and 3 by means of bits A2W2–A2W0 and A3W2–A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles.
Page 554 Section 13 Bus State Controller (BSC) In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the start of the bus cycle. The access sequence is as follows: in a fill operation in the event of a cache miss, 64-bit boundary data including the missed data is read first, then 32-byte boundary data including the missed data is read in wraparound mode.
Page 555: Figure 13.29 Basic Timing For Synchronous Dram Single Read
Section 13 Bus State Controller (BSC) Tc3 Tc4/Td1 Td2 CKIO Bank Precharge-sel Address RD/WR CASS DQMn D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.29 Basic Timing for Synchronous DRAM Single Read Rev.7.00 Oct.
Page 556 Section 13 Bus State Controller (BSC) Burst Write: The timing chart for a burst write is shown in figure 13.30. In this LSI, a burst write occurs only in the event of cache copy-back or a 32-byte transfer by the DMAC. In a burst write operation, the WRITA command is issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output.
Page 557: Figure 13.30 Basic Timing For Synchronous Dram Burst Write
Section 13 Bus State Controller (BSC) Trwl Trwl CKIO Bank Precharge-sel Address RD/WR CASS DQMn D63–D0 (read) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.30 Basic Timing for Synchronous DRAM Burst Write Single Write: The basic timing chart for write access is shown in figure 13.31.
Page 558: Figure 13.31 Basic Timing For Synchronous Dram Single Write
Section 13 Bus State Controller (BSC) interval. The number of Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. DACK is asserted two cycles before the data write cycle. As this LSI supports burst read/burst write operations for synchronous DRAM, there are empty cycles in a single write operation.
Page 559 Section 13 Bus State Controller (BSC) RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends.
Page 560: Figure 13.32 Burst Read Timing
Section 13 Bus State Controller (BSC) different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 13.34 or 13.37 is executed instead of that in figure 13.33 or 13.36.
Page 561: Figure 13.33 Burst Read Timing (Ras Down, Same Row Address)
Section 13 Bus State Controller (BSC) Tc3 Tc4/Td1 CKIO Bank Precharge-sel Address RD/WR CASS DQMn D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.33 Burst Read Timing (RAS Down, Same Row Address) Rev.7.00 Oct.
Page 562: Figure 13.34 Burst Read Timing (Ras Down, Different Row Addresses)
Section 13 Bus State Controller (BSC) Tc4/Td1 CKIO Bank Precharge-sel Address RD/WR CASS DQMn D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses) Rev.7.00 Oct.
Page 563: Figure 13.35 Burst Write Timing
Section 13 Bus State Controller (BSC) Trwl Trwl CKIO Bank Precharge-sel Address RD/WR CASS DQMn D63–D0 (read) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.35 Burst Write Timing Rev.7.00 Oct.
Page 564: Figure 13.36 Burst Write Timing (Same Row Address)
Section 13 Bus State Controller (BSC) Tncp Tnop Trwl Trwl CKIO Bank Precharge-sel Address RD/WR CASS DQMn D63–D0 (read) Single-address DMA DACKn (SA: IO → memory) Normal write Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the solid line.
Page 565: Figure 13.37 Burst Write Timing (Different Row Addresses)
Section 13 Bus State Controller (BSC) Trwl Trwl Trwl CKIO Bank Precharge-sel Address RD/WR CASS DQMn D63–D0 (read) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.37 Burst Write Timing (Different Row Addresses) Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the DMAC, to provide faster access to synchronous DRAM.
Page 566 Section 13 Bus State Controller (BSC) When a read access is followed by another read access to the same row address, after a READ command has been issued, another READ command is issued before the end of the data latch cycle, so that there is read data on the data bus continuously.
Page 567: Figure 13.38 Burst Read Cycle For Different Bank And Row Address Following Preceding
Section 13 Bus State Controller (BSC) Tc1_A Tc1_B CKIO Bank Precharge-sel Address RD/WR CASS DQMn D63–D0 (read) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.38 Burst Read Cycle for Different Bank and Row Address Following Preceding Burst Read Cycle Rev.7.00 Oct.
Page 568: Table 13.17 Cycles For Which Pipeline Access Is Possible
Section 13 Bus State Controller (BSC) Table 13.17 Cycles for which Pipeline Access is Possible Succeeding Access DMAC Dual DMAC Single Preceding Access Read Write Read Write Read Write Read Write DMAC dual Read Write DMAC single Read Write Legend: O: Pipeline access possible X: Pipeline access not possible Refreshing: The bus state controller is provided with a function for controlling synchronous...
Page 569: Figure 13.39 Auto-Refresh Operation
Section 13 Bus State Controller (BSC) When both areas 2 and 3 are set to the synchronous DRAM, auto-refreshing of area 2 is performed subsequent to area 3. RTCNT cleared to 0 when RTCNT value RTCNT = RTCOR RTCOR-1 H'00000000 Time ≠...
Page 570: Figure 13.40 Synchronous Dram Auto-Refresh Timing
Section 13 Bus State Controller (BSC) TRr1 TRr2 TRr3 TRr4 TRrw TRr5 CKIO RD/WR CASS DQMn D63–D0 Figure 13.40 Synchronous DRAM Auto-Refresh Timing • Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM.
Page 571: Figure 13.41 Synchronous Dram Self-Refresh Timing
Section 13 Bus State Controller (BSC) In the case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the case of a manual reset.
Page 572 Section 13 Bus State Controller (BSC) • Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus cycles generated because the data bus width is smaller than the access size (for example, when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back, and also between read and write cycles during execution of a TAS...
Page 573 Section 13 Bus State Controller (BSC) Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the RAS, CAS, and RD/WR signals.
Page 574: Figure 13.42 (1) Synchronous Dram Mode Write Timing (Pall)
Section 13 Bus State Controller (BSC) value to set a short refresh request generation interval just while these dummy cycles are being executed. With simple read or write access, the address counter in the synchronous DRAM used for auto-refreshing is not initialized, and so the cycle must always be an auto-refresh cycle. After auto-refreshing has been executed at least the prescribed number of times, a mode register setting command is issued in the TMw1 cycle by setting MCR.MRSET to 1 and performing a write to address H'FF900000 + X or H'FF940000 + X.
Page 575: Figure 13.42 (2) Synchronous Dram Mode Write Timing (Mode Register Set)
Section 13 Bus State Controller (BSC) TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5 CKIO Bank Precharge-sel Address RD/WR CASS D63–D0 (High) Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set) Notes on Changing the Burst Length (SH7750R Only): In the SH7750R, when synchronous DRAM is connected with a 32-bit memory bus, the burst length can be selected as either 4 or 8 by the setting of the SDBL bit of the BCR3 register.
Page 576: Figure 13.43 Basic Timing Of Synchronous Dram Burst Read (Burst Length = 4)
Section 13 Bus State Controller (BSC) • Burst Read Figure 13.43 is the timing chart of a burst-read operation with a burst length of 4. Following the Tr cycle, during which an ACTV command is output, a READ command is issued during cycle Tc1, and a READA command is issued four cycles later.
Page 577 Section 13 Bus State Controller (BSC) In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the beginning of each data transfer cycle that is in response to a READ or READA command. Data are accessed in the following sequence: in the fill operation for a cache miss, the data between 64-bit boundaries that include the missing data are first read by the initial READ command;...
Page 578: Figure 13.44 Basic Timing Of A Burst Write To Synchronous Dram
Section 13 Bus State Controller (BSC) Trw1 Trw1 CKIO Bank Precharge-sel Address RD/WR CASS DQMn D31–D0 (read) DACKn (SA: IO → memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.44 Basic Timing of a Burst Write to Synchronous DRAM Connecting a 128-Mbit/256-Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R Only): It is possible to connect 128-Mbit or 256-Mbit synchronous DRAMs with 64-bit bus width to the SH7750R.
Page 579: Figure 13.45 Example Of The Connection Of Synchronous Dram With 64-Bit Bus Width
Section 13 Bus State Controller (BSC) cycles. The interval cycle number between the second REF command and the next ACTV command issuance is specified by the settings of both the TRAS2–TRAS0 bits and the TRC2– TRC0 bits in MCR in the sum total, which is 4 to 32 CKIO cycles. Set RTCOR and bits CKS2–CKS0, and MCR so as to satisfy the refresh-interval rating of the synchronous DRAM which you are using.
Page 580: Figure 13.46 Synchronous Dram Auto-Refresh Timing With 64-Bit Bus Width (Tras[2:0] = 001, Trc[2:0] = 001)
Section 13 Bus State Controller (BSC) TRr1 TRr2 TRr3 TRr4 TRrw* TRr1 TRr2 TRr3 TRr4 TRrw* TRr5 Trc* Trc* Trc* CKIO RD/WR CASS DQMn D63−D0 MCR.TRAS[2:0] MCR.TRAS[2:0] and MCR.TRC[2:0] Notes: 1. The interval cycle number between the first and second REF commands is 4 + TRrw × m (m = 0 to 7) CKIO cycles by the setting of the TRAS[2:0] bits.
Page 581: Burst Rom Interface
Section 13 Bus State Controller (BSC) 13.3.6 Burst ROM Interface Setting bits A0BST2–A0BST0, A5BST2–A5BST0, and A6BST2–A6BST0 in BCR1 to a non- zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a burst access function. The timing for burst access to burst ROM is shown in figure 13.47.
Page 582: Figure 13.47 Burst Rom Basic Access Timing
Section 13 Bus State Controller (BSC) CKIO A25–A5 A4–A0 RD/WR D63–D0 (read) DACKn (SA: IO ← memory) Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed. 2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.47 Burst ROM Basic Access Timing Rev.7.00 Oct.
Page 583: Figure 13.48 Burst Rom Wait Access Timing
Section 13 Bus State Controller (BSC) CKIO A25–A5 A4–A0 RD/WR D63–D0 (read) DACKn (SA: IO ← memory) Notes: 1. For a write cycle, a basic bus cycle (write cycle) is performed. 2. For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.48 Burst ROM Wait Access Timing Rev.7.00 Oct.
Page 584: Pcmcia Interface
Section 13 Bus State Controller (BSC) CKIO A25–A5 A4–A0 RD/WR D63–D0 (read) DACKn (SA: IO ← memory) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.49 Burst ROM Wait Access Timing 13.3.7 PCMCIA Interface In this LSI, setting the A56PCM bit in BCR1 to 1 makes the bus interface for external memory...
Page 585 Section 13 Bus State Controller (BSC) The setting for wait cycles during a bus access can also be made in MMU page units. When the TC bit to be accessed is cleared to 0, bits A5W2 to A5W0 in wait control register 2 (WCR2), and bits A5PCW1 and A5PCW0, A5TED2 to A5TED0, and A5TEH2 to A5TEH0 in the PCMCIA control register (PCR), are selected.
Page 586: Table 13.18 Relationship Between Address And Ce When Using Pcmcia Interface
Section 13 Bus State Controller (BSC) In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed on the data at the 32-byte boundary.
Page 587 Section 13 Bus State Controller (BSC) Access Width Size Read/ Odd/ (Bits) * (Bits) Write Even IOIS16 Access CE2 D15–D8 D7–D0 Dynamic Read Even — Invalid Read data — Read data Invalid sizing * Even — Upper read data Lower read data —...
Page 588: Figure 13.50 Example Of Pcmcia Interface
Section 13 Bus State Controller (BSC) A25–A0 A25–A0 D15–D0 D7–D0 RD/WR CE1B/(CS6) D15–D0 CE1A/(CS5) CE2B PC card CE2A D15–D8 (memory I/O) SH7750 SH7750S SH7750R WE/PGM ICIORD (IORD) (IOWR) ICIOWR WAIT IOIS16 (IOIS16) Card detection CD1, CD2 circuit Output A25–A0 Port D7–D0 D15–D0 D15–D8...
Page 589: Figure 13.51 Basic Timing For Pcmcia Memory Card Interface
Section 13 Bus State Controller (BSC) Memory Card Interface Basic Timing: Figure 13.51 shows the basic timing for the PCMCIA IC memory card interface, and figure 13.52 shows the PCMCIA memory card interface wait timing. Tpcm1 Tpcm2 CKIO A25–A0 CExx RD/WR (read) D15–D0...
Page 590: Figure 13.52 Wait Timing For Pcmcia Memory Card Interface
Section 13 Bus State Controller (BSC) Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25–A0 CExx RD/WR (read) D15–D0 (read) (write) D15–D0 (write) DACKn (DA) Notes: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. * SH7750S, SH7750R only Figure 13.52 Wait Timing for PCMCIA Memory Card Interface Rev.7.00 Oct.
Page 591: Figure 13.53 Pcmcia Space Allocation
Section 13 Bus State Controller (BSC) Common memory (64 MB) Virtual Access address space by CS5 wait Physical I/O controller addresses 1 KB IO 1 Virtual Access page address space by CS6 wait IO 1 controller Common IO 2 memory 1 Common Card 1 memory 2...
Page 592: Figure 13.54 Basic Timing For Pcmcia I/O Card Interface
Section 13 Bus State Controller (BSC) Tpci1 Tpci2 CKIO A25–A0 CExx RD/WR ICIORD (read) D15–D0 (read) ICIOWR (write) D15–D0 (write) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.54 Basic Timing for PCMCIA I/O Card Interface Rev.7.00 Oct.
Page 593: Figure 13.55 Wait Timing For Pcmcia I/O Card Interface
Section 13 Bus State Controller (BSC) Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25–A0 CExx RD/WR ICIORD (read) D15–D0 (read) ICIOWR (write) D15–D0 (write) IOIS16 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.55 Wait Timing for PCMCIA I/O Card Interface Rev.7.00 Oct.
Page 594: Figure 13.56 Dynamic Bus Sizing Timing For Pcmcia I/O Card Interface
Section 13 Bus State Controller (BSC) Tpci2 Tpci2w Tpci0 Tpci Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci1w CKIO A25–A1 CExx REG (WE7) RD/WR IORD (WE2) (read) D15–D0 (read) IOWR (WE3) (write) D15–D0 (write) IOIS16 DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.56 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.7.00 Oct.
Page 595: Mpx Interface
Section 13 Bus State Controller (BSC) 13.3.8 MPX Interface If the MD6 pin is set to 0 in a power-on reset by the RESET pin, the MPX interface for normal memory is selected for area 0. The MPX interface is selected for areas 1 to 6 by means of the MPX bit in BCR1 and the MEMMODE, A4MPX, and AIMPX bits in BCR3.
Page 596: Figure 13.57 Example Of 64-Bit Data Width Mpx Connection
Section 13 Bus State Controller (BSC) MPX device SH7750, SH7750S, SH7750R CKIO RD/FRAME FRAME RD/WR D63–D0 I/O63–I/O0 Figure 13.57 Example of 64-Bit Data Width MPX Connection The MPX interface timing is shown below. When the MPX interface is used for areas 1 to 6, a bus size of 32 or 64 bits should be specified in BCR2.
Page 597: Figure 13.58 Mpx Interface Timing 1
Section 13 Bus State Controller (BSC) Tmd1w Tmd1 CKIO RD/FRAME D63–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.58 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits) Rev.7.00 Oct.
Page 598: Figure 13.59 Mpx Interface Timing 2
Section 13 Bus State Controller (BSC) Tmd1w Tmd1w Tmd1 CKIO RD/FRAME D63–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.59 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted, Bus Width: 64 Bits) Rev.7.00 Oct.
Page 599: Figure 13.60 Mpx Interface Timing 3
Section 13 Bus State Controller (BSC) Tmd1 CKIO RD/FRAME D63–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.60 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits) Rev.7.00 Oct.
Page 600: Figure 13.61 Mpx Interface Timing 4
Section 13 Bus State Controller (BSC) Tmd1w Tmd1w Tmd1 CKIO RD/FRAME D63–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.61 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted, Bus Width: 64 Bits) Rev.7.00 Oct.
Page 601: Figure 13.62 Mpx Interface Timing 5
Section 13 Bus State Controller (BSC) Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 CKIO RD/FRAME D63–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the Figure 13.62 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct.
Page 602: Figure 13.63 Mpx Interface Timing 6
Section 13 Bus State Controller (BSC) Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO RD/FRAME D63–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.63 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct.
Page 603: Figure 13.64 Mpx Interface Timing 7
Section 13 Bus State Controller (BSC) Tmd1 Tmd2 Tmd3 Tmd4 CKIO RD/FRAME D63–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.64 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct.
Page 604: Figure 13.65 Mpx Interface Timing 8
Section 13 Bus State Controller (BSC) Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 CKIO RD/FRAME D63–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.65 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 64 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct.
Page 605: Figure 13.66 Mpx Interface Timing 9
Section 13 Bus State Controller (BSC) Tmd1w Tmd1 Tmd2 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.66 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.7.00 Oct.
Page 606: Figure 13.67 Mpx Interface Timing 10
Section 13 Bus State Controller (BSC) Tmd1w Tmd1w Tmd1 Tmd2 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.67 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.7.00 Oct.
Page 607: Figure 13.68 Mpx Interface Timing 11
Section 13 Bus State Controller (BSC) Tmd1 Tmd2 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.68 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.7.00 Oct.
Page 608: Figure 13.69 Mpx Interface Timing 12
Section 13 Bus State Controller (BSC) Tmd1w Tmd1w Tmd1 Tmd2 CKIO RD/FRAME D31–D0 RD/WR DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.69 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits, Transfer Data Size: 64 Bits) Rev.7.00 Oct.
Page 609: Figure 13.70 Mpx Interface Timing
Section 13 Bus State Controller (BSC) Figure 13.70 MPX Interface Timing 13 (Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 525 of 1074 REJ09B0366-0700...
Page 610: Figure 13.71 Mpx Interface Timing 14 (Burst Read Cycle, Anw = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)
Section 13 Bus State Controller (BSC) Figure 13.71 MPX Interface Timing 14 (Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 526 of 1074 REJ09B0366-0700...
Page 611: Figure 13.72 Mpx Interface Timing 15 (Burst Write Cycle, Anw = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)
Section 13 Bus State Controller (BSC) Figure 13.72 MPX Interface Timing 15 (Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 527 of 1074 REJ09B0366-0700...
Page 612: Figure 13.73 Mpx Interface Timing 16 (Burst Write Cycle, Anw = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)
Section 13 Bus State Controller (BSC) Figure 13.73 MPX Interface Timing 16 (Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits, Transfer Data Size: 32 Bytes) Rev.7.00 Oct. 10, 2008 Page 528 of 1074 REJ09B0366-0700...
Page 613: Byte Control Sram Interface
Section 13 Bus State Controller (BSC) 13.3.9 Byte Control SRAM Interface The byte control SRAM interface is a memory interface that outputs a byte select strobe (WEn) in both read and write bus cycles. It has 16 bit data pins, and can be connected to SRAM which has an upper byte select strobe and lower byte select strobe function such as UB and LB.
Page 614: Figure 13.74 Example Of 64-Bit Data Width Byte Control Sram
Section 13 Bus State Controller (BSC) 64K × 16-bit SH7750, SH7750S, SH7750R SRAM A18–A3 A15–A0 RD/WR I/O15–I/O0 D63–D48 A15–A0 D47–D32 I/O15–I/O0 A15–A0 D31–D16 I/O15–I/O0 A15–A0 D15–D0 I/O15–I/O0 Figure 13.74 Example of 64-Bit Data Width Byte Control SRAM Rev.7.00 Oct. 10, 2008 Page 530 of 1074 REJ09B0366-0700...
Page 615: Figure 13.75 Byte Control Sram Basic Read Cycle (No Wait)
Section 13 Bus State Controller (BSC) CKIO A25–A0 RD/WR D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.75 Byte Control SRAM Basic Read Cycle (No Wait) Rev.7.00 Oct.
Page 616: Figure 13.76 Byte Control Sram Basic Read Cycle (One Internal Wait Cycle)
Section 13 Bus State Controller (BSC) CKIO A25–A0 RD/WR D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.76 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) Rev.7.00 Oct.
Page 617: Figure 13.77 Byte Control Sram Basic Read Cycle (One Internal Wait + One External Wait)
Section 13 Bus State Controller (BSC) CKIO A25–A0 RD/WR D63–D0 (read) DACKn (SA: IO ← memory) DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC. Figure 13.77 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait) Rev.7.00 Oct.
Page 618: 13.3.10 Waits Between Access Cycles
Section 13 Bus State Controller (BSC) 13.3.10 Waits between Access Cycles A problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and so resulting in lower reliability or incorrect operation.
Page 619: Figure 13.78 Waits Between Access Cycles
Section 13 Bus State Controller (BSC) Twait Twait CKIO A25–A0 RD/WR D31–D0 Area m space read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification Figure 13.78 Waits between Access Cycles Rev.7.00 Oct.
Page 620: 13.3.11 Bus Arbitration
Section 13 Bus State Controller (BSC) 13.3.11 Bus Arbitration This LSI is provided with a bus arbitration function that grants the bus to an external device when it makes a bus request. There are three bus arbitration modes: master mode, partial-sharing master mode, and slave mode. In master mode the bus is held on a constant basis, and is released to another device in response to a bus request.
Page 621 Section 13 Bus State Controller (BSC) memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus release is not performed between read and write cycles during execution of a TAS instruction, or between read and write cycles when DMAC dual address transfer is executed. When BREQ is negated, BACK is negated and use of the bus is resumed.
Page 622: Figure 13.79 Arbitration Sequence
Section 13 Bus State Controller (BSC) CKIO BREQ Asserted for at least 2 cycles BACK Negated within 2 cycles Hi-Z A25–A0 Hi-Z Hi-Z RD/WR Hi-Z Hi-Z Hi-Z D63–D0 (write) Hi-Z Master mode device access Must be asserted for Must be negated within 2 cycles at least 2 cycles BREQ/BSACK BACK/BSREQ...
Page 623: 13.3.12 Master Mode
Section 13 Bus State Controller (BSC) 13.3.12 Master Mode The master mode processor holds the bus itself unless it receives a bus request. On receiving an assertion (low level) of the bus request signal (BREQ) from off-chip, the master mode processor releases the bus and asserts (drives low) the bus use permission signal (BACK) as soon as the currently executing bus cycle ends.
Page 624: 13.3.13 Slave Mode
Section 13 Bus State Controller (BSC) If a refresh request is generated when BACK has been asserted and the bus has been released, the BACK signal is negated even while the BREQ signal is asserted to request the slave to relinquish the bus.
Page 625: 13.3.14 Partial-Sharing Master Mode
Section 13 Bus State Controller (BSC) 13.3.14 Partial-Sharing Master Mode In partial-sharing master mode, area 2 only is shared with other devices, and other areas can be accessed at all times. Partial-sharing master mode can be set by setting master mode with the external mode pins, and setting the PSHR bit to 1 in BCR1 in the initialization procedure in a power-on reset.
Page 626: 13.3.15 Cooperation Between Master And Slave
Section 13 Bus State Controller (BSC) Do not use DRAM/synchronous DRAM RAS down mode in partial-sharing master mode. Area 2 synchronous DRAM mode register settings should be made by the master mode device. Set partial-sharing master mode (by setting the PSHR bit to 1 in BCR1) after completion of the area 3 synchronous DRAM mode register settings.
Page 627: 13.3.16 Notes On Usage
Section 13 Bus State Controller (BSC) 13.3.16 Notes on Usage Refresh: Auto refresh operations stop when a transition is made to standby mode, hardware standby mode or deep-sleep mode. If the memory system requires refresh operations, set the memory in the self-refresh state prior to making the transition to standby mode, hardware standby mode or deep-sleep mode.
Page 628 Section 13 Bus State Controller (BSC) Conditions Under which Problem Occurs a. The partial-sharing master mode is selected (BCR1.PSHR = 1). b. Refresh is enabled for area 3 (BCR1.DRAMTP[2:0] = 010, 011, or 101; MCR.RFSH = 1; MCR.RMODE = 0). c.
Page 629: Section 14 Direct Memory Access Controller (Dmac)
Section 14 Direct Memory Access Controller (DMAC) Section 14 Direct Memory Access Controller (DMAC) 14.1 Overview The SH7750 and SH7750S include an on-chip four-channel direct memory access controller (DMAC). The SH7750R includes an on-chip eight-channel DMAC. The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (TMU, SCI, SCIF), external memories, memory-mapped external devices, and on-chip peripheral modules (except the DMAC, BSC, and UBC).
Page 630 Section 14 Direct Memory Access Controller (DMAC) • An interrupt request can be sent to the CPU on completion of the specified number of transfers. • Transfer requests: The following three DMAC transfer activation requests are supported. ⎯ External request (1) Normal DMA mode From two DREQ pins.
Page 631: Block Diagram (Sh7750, Sh7750S)
Section 14 Direct Memory Access Controller (DMAC) • Channel 2: Dual address mode only. • Channel 3: Dual address mode only. • Channel 4 (SH7750R only): Dual address mode only. • Channel 5 (SH7750R only): Dual address mode only. • Channel 6 (SH7750R only): Dual address mode only.
Page 632: Figure 14.1 Block Diagram Of Dmac
Section 14 Direct Memory Access Controller (DMAC) DMAC module Count SARn control Register DARn control DMATCRn Activation On-chip control peripheral CHCRn module DMAOR Request priority SCI, SCIF control DACK0, DACK1 DRAK0, DRAK1 interface SAR0, DAR0, DMATCR0, CHCR0 only Request DDT module DREQ0, DREQ1 DTR command buffer BAVL...
Page 633: Pin Configuration (Sh7750, Sh7750S)
Section 14 Direct Memory Access Controller (DMAC) 14.1.3 Pin Configuration (SH7750, SH7750S) Tables 14.1 and 14.2 show the DMAC pins. Table 14.1 DMAC Pins Channel Pin Name Abbreviation Function DREQ0 DMA transfer Input DMA transfer request input from request external device to channel 0 DREQ acceptance DRAK0 Output...
Page 634: Register Configuration (Sh7750, Sh7750S)
Section 14 Direct Memory Access Controller (DMAC) Table 14.2 DMAC Pins in DDT Mode Pin Name Abbreviation Function DBREQ Data bus request Input Data bus release request from external (DREQ0) device for DTR format input BAVL Data bus available Output Data bus release notification (DRAK0) Data bus can be used 2 cycles after...
Page 635 Section 14 Direct Memory Access Controller (DMAC) Chan- Abbre- Read/ Area 7 Access Name viation Write Initial Value P4 Address Address Size DMA source Undefined H'FFA00010 H'1FA00010 32 SAR1 address register 1 DMA destination Undefined H'FFA00014 H'1FA00014 32 DAR1 address register 1 DMA transfer DMATCR1 R/W Undefined...
Page 636: Register Descriptions (Sh7750, Sh7750S)
Section 14 Direct Memory Access Controller (DMAC) 14.2 Register Descriptions (SH7750, SH7750S) 14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) Bit: Initial value: — — — — — — — — R/W: Bit: · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Initial value: —...
Page 637: Dma Destination Address Registers 0-3 (Dar0-Dar3)
Section 14 Direct Memory Access Controller (DMAC) 14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) Bit: Initial value: — — — — — — — — R/W: Bit: · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Initial value: —...
Page 638: Dma Transfer Count Registers 0-3 (Dmatcr0-Dmatcr3)
Section 14 Direct Memory Access Controller (DMAC) 14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3) Bit: Initial value: R/W: Bit: Initial value: — — — — — — — — R/W: Bit: Initial value: — — — — — — — —...
Page 639: Dma Channel Control Registers 0-3 (Chcr0-Chcr3)
Section 14 Direct Memory Access Controller (DMAC) 14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) Bit: SSA2 SSA1 SSA0 DSA2 DSA1 DSA0 Initial value: R/W: Bit: — — — — Initial value: R/W: (R/W) (R/W) Bit: Initial value: R/W: Bit: — Initial value: R/W: R/(W)
Page 640 Section 14 Direct Memory Access Controller (DMAC) These registers are initialized to H'00000000 by a power-on or manual reset. They retain their values in standby mode and deep sleep mode. Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify the space attribute for access to a PCMCIA interface area.
Page 641 Section 14 Direct Memory Access Controller (DMAC) Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits specify the space attribute for access to a PCMCIA interface area. Bit 27: DSA2 Bit 26: DSA1 Bit 25: DSA0 Description Reserved in PCMCIA access (Initial value) Dynamic bus sizing I/O space 8-bit I/O space...
Page 642 Section 14 Direct Memory Access Controller (DMAC) Bit 19—DREQ Select (DS): Specifies either low level detection or falling edge detection as the sampling method for the DREQ pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR3.
Page 643 Section 14 Direct Memory Access Controller (DMAC) Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or active-low. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, this bit is invalid. Bit 16: AL Description Active-high output...
Page 644 Section 14 Direct Memory Access Controller (DMAC) Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify incrementing/decrementing of the DMA transfer source address. The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode.
Page 645 Section 14 Direct Memory Access Controller (DMAC) Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source. Bit 11: Bit 10: Bit 9: Bit 8: Description External request, dual address mode * (external address space →...
Page 646 Section 14 Direct Memory Access Controller (DMAC) [SH7750] An external request specification should be set for channels 1 to 3. For channel 0, only single address mode can be set with the DTR format. [SH7750S] An external request specification can be set for channels 0 to 3. Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer.
Page 647 Section 14 Direct Memory Access Controller (DMAC) Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1.
Page 648: Dma Operation Register (Dmaor)
Section 14 Direct Memory Access Controller (DMAC) 14.2.5 DMA Operation Register (DMAOR) Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — — — — Initial value: R/W: Bit: — — — —...
Page 649 Section 14 Direct Memory Access Controller (DMAC) Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. Bit 15: DDT Description Normal DMA mode (Initial value) On-demand data transfer mode Note: BAVL (DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1, the BAVL pin function is enabled and this pin becomes an active-low output.
Page 650 Section 14 Direct Memory Access Controller (DMAC) interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be cleared by writing 0 after reading 1. Bit 2: AE Description No address error, DMA transfer enabled (Initial value) [Clearing condition] When 0 is written to AE after reading AE = 1...
Page 651: Operation
Section 14 Direct Memory Access Controller (DMAC) 14.3 Operation When a DMA transfer request is issued, the DMAC starts the transfer according to the predetermined channel priority order. It ends the transfer when the transfer end conditions are satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request.
Page 652: Figure 14.2 Dmac Transfer Flowchart
Section 14 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1? Illegal address check (reflected in AE bit) NMIF, AE, TE = 0? Transfer request issued? Bus mode, transfer request mode, DREQ detection method Transfer (1 transfer unit) DMATCR - 1 →...
Page 653: Dma Transfer Requests
Section 14 Direct Memory Access Controller (DMAC) 14.3.2 DMA Transfer Requests DMA transfer requests are basically generated at either the data transfer source or destination, but they can also be issued by external devices or on-chip peripheral modules that are neither the source nor the destination.
Page 654: Table 14.4 Selecting External Request Mode With Rs Bits
Section 14 Direct Memory Access Controller (DMAC) Table 14.4 Selecting External Request Mode with RS Bits Address Mode Transfer Source Transfer Destination Dual address External memory External memory mode or memory-mapped or memory-mapped external device, or external device, or external device with external device with DACK DACK...
Page 655 Section 14 Direct Memory Access Controller (DMAC) • Usage Notes An external request (DREQ) is detected by a low level or falling edge. Ensure that the external request (DREQ) signal is held high when there is no DMA transfer request from an external device after a power-on reset or manual reset.
Page 656: Table 14.5 Selecting On-Chip Peripheral Module Request Mode With Rs Bits
Section 14 Direct Memory Access Controller (DMAC) Table 14.5 Selecting On-Chip Peripheral Module Request Mode with RS Bits DMAC Transfer DMAC Transfer Transfer Transfer RS3 RS2 RS1 RS0 Request Source Request Signal Source Destination Bus Mode SCI transmitter SCTDR1 (SCI External* SCTDR1 Cycle steal...
Page 657: Channel Priorities
Section 14 Direct Memory Access Controller (DMAC) When a DMA transfer corresponding to a transfer request signal from an on-chip peripheral module shown in table 14.5 is carried out, the signal is discontinued automatically. This occurs every transfer in cycle steal mode, and in the last transfer in burst mode. 14.3.3 Channel Priorities If the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel...
Page 658: Figure 14.3 Round Robin Mode
Section 14 Direct Memory Access Controller (DMAC) Transfer on channel 0 Channel 0 is given the lowest CH0 > CH1 > CH2 > CH3 Initial priority order priority. CH1 > CH2 > CH3 > CH0 Priority order after transfer Transfer on channel 1 When channel 1 is given the Initial priority order CH0 >...
Page 659: Figure 14.4 Example Of Changes In Priority Order In Round Robin Mode
Section 14 Direct Memory Access Controller (DMAC) 1. Transfer requests are issued simultaneously for channels 0 and 3. 2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3.
Page 660: Types Of Dma Transfer
Section 14 Direct Memory Access Controller (DMAC) 14.3.4 Types of DMA Transfer The DMAC supports the transfers shown in table 14.6. It can operate in single address mode, in which either the transfer source or the transfer destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output.
Page 661: Figure 14.5 Data Flow In Single Address Mode
Section 14 Direct Memory Access Controller (DMAC) Address Modes Single Address Mode: In single address mode, both the transfer source and the transfer destination are external; one is accessed by the DACK signal and the other by an address. In this mode, the DMAC performs a DMA transfer in one bus cycle by simultaneously outputting the external device strobe signal (DACK) to either the transfer source or transfer destination external device to access it, while outputting an address to the other side of the transfer.
Page 662: Figure 14.6 Dma Transfer Timing In Single Address Mode
Section 14 Direct Memory Access Controller (DMAC) CKIO Address output to external memory A28–A0 space Data output from external device D63–D0 with DACK DACK DACK signal to external device with DACK WE signal to external memory space (a) From external device with DACK to external memory space CKIO Address output to external memory A28–A0...
Page 663: Figure 14.7 Operation In Dual Address Mode
Section 14 Direct Memory Access Controller (DMAC) In dual address mode, data corresponding to the size specified by CHCRn.TS is read from the transfer source in the data read cycle, and, in the data write cycle, it is transferred in two bus cycles in order to write in the transfer destination the data corresponding to the size specified by CHCRn.TS.
Page 664: Figure 14.8 Example Of Transfer Timing In Dual Address Mode
Section 14 Direct Memory Access Controller (DMAC) CKIO Transfer source Transfer destination A26–A0 address address D63–D0 DACK Data read cycle Data write cycle (1st cycle) (2nd cycle) Transfer from external memory space to external memory space Figure 14.8 Example of Transfer Timing in Dual Address Mode Bus Modes There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0–...
Page 665: Figure 14.9 Example Of Dma Transfer In Cycle Steal Mode
Section 14 Direct Memory Access Controller (DMAC) Figure 14.9 shows an example of DMA transfer timing in cycle steal mode. The transfer conditions in this example are dual address mode and DREQ level detection. DREQ Bus returned to CPU Bus cycle DMAC DMAC DMAC...
Page 666: Table 14.7 Relationship Between Dma Transfer Type, Request Mode, And Bus Mode
Section 14 Direct Memory Access Controller (DMAC) Table 14.7 Relationship between DMA Transfer Type, Request Mode, and Bus Mode Address Request Transfer Size Usable Mode Type of Transfer Mode Mode (Bits) Channels 8/16/32/64/32B 0, 1 (2, 3) * Single External device with DACK External and external memory 8/16/32/64/32B 0, 1 (2, 3) *...
Page 667: Table 14.8 External Request Transfer Sources And Destinations In Normal Dma Mode
Section 14 Direct Memory Access Controller (DMAC) 7. See tables 14.8 and 14.9 for the transfer sources and transfer destinations in DMA transfer by means of an external request. (a) Normal DMA Mode Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request supported by this LSI in normal DMA mode.
Page 668: Table 14.9 External Request Transfer Sources And Destinations In Ddt Mode
Section 14 Direct Memory Access Controller (DMAC) Table 14.9 External Request Transfer Sources and Destinations in DDT Mode Usable Transfer Direction (Settable Memory Interface) Address DMAC Transfer Source Transfer Destination Mode Channels Synchronous DRAM * External device with DACK Single 0 to 3 External device with DACK Synchronous DRAM...
Page 669: Number Of Bus Cycle States And Dreq Pin Sampling Timing
Section 14 Direct Memory Access Controller (DMAC) DMAC CH1 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH1 DMAC channel 1 DMAC channel 0 and DMAC channel 1 burst mode channel 1 round robin burst mode mode Legend: Priority system: Round robin mode Channel 0:...
Page 670 Section 14 Direct Memory Access Controller (DMAC) Operation: Figures 14.12 to 14.22 show the timing in each mode. 1. Cycle Steal Mode In cycle steal mode, The DREQ sampling timing differs for dual address mode and single address mode, and for level detection and edge detection of DREQ. For example, in figure 14.12 (cycle steal mode, dual address mode, level detection), DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation.
Page 671 Section 14 Direct Memory Access Controller (DMAC) In the example shown in figure 14.20, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation, and the second sampling operation begins one cycle after the start of the first DMAC transfer bus cycle. In single address mode, the DACK signal is output every DMAC transfer cycle.
Page 672: Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
Section 14 Direct Memory Access Controller (DMAC) Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) Rev.7.00 Oct. 10, 2008 Page 588 of 1074 REJ09B0366-0700...
Page 673: Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/Dreq
Section 14 Direct Memory Access Controller (DMAC) Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) Rev.7.00 Oct. 10, 2008 Page 589 of 1074 REJ09B0366-0700...
Page 674 Section 14 Direct Memory Access Controller (DMAC) Figure 14.14 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection), DACK (Read Cycle) Rev.7.00 Oct. 10, 2008 Page 590 of 1074 REJ09B0366-0700...
Page 675 Section 14 Direct Memory Access Controller (DMAC) Figure 14.15 Dual Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) Rev.7.00 Oct. 10, 2008 Page 591 of 1074 REJ09B0366-0700...
Page 676 Section 14 Direct Memory Access Controller (DMAC) Figure 14.16 Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection) → External Bus Rev.7.00 Oct. 10, 2008 Page 592 of 1074 REJ09B0366-0700...
Page 677 Section 14 Direct Memory Access Controller (DMAC) Figure 14.17 Dual Address Mode/Cycle Steal Mode External Bus → On-Chip SCI (Level Detection) Rev.7.00 Oct. 10, 2008 Page 593 of 1074 REJ09B0366-0700...
Page 678 Section 14 Direct Memory Access Controller (DMAC) Figure 14.18 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Level Detection) Rev.7.00 Oct. 10, 2008 Page 594 of 1074 REJ09B0366-0700...
Page 679 Section 14 Direct Memory Access Controller (DMAC) Figure 14.19 Single Address Mode/Cycle Steal Mode External Bus → External Bus/DREQ (Edge Detection) Rev.7.00 Oct. 10, 2008 Page 595 of 1074 REJ09B0366-0700...
Page 680 Section 14 Direct Memory Access Controller (DMAC) Figure 14.20 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection) Rev.7.00 Oct. 10, 2008 Page 596 of 1074 REJ09B0366-0700...
Page 681 Section 14 Direct Memory Access Controller (DMAC) Figure 14.21 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Edge Detection) Rev.7.00 Oct. 10, 2008 Page 597 of 1074 REJ09B0366-0700...
Page 682: Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/Dreq
Section 14 Direct Memory Access Controller (DMAC) Figure 14.22 Single Address Mode/Burst Mode External Bus → External Bus/DREQ (Level Detection)/32-Byte Block Transfer (Bus Width: 64 Bits, SDRAM: Row Hit Write) Rev.7.00 Oct. 10, 2008 Page 598 of 1074 REJ09B0366-0700...
Page 683: Ending Dma Transfer
Section 14 Direct Memory Access Controller (DMAC) 14.3.6 Ending DMA Transfer The conditions for ending DMA transfer are different for ending on individual channels and for ending on all channels together. Except for the case where transfer ends when the value in the DMA transfer count register (DMATCR) reaches 0, the following conditions apply to ending transfer.
Page 684 Section 14 Direct Memory Access Controller (DMAC) Conditions for Ending Transfer on Individual Channels: Transfer ends on the corresponding channel when either of the following conditions is satisfied: • The value in the DMA transfer count register (DMATCR) reaches 0. •...
Page 685 Section 14 Direct Memory Access Controller (DMAC) 2. End of transfer when NMIF = 1 in DMAOR If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on all channels in accordance with the conditions in 1 to 4 in section 14.3.6, Ending DMA Transfer, and the bus is passed to the CPU.
Page 686: Examples Of Use
Section 14 Direct Memory Access Controller (DMAC) 14.4 Examples of Use 14.4.1 Examples of Transfer between External Memory and an External Device with DACK Examples of transfer of data in external memory to an external device with DACK using DMAC channel 1 are considered here.
Page 687: On-Demand Data Transfer Mode (Ddt Mode)
Section 14 Direct Memory Access Controller (DMAC) 14.5 On-Demand Data Transfer Mode (DDT Mode) 14.5.1 Operation Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT mode). In DDT mode, it is possible to specify direct single address mode transfer to channel 0 via the data bus and DDT module, and simultaneously issue a transfer request, using the DBREQ, BAVL, TR, TDACK, and ID [1:0] signals between an external device and the DMAC.
Page 688 Section 14 Direct Memory Access Controller (DMAC) 1. Normal data transfer mode (channel 0) BAVL (the data bus available signal) is asserted in response to DBREQ (the data bus request signal) from an external device. Two CKIO-synchronous cycles after BAVL is asserted, the external data bus drives the data transfer setting command (DTR command) in synchronization with TR (the transfer request signal).
Page 689: Pins In Ddt Mode
Section 14 Direct Memory Access Controller (DMAC) 14.5.2 Pins in DDT Mode Figure 14.24 shows the system configuration in DDT mode. DBREQ/DREQ0 BAVL/DRAK0 TR/DREQ1 TDACK/DACK0 SH7750, SH7750S, SH7750R ID1, ID0/DRAK1, DACK1 External device CKIO D63–D0=DTR A25–A0, RAS, CAS, WE, DQMn, CKE Synchronous DRAM Figure 14.24 System Configuration in On-Demand Data Transfer Mode...
Page 690: Figure 14.25 Data Transfer Request Format
Section 14 Direct Memory Access Controller (DMAC) ⎯ In the case of direct data transfer mode (valid only for channel 2), a direct transfer request can be made to channel 2 by asserting DBREQ and TR simultaneously. • TDACK: Reply strobe signal for external device from DMAC The assert timing of this signal is the same as the DACKn assert timing of the memory interfaces.
Page 691 Section 14 Direct Memory Access Controller (DMAC) Bits 63 to 61: Transmit Size (SZ2–SZ0) • 000: Byte size (8-bit) specification • 001: Word size (16-bit) specification • 010: Longword size (32-bit) specification • 011: Quadword size (64-bit) specification • 100: 32-byte block transfer specification •...
Page 692: Transfer Request Acceptance On Each Channel
Section 14 Direct Memory Access Controller (DMAC) 3. The COUNT field is ignored if MD = 00. 4. In edge-sense burst mode, DMA transfer is executed continuously. In level-sense burst mode and cycle steal mode, a handshake protocol is used to transfer each unit of data. 5.
Page 693: Figure 14.26 Single Address Mode: Synchronous Dram → External Device Longword Transfer
Section 14 Direct Memory Access Controller (DMAC) Figure 14.26 Single Address Mode: Synchronous DRAM → External Device Longword Transfer SDRAM auto-precharge Read bus cycle, burst (RCD[1:0] = 01, CAS latency = 3, TPC[2:0] = 001) Rev.7.00 Oct. 10, 2008 Page 609 of 1074 REJ09B0366-0700...
Page 694: Figure 14.27 Single Address Mode: External Device → Synchronous Dram Longword Transfer
Section 14 Direct Memory Access Controller (DMAC) Figure 14.27 Single Address Mode: External Device → Synchronous DRAM Longword Transfer SDRAM auto-precharge Write bus cycle, burst (RCD[1:0] = 01, TRWL[2:0] = 101, TPC[2:0] = 001) Rev.7.00 Oct. 10, 2008 Page 610 of 1074 REJ09B0366-0700...
Page 695: Figure 14.28 Dual Address Mode/Synchronous Dram → Sram Longword Transfer
Section 14 Direct Memory Access Controller (DMAC) Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer Rev.7.00 Oct. 10, 2008 Page 611 of 1074 REJ09B0366-0700...
Page 696: Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev.7.00 Oct. 10, 2008 Page 612 of 1074 REJ09B0366-0700...
Page 697: Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev.7.00 Oct. 10, 2008 Page 613 of 1074 REJ09B0366-0700...
Page 698: Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit
Section 14 Direct Memory Access Controller (DMAC) A25–A0 D63–D0 RAS, CAS, WE DQMn ID1, ID0 Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit Transfer/Channel 0 On-Demand Data Transfer Rev.7.00 Oct. 10, 2008 Page 614 of 1074 REJ09B0366-0700...
Page 699: Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE DQMn TDACK ID1, ID0 Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit Transfer/Channel 0 On-Demand Data Transfer Rev.7.00 Oct. 10, 2008 Page 615 of 1074 REJ09B0366-0700...
Page 700: Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer)
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 MD = 10 or 11 MD = 00 TDACK ID1, ID0 Next transfer request Start of data transfer Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) Rev.7.00 Oct.
Page 701: Figure 14.34 Handshake Protocol Without Use Of Data Bus (Channel 0 On-Demand Data Transfer)
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 MD = 10 or 11 TDACK ID1, ID0 Next transfer request Start of data transfer Figure 14.34 Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data Transfer) Rev.7.00 Oct.
Page 702: Figure 14.35 Read From Synchronous Dram Precharge Bank
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 D2 D3 RAS, CAS, Figure 14.35 Read from Synchronous DRAM Precharge Bank DBREQ Transfer requests can be accepted BAVL A25–A0 D63–D0 D2 D3 RAS, CAS, Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) Rev.7.00 Oct.
Page 703: Figure 14.37 Read From Synchronous Dram (Row Hit)
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 D2 D3 RAS, CAS, Figure 14.37 Read from Synchronous DRAM (Row Hit) DBREQ BAVL A25–A0 D63–D0 D2 D3 RAS, CAS, Figure 14.38 Write to Synchronous DRAM Precharge Bank Rev.7.00 Oct. 10, 2008 Page 619 of 1074 REJ09B0366-0700...
Page 704: Figure 14.39 Write To Synchronous Dram Non-Precharge Bank (Row Miss)
Section 14 Direct Memory Access Controller (DMAC) DBREQ Transfer requests can be accepted BAVL A25–A0 D63–D0 D2 D3 RAS, CAS, Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss) A25–A0 D63–D0 RAS, CAS, Figure 14.40 Write to Synchronous DRAM (Row Hit) Rev.7.00 Oct.
Page 705: Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte Block Transfer/Channel 0 On-Demand Data Transfer Rev.7.00 Oct. 10, 2008 Page 621 of 1074 REJ09B0366-0700...
Page 706: Figure 14.42 Ddt Mode Setting
Section 14 Direct Memory Access Controller (DMAC) DMA Operation Register (DMAOR) PR[1:0] NMIF (SH7750S) DDT: 0: Normal DMA mode 1: On-demand data transfer mode Figure 14.42 DDT Mode Setting DBREQ BAVL No DMA request sampling A25–A0 D63–D0 D1 D2 D3 D1 D2 MD = 01 TDACK ID1, ID0...
Page 707: Figure 14.44 Single Address Mode/Burst Mode/Level Detection/External Bus → External Device Data Transfer
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL Wait for next DMA request A25–A0 D63–D0 D1 D2 D3 D0 D1 D2 D3 MD = 10 TDACK ID1, ID0 Start of data transfer Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus →...
Page 708: Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus → External Device Data Transfer
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 Idle cycle Idle cycle Idle cycle MD = 01 DQMn TDACK ID1, ID0 Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Bus → External Device Data Transfer Rev.7.00 Oct.
Page 709: Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → External Bus Data Transfer
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 MD = 01 DQMn Idle cycle Idle cycle Idle cycle TDACK ID1, ID0 Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device → External Bus Data Transfer Rev.7.00 Oct.
Page 710: Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/Dma Transfer Request To Channels 1-3 Using Data Bus
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 ID = 1, 2, or 3 RAS, CAS, WE TDACK ID1, ID0 01 or 10 or 11 Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer Request to Channels 1–3 Using Data Bus Rev.7.00 Oct.
Page 711: Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/External Bus → External Device Data Transfer/Direct Data Transfer Request To Channel 2 Without Using Data Bus
Section 14 Direct Memory Access Controller (DMAC) DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 No DTR cycle, so requests can be made at any time Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus → External Device Data Transfer/ Direct Data Transfer Request to Channel 2 without Using Data Bus Rev.7.00 Oct.
Page 712: Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data
Section 14 Direct Memory Access Controller (DMAC) Four requests can be queued Handshaking is necessary to send additional requests No more requests A25–A0 D63–D0 D1 D2 RAS, CAS, WE ID1, ID0 Must be ignored (no request transmitted) Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer/Direct Data Transfer Request to Channel 2 Rev.7.00 Oct.
Page 713: Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data
Section 14 Direct Memory Access Controller (DMAC) Four requests can be queued Handshaking is necessary to send additional requests DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer/Direct Data Transfer Request to Channel 2 Rev.7.00 Oct.
Page 714: Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data
Section 14 Direct Memory Access Controller (DMAC) Handshaking is necessary Four requests can be queued to send additional requests DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 Rev.7.00 Oct.
Page 715: Notes On Use Of Ddt Module
Section 14 Direct Memory Access Controller (DMAC) Four requests can be queued Handshaking is necessary to send additional requests DBREQ BAVL A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Must be ignored (no request transmitted) Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2 14.5.4 Notes on Use of DDT Module...
Page 716 Section 14 Direct Memory Access Controller (DMAC) b. If, during execution of the handshake protocol using the data bus for channel 0, a request is input for one of channels 1 to 3, and after that DMA transfer is executed settings of DTR.ID = 00, DTR.MD = 00, and DTR, SZ ≠...
Page 717 Section 14 Direct Memory Access Controller (DMAC) 7. DTR format a. The DDT module processes DTR.ID, DTR.MD, and DTR.SZ as follows. When DTR.ID= 00 MD = 00, SZ ≠ 101, 110: Handshake protocol using the data bus • MD ≠ 00, SZ = 111: CHCR0.DE = 0 setting (DMA transfer end request) •...
Page 718: Configuration Of The Dmac (Sh7750R)
Section 14 Direct Memory Access Controller (DMAC) 11. Clearing DDT mode Check that DMA transfer is not in progress on any channel before setting the DMAOR.DDT bit. If the DMAOR.DDT setting is changed from 1 to 0 during DMA transfer in DDT mode, the DMAC will freeze.
Page 719: Figure 14.53 Block Diagram Of The Dmac
Section 14 Direct Memory Access Controller (DMAC) DMAC module Count control SARn DARn Registr control DMATCRn Activation control On-chip peripheral CHCRn module DMAOR Request SCI, SCIF priority control queclr0–7 DACK0, DACK1 interface DRAK0, DRAK1 dmaqueclr0-7 SAR0, DAR0, DMATCR0, Request CHCR0 only DDT module DREQ0, DREQ1 DTR command buffer...
Page 720: Pin Configuration (Sh7750R)
Section 14 Direct Memory Access Controller (DMAC) 14.6.2 Pin Configuration (SH7750R) Tables 14.11 and 14.12 show the pin configuration of the DMAC. Table 14.11 DMAC Pins Channel Pin Name Abbreviation Function DREQ0 DMA transfer Input DMA transfer request input from request external device to channel 0 DREQ acceptance...
Page 721: Register Configuration (Sh7750R)
Section 14 Direct Memory Access Controller (DMAC) Table 14.12 DMAC Pins in DDT Mode Pin Name Abbreviation Function DBREQ Data bus request Input Data bus release request from external (DREQ0) device for DTR format input BAVL/ID2 Data bus available Output Data bus release notification (DRAK0) Data bus can be used 2 cycles after...
Page 722: Table 14.13 Register Configuration
Section 14 Direct Memory Access Controller (DMAC) Table 14.13 Register Configuration Chan- Abbre- Read/ Area 7 Access Name viation Write Initial Value P4 Address Address Size R/W * DMA source SAR0 Undefined H'FFA00000 H'1FA00000 32 address register 0 R/W * DMA destination DAR0 Undefined...
Page 723 Section 14 Direct Memory Access Controller (DMAC) Chan- Abbre- Read/ Area 7 Access Name viation Write Initial Value P4 Address Address Size DMA source SAR4 Undefined H'FFA00050 H'1FA00050 32 address register 4 DMA destination DAR4 Undefined H'FFA00054 H'1FA00054 32 address register 4 DMA transfer DMATCR4 R/W Undefined...
Page 724: Register Descriptions (Sh7750R)
Section 14 Direct Memory Access Controller (DMAC) 2. In the SH7750R, writes from the CPU and writes from external I/O devices using the DTR format are possible in DDT mode. 14.7 Register Descriptions (SH7750R) 14.7.1 DMA Source Address Registers 0−7 (SAR0−SAR7) Bit: Initial value: —...
Page 725: Dma Transfer Count Registers 0-7 (Dmatcr0-Dmatcr7)
Section 14 Direct Memory Access Controller (DMAC) DMA destination address registers 0−7 (DAR0−DAR7) are 32-bit readable/writable registers that specify the destination address for a DMA transfer. The functions of these registers are the same as on the SH7750 and SH7750S. For more information, see section 14.2.2, DMA Destination Address Registers 0−3 (DAR0−DAR3).
Page 726 Section 14 Direct Memory Access Controller (DMAC) DMA channel control registers 0−7(CHCR0−CHCR7) are 32-bit readable/writable registers that specify the operating mode, transfer method, etc., for each channel. Bits 31−28 and 27−24 correspond to the source address and destination address, respectively; these settings are only valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA-interface space.
Page 727 Section 14 Direct Memory Access Controller (DMAC) Bit 19—DREQ Select (DS): Specifies either low level detection or falling edge detection as the sampling method for the DREQ pin used in external request mode. In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in CHCR0–CHCR7.
Page 728 Section 14 Direct Memory Access Controller (DMAC) Bits 11 to 8—Resource Select 3 to 0 (RS3–RS0): These bits specify the transfer request source. For details of the settings, see the description of the RS3−RS0 bits in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer.
Page 729: Dma Operation Register (Dmaor)
Section 14 Direct Memory Access Controller (DMAC) Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel. For details of the settings, see the description of the DE bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3). 14.7.5 DMA Operation Register (DMAOR) Bit: Initial value: R/W:...
Page 730: Figure 14.54 Dtr Format (Transfer Request Format) (Sh7750R)
Section 14 Direct Memory Access Controller (DMAC) Table 14.14 Channel Selection by DTR Format (DMAOR.DBL = 1) DTR.SZ[2:0] ≠ 101 DTR.ID[1:0] DTR.SZ[2:0] = 101 61 60 59 58 57 56 55 4847 32 31 COUNT (Reserved) ADDRESS Figure 14.54 DTR Format (Transfer Request Format) (SH7750R) Bits 13 to 10—Reserved: These bits are always read as 0, and should only be written with 0.
Page 731: Operation (Sh7750R)
Section 14 Direct Memory Access Controller (DMAC) 0 after reading 1. For details of the settings, see the description of the NMIF bit in section 14.2.5, DMA Operation Register (DMAOR) Bit 0—DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is enabled for transfer.
Page 732: Transfer Channel Notification In Ddt Mode
Section 14 Direct Memory Access Controller (DMAC) 14.8.3 Transfer Channel Notification in DDT Mode When the DMAC is set up for four-channel external request acceptance in DDT mode (DMAOR.DBL = 0), the ID [1:0] bits are used to notify the external device of the DMAC channel that is to be used.
Page 733: Clearing Request Queues By Dtr Format
Section 14 Direct Memory Access Controller (DMAC) 14.8.4 Clearing Request Queues by DTR Format In DDT mode, the request queues of any channel can be cleared by using DTR.ID, DTR.MD, DTR.SZ, and DTR.COUNT [7:4] in a DTR format. This function is only available when DMAOR.DBL = 1.
Page 734: Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Section 14 Direct Memory Access Controller (DMAC) Table 14.18 DMAC Interrupt-Request Codes Source of the Interrupt Description INTEVT Code Priority DMTE0 CH0 transfer-end interrupt H'640 High DMTE1 CH1 transfer-end interrupt H'660 DMTE2 CH2 transfer-end interrupt H'680 DMTE3 CH3 transfer-end interrupt H'6A0 DMTE4 CH4 transfer-end interrupt...
Page 735: Figure 14.56 Single Address Mode/Burst Mode/External Bus → External Device/32-Byte
Section 14 Direct Memory Access Controller (DMAC) CKIO DBREQ BAVL/ID2 A25–A0 D63–D0 RAS, CAS, WE TDACK ID1, ID0 Figure 14.56 Single Address Mode/Burst Mode/External Bus → External Device/32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 Rev.7.00 Oct. 10, 2008 Page 651 of 1074 REJ09B0366-0700...
Page 736: Usage Notes
Section 14 Direct Memory Access Controller (DMAC) 14.9 Usage Notes 1. When modifying SAR0–SAR3, DAR0–DAR3, DMATCR0–DMATCR3, and CHCR0– CHCR3 in the SH7750 or SH7750S or when modifying SAR0–SAR7, DAR0–DAR7, DMATCR0–DMATCR7, and CHCR0–CHCR7 in the SH7750R, first clear the DE bit for the relevant channel.
Page 737 Section 14 Direct Memory Access Controller (DMAC) 7. When falling edge detection is used for external requests, keep the external request pin high when making DMAC settings. 8. When using the DMAC in single address mode, set an external address as the address. All channels will halt due to an address error if an on-chip peripheral module address is set.
Page 738 Section 14 Direct Memory Access Controller (DMAC) Rev.7.00 Oct. 10, 2008 Page 654 of 1074 REJ09B0366-0700...
Page 739: Section 15 Serial Communication Interface (Sci)
Section 15 Serial Communication Interface (SCI) Section 15 Serial Communication Interface (SCI) 15.1 Overview This LSI is equipped with a single-channel serial communication interface (SCI) and a single- channel serial communication interface with built-in FIFO registers (SCI with FIFO: SCIF). The SCI can handle both asynchronous and synchronous serial communication.
Page 740 Section 15 Serial Communication Interface (SCI) ⎯ Synchronous mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other chips that have a synchronous communication function. There is a single serial data transfer format. Data length: 8 bits Receive error detection: Overrun errors...
Page 741: Block Diagram
Section 15 Serial Communication Interface (SCI) 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the SCI. Internal Module data bus data bus SCSSR1 SCBRR1 SCRDR1 SCTDR1 SCSCR1 SCSMR1 SCRSR1 SCTSR1 Baud rate Pck/4 SCSPTR1 generator Transmission/ Pck/16 reception control Pck/64 Clock...
Page 742: Pin Configuration
Section 15 Serial Communication Interface (SCI) 15.1.3 Pin Configuration Table 15.1 shows the SCI pin configuration. Table 15.1 SCI Pins Pin Name Abbreviation Function Serial clock pin MD0/SCK Clock input/output Receive data pin Input Receive data input Transmit data pin MD7/TxD Output Transmit data output...
Page 743: Register Descriptions
Section 15 Serial Communication Interface (SCI) Table 15.2 SCI Registers Initial Area 7 Access Name Abbreviation Value P4 Address Address Size Serial mode register SCSMR1 H'00 H'FFE00000 H'1FE00000 Bit rate register SCBRR1 H'FF H'FFE00004 H'1FE00004 Serial control register SCSCR1 H'00 H'FFE00008 H'1FE00008 Transmit data register...
Page 744: Receive Data Register (Scrdr1)
Section 15 Serial Communication Interface (SCI) 15.2.2 Receive Data Register (SCRDR1) Bit: Initial value: R/W: SCRDR1 is the register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received data from SCRSR1 to SCRDR1 where it is stored, and completes the receive operation.
Page 745: Transmit Data Register (Sctdr1)
Section 15 Serial Communication Interface (SCI) 15.2.4 Transmit Data Register (SCTDR1) Bit: Initial value: R/W: SCTDR1 is an 8-bit register that stores data for serial transmission. When the SCI detects that SCTSR1 is empty, it transfers the transmit data written in SCTDR1 to SCTSR1 and starts serial transmission.
Page 746 Section 15 Serial Communication Interface (SCI) Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting, Bit 6: CHR Description 8-bit data (Initial value)
Page 747 Section 15 Serial Communication Interface (SCI) Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set, the STOP bit setting is invalid since stop bits are not added.
Page 748: Serial Control Register (Scscr1)
Section 15 Serial Communication Interface (SCI) For the relation between the clock source, the bit rate register setting, and the baud rate, see section 15.2.9, Bit Rate Register (SCBRR1). Bit 1: CKS1 Bit 0: CKS0 Description Pck clock (Initial value) Pck/4 clock Pck/16 clock Pck/64 clock...
Page 749 Section 15 Serial Communication Interface (SCI) Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1. Bit 6: RIE Description Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI)
Page 750 Section 15 Serial Communication Interface (SCI) Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR1 is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3: MPIE Description Multiprocessor interrupts disabled (normal reception performed) (Initial value)
Page 751: Serial Status Register (Scssr1)
Section 15 Serial Communication Interface (SCI) Bit 1: CKE1 Bit 0: CKE0 Description Asynchronous mode Internal clock/SCK pin functions as input pin (input signal ignored) * Synchronous mode Internal clock/SCK pin functions as serial clock output * Asynchronous mode Internal clock/SCK pin functions as clock output * Synchronous mode Internal clock/SCK pin functions as...
Page 752 Section 15 Serial Communication Interface (SCI) Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1. Bit 7: TDRE Description Valid transmit data has been written to SCTDR1 [Clearing conditions] •...
Page 753 Section 15 Serial Communication Interface (SCI) Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5: ORER Description Reception in progress, or reception has ended normally * (Initial value) [Clearing conditions] • Power-on reset, manual reset, standby mode, or module standby •...
Page 754 Section 15 Serial Communication Interface (SCI) Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception with parity addition in asynchronous mode, causing abnormal termination. Bit 3: PER Description Reception in progress, or reception has ended normally * (Initial value) [Clearing conditions] •...
Page 755: Serial Port Register (Scsptr1)
Section 15 Serial Communication Interface (SCI) Note: * This bit is prepared for storing a multi-processor bit in the received data when the receipt is carried out with a multi-processor format in asynchronous mode. This bit does not function correctly in this LSI. However, do not use the read value from this bit.
Page 756 Section 15 Serial Communication Interface (SCI) ERI interrupts are handled by the CPU. The DMAC transfers read data to memory or another peripheral module. This bit specifies enabling or disabling of the RXI interrupt. Bit 7: EIO Description When the RIE bit is 1, RXI and ERI interrupts are sent to INTC (Initial value) When the RIE bit is 1, only ERI interrupts are sent to INTC Bits 6 to 4—Reserved: These bits are always read as 0, and should only be written with 0.
Page 757 Section 15 Serial Communication Interface (SCI) SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless of the value of the SPB0IO bit. The initial value of this bit after a power-on or manual reset is undefined.
Page 758: Figure 15.2 Md0/Sck Pin
Section 15 Serial Communication Interface (SCI) Reset SPB1IO Internal data bus SPTRW Reset MD0/SCK SPB1DT SPTRW Clock output enable signal Mode setting Serial clock output signal register Serial clock input signal Clock input enable signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * Signals that set the SCK pin function as internal clock output or external clock input according to the CKE0 and CKE1 bits in SCSCR1 and the C/A bit in SCSMR1.
Page 759: Figure 15.3 Md7/Txd Pin
Section 15 Serial Communication Interface (SCI) Reset SPB0IO Internal data bus SPTRW Reset MD7/TxD SPB0DT Transmit enable signal SPTRW Mode setting register Serial transmit data Legend: SPTRW: Write to SPTR Figure 15.3 MD7/TxD Pin Serial receive data Internal data bus SPTRR Legend: SPTRR: Read SPTR...
Page 760: Bit Rate Register (Scbrr1)
Section 15 Serial Communication Interface (SCI) 15.2.9 Bit Rate Register (SCBRR1) Bit: Initial value: R/W: SCBRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR1. SCBRR1 can be read or written to by the CPU at all times.
Page 761: Table 15.3 Examples Of Bit Rates And Scbrr1 Settings In Asynchronous Mode
Section 15 Serial Communication Interface (SCI) The bit rate error in asynchronous mode is found from the following equation: Pck × 10 × 100 Error (%) = – 1 (N + 1) × B × 64 × 2 2n – 1 Table 15.3 shows sample SCBRR1 settings in asynchronous mode, and table 15.4 shows sample SCBRR1 settings in synchronous mode.
Page 762 Section 15 Serial Communication Interface (SCI) Pck (MHz) 3.6864 4.9152 Bit Rate Error Error Error Error (bits/s) 0.70 0.03 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00 0.16 2400 0.00 0.16 0.00 0.16...
Page 763 Section 15 Serial Communication Interface (SCI) Pck (MHz) 9.8304 12.288 Bit Rate Error Error Error Error (bits/s) –0.26 –0.25 0.03 0.08 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 1200 0.00 0.16 0.16 0.00 2400 0.00 0.16 0.16 0.00...
Page 764 Section 15 Serial Communication Interface (SCI) Pck (MHz) 24.576 28.7 Bit Rate Error Error Error Error (bits/s) –0.44 0.08 0.31 0.13 0.16 0.00 0.46 –0.35 0.16 0.00 –0.08 0.16 0.16 0.00 0.46 –0.35 1200 0.16 0.00 –0.08 0.16 2400 0.16 0.00 0.46 –0.35...
Page 765: Table 15.4 Examples Of Bit Rates And Scbrr1 Settings In Synchronous Mode
Section 15 Serial Communication Interface (SCI) Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode Pck (MHz) 28.7 Bit Rate (bits/s) — — — — — — — — — — — — — — 2.5k 100k 250k —...
Page 766: Table 15.5 Maximum Bit Rate For Various Frequencies With Baud Rate Generator
Section 15 Serial Communication Interface (SCI) Table 15.5 shows the maximum bit rate for various frequencies in asynchronous mode. Tables 15.6 and 15.7 show the maximum bit rates with external clock input. Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pck (MHz)
Page 767: Table 15.6 Maximum Bit Rate With External Clock Input (Asynchronous Mode)
Section 15 Serial Communication Interface (SCI) Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) Pck (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152...
Page 768: Operation
Section 15 Serial Communication Interface (SCI) 15.3 Operation 15.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SCSMR1 as shown in table 15.8.
Page 769: Table 15.8 Scsmr1 Settings For Serial Transfer Format Selection
Section 15 Serial Communication Interface (SCI) Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection SCSMR1 Settings SCI Transfer Format Multi- Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: Data processor Parity Stop Bit STOP Mode Length Length Asynchronous 8-bit data 1 bit...
Page 770: Operation In Asynchronous Mode
Section 15 Serial Communication Interface (SCI) Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection SCSMR1 SCSCR1 Setting SCI Transmit/Receive Clock Bit 7: Bit 1: Bit 0: Clock CKE1 CKE0 Mode Source SCK Pin Function Asynchronous Internal SCI does not use SCK pin mode Outputs clock with same frequency as bit rate...
Page 771: Figure 15.5 Data Format In Asynchronous Communication (Example With 8-Bit Data, Parity, Two Stop Bits)
Section 15 Serial Communication Interface (SCI) In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the eighth pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit.
Page 772: Table 15.10 Serial Transfer Formats (Asynchronous Mode)
Section 15 Serial Communication Interface (SCI) Table 15.10 Serial Transfer Formats (Asynchronous Mode) SCSMR1 Settings Serial Transfer Format and Frame Length CHR PE MP STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP...
Page 773: Figure 15.6 Relation Between Output Clock And Transfer Data Phase
Section 15 Serial Communication Interface (SCI) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1.
Page 774: Figure 15.7 Sample Sci Initialization Flowchart
Section 15 Serial Communication Interface (SCI) 1. Set the clock selection in SCSCR1. Initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits When clock output is selected in in SCSCR1 to 0 asynchronous mode, it is output immediately after SCSCR1 settings...
Page 775: Figure 15.8 Sample Serial Transmission Flowchart
Section 15 Serial Communication Interface (SCI) 1. SCI status check and transmit data Start of transmission write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear Read TDRE flag in SCSSR1 the TDRE flag to 0.
Page 776 Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2.
Page 777: Figure 15.9 Example Of Transmit Operation In Asynchronous Mode (Example With 8-Bit Data, Parity, One Stop Bit)
Section 15 Serial Communication Interface (SCI) Start Data Parity Stop Start Data Parity Stop Serial Idle state data (mark state) TDRE TEND TXI interrupt TXI interrupt request request TEI interrupt Data written to SCTDR1 request and TDRE flag cleared to 0 by TXI interrupt handler One frame Figure 15.9 Example of Transmit Operation in Asynchronous Mode...
Page 778: Figure 15.10 Sample Serial Reception Flowchart (1)
Section 15 Serial Communication Interface (SCI) 1. Receive error handling and Start of reception break detection: If a receive error occurs, read the ORER, PER, and FER flags in Read ORER, PER, and FER flags SCSSR1 to identify the error. in SCSSR1 After performing the appropriate error handling,...
Page 779: Figure 15.10 Sample Serial Reception Flowchart (2)
Section 15 Serial Communication Interface (SCI) Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCSCR1 to 0 PER = 1? Parity error handling Clear ORER, PER, and FER flags in SCSSR1 to 0 Figure 15.10 Sample Serial Reception Flowchart (2) Rev.7.00 Oct.
Page 780: Table 15.11 Receive Error Conditions
Section 15 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3.
Page 781: Figure 15.11 Example Of Sci Receive Operation (Example With 8-Bit Data, Parity, One Stop Bit)
Section 15 Serial Communication Interface (SCI) Figure 15.11 shows an example of the operation for reception in asynchronous mode. Start Data Parity Stop Start Data Parity Stop Serial data RDRF RXI interrupt request SCRDR1 data read and ERI interrupt request RDRF flag cleared to 0 generated by framing One frame...
Page 782: Multiprocessor Communication Function
Section 15 Serial Communication Interface (SCI) 15.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a serial transmission line.
Page 783: Figure 15.12 Example Of Inter-Processor Communication Using Multiprocessor Format (Transmission Of Data H'aa To Receiving Station A)
Section 15 Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle: Data transmission cycle:...
Page 784: Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart
Section 15 Serial Communication Interface (SCI) Start of transmission 1. SCI status check and ID data write: Read SCSSR1 and check that the Read TEND flag in SCSSR1 TEND flag is set to 1, then set the MPBT bit in SCSSR1 to 1 and write ID data to SCTDR1.
Page 785 Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2.
Page 786: Figure 15.14 Example Of Sci Transmit Operation (Example With 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Section 15 Serial Communication Interface (SCI) Multi- Multi- Multi- Start Data proces- Stop Start Data proces- Stop Start Data proces- Stop sor bit sor bit sor bit Serial Idle state D0 D1 D0 D1 D0 D1 data (mark state) TDRE TEND Data written to SCTDR1 TXI interrupt...
Page 787 Section 15 Serial Communication Interface (SCI) b. If the MPIE bit in the SCSCR1 register is cleared to 0 A multiprocessor interrupt indicating that data (ID) with the multiprocessor bit (MPB) set to 1 was received, or a receive data full interrupt (RXI) occurred when data with the multiprocessor bit (MPB) set to 0 and intended for this station was received.
Page 788: Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1)
Section 15 Serial Communication Interface (SCI) Start of reception Set MPIE bit to 1 RXI = 1? User-defined receive start flag = 1? Read ORER and FER flags in SCSSR1 FER or ORER = 1? Read RDRF flag in SCSSR1 MPIE = 0? Read receive data in SCRDR1 This station's ID?
Page 789: Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2)
Section 15 Serial Communication Interface (SCI) Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCSCR1 to 0 Clear ORER and FER flags in SCSSR1 to 0 Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2) Rev.7.00 Oct.
Page 790: Figure 15.16 Example Of Sci Receive Operation (Example With 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Section 15 Serial Communication Interface (SCI) Figure 15.16 shows an example of SCI operation for multiprocessor format reception. Data Start Stop Start Stop Data (ID1) (Data1) Serial Idle state data (mark state) MPIE RDRF SCRDR1 value RXI interrupt request SCRDR1 data read As data is not this RXI interrupt The RDRF flag...
Page 791: Operation In Synchronous Mode
Section 15 Serial Communication Interface (SCI) In multiprocessor mode serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR1 in LSB-to-MSB order. 3.
Page 792 Section 15 Serial Communication Interface (SCI) In serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In synchronous mode, the SCI receives data in synchronization with the falling edge of the serial clock.
Page 793: Figure 15.18 Sample Sci Initialization Flowchart
Section 15 Serial Communication Interface (SCI) Figure 15.18 shows a sample SCI initialization flowchart. 1. Set the clock selection in SCSCR1. Initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Clear TE and RE bits 2.
Page 794: Figure 15.19 Sample Serial Transmission Flowchart
Section 15 Serial Communication Interface (SCI) Serial Data Transmission (Synchronous Mode): Figure 15.19 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. 1. SCI status check and transmit Start of transmission data write: Read SCSSR1 and check that the TDRE flag is set to...
Page 795 Section 15 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1. 2.
Page 796: Figure 15.20 Example Of Sci Transmit Operation
Section 15 Serial Communication Interface (SCI) Transfer direction Serial clock Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Serial data TDRE TEND Data written to SCTDR1 TXI interrupt TEI interrupt and TDRE flag cleared to request request 0 in TXI interrupt handler...
Page 797: Figure 15.21 Sample Serial Reception Flowchart (1)
Section 15 Serial Communication Interface (SCI) Serial Data Reception (Synchronous Mode): Figure 15.21 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0.
Page 798: Figure 15.21 Sample Serial Reception Flowchart (2)
Section 15 Serial Communication Interface (SCI) Error handling ORER = 1? Overrun error handling Clear ORER flag in SCSSR1 to 0 Figure 15.21 Sample Serial Reception Flowchart (2) In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with serial clock input or output. 2.
Page 799: Figure 15.22 Example Of Sci Receive Operation
Section 15 Serial Communication Interface (SCI) Figure 15.22 shows an example of SCI operation in reception. Transfer direction Serial clock Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Serial data RDRF ORER Data read from RXI interrupt ERI interrupt RXI interrupt...
Page 800: Figure 15.23 Sample Flowchart For Serial Data Transmission And Reception
Section 15 Serial Communication Interface (SCI) 1. SCI status check and transmit data Start of transmission/reception write: Read SCSSR1 and check that the TDRE flag is set to 1, then write transmit data to SCTDR1 and clear Read TDRE flag in SCSSR1 the TDRE flag to 0.
Page 801: Sci Interrupt Sources And Dmac
Section 15 Serial Communication Interface (SCI) 15.4 SCI Interrupt Sources and DMAC The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 15.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCRSR1, and the EIO bit in SCSPTR1.
Page 802: Usage Notes
Section 15 Serial Communication Interface (SCI) Table 15.12 SCI Interrupt Sources Interrupt DMAC Priority on Source Description Activation Reset Release Receive error (ORER, FER, or PER) Not possible High Receive data register full (RDRF) Possible Transmit data register empty (TDRE) Possible Transmit end (TEND) Not possible Low...
Page 803: Table 15.13 Scssr1 Status Flags And Transfer Of Receive Data
Section 15 Serial Communication Interface (SCI) Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data SCSSR1 Status Flags Receive Data Transfer SCRSR1 → SCRDR1 Receive Errors RDRF ORER Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error +...
Page 804: Figure 15.24 Receive Data Sampling Timing In Asynchronous Mode
Section 15 Serial Communication Interface (SCI) Handling of TEND Flag and TE Bit: The TEND flag is set to 1 when the stop bit of the final data segment is transmitted. If the TE bit is cleared immediately after confirming that the TEND flag was set, transmission may not complete properly because stop bit transmission processing is still underway.
Page 805: Figure 15.25 Example Of Synchronous Transmission By Dmac
Section 15 Serial Communication Interface (SCI) The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). | D – 0.5 | (1 + F) × 100% ....(1) M = (0.5 – ) – (L – 0.5) F – M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0 to 1.0)
Page 806 Section 15 Serial Communication Interface (SCI) • When using the DMAC for transmission/reception, making a setting to disable RXI and TXI interrupt requests to the interrupt controller. Even if issuance of interrupt requests is set, interrupt requests to the interrupt controller will be cleared by the DMAC independently of the interrupt handling program.
Page 807: Figure 15.26 Example Countermeasure On Sh7750
Section 15 Serial Communication Interface (SCI) Workaround 2 Do not select settings a., b., and c. at the same time. Multiplexer (switches between clock mode and SCK input) SH7750 Mode setting signal MD0/SCK Edge trigger FF CKIO Figure 15.26 Example Countermeasure on SH7750 •...
Page 808: Table 15.14 Peripheral Module Signal Timing
Section 15 Serial Communication Interface (SCI) Table 15.14 Peripheral Module Signal Timing tSCKS tSCKH Product Unit ⎯ ⎯ HD6417750BP200 ⎯ ⎯ HD6417750BP200M ⎯ ⎯ HD6417750F167 ⎯ ⎯ HD6417750F167I ⎯ ⎯ HD6417750VF128 Rev.7.00 Oct. 10, 2008 Page 724 of 1074 REJ09B0366-0700...
Page 809: Section 16 Serial Communication Interface With Fifo (Scif)
Section 16 Serial Communication Interface with FIFO (SCIF) Section 16 Serial Communication Interface with FIFO (SCIF) 16.1 Overview This LSI is equipped with a single-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform asynchronous serial communication.
Page 810 Section 16 Serial Communication Interface with FIFO (SCIF) • Choice of serial clock source: internal clock from baud rate generator or external clock from SCK2 pin • Four interrupt sources There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error—that can issue requests independently. •...
Page 811: Block Diagram
Section 16 Serial Communication Interface with FIFO (SCIF) 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the SCIF. Internal Module data bus data bus SCBRR2 SCFRDR2 SCSMR2 SCFTDR2 (16-stage) (16-stage) SCLSR2 SCFDR2 SCFCR2 RxD2 SCRSR2 SCTSR2 SCFSR2 Baud rate Pck/4 generator SCSCR2...
Page 812: Pin Configuration
Section 16 Serial Communication Interface with FIFO (SCIF) 16.1.3 Pin Configuration Table 16.1 shows the SCIF pin configuration. Table 16.1 SCIF Pins Pin Name Abbreviation Function Serial clock pin SCK2/MRESET Input Clock input Receive data pin MD2/RxD2 Input Receive data input Transmit data pin MD1/TxD2 Output...
Page 813: Register Configuration
Section 16 Serial Communication Interface with FIFO (SCIF) 16.1.4 Register Configuration The SCIF has the internal registers shown in table 16.2. These registers are used to specify the data format and bit rate, and to perform transmitter/receiver control. Table 16.2 SCIF Registers Abbrevia- Initial Area 7...
Page 814: Receive Fifo Data Register (Scfrdr2)
Section 16 Serial Communication Interface with FIFO (SCIF) SCRSR2 cannot be directly read or written to by the CPU. 16.2.2 Receive FIFO Data Register (SCFRDR2) Bit: R/W: SCFRDR2 is a 16-stage FIFO register that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR2 to SCFRDR2 where it is stored, and completes the receive operation.
Page 815: Transmit Fifo Data Register (Scftdr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.4 Transmit FIFO Data Register (SCFTDR2) Bit: R/W: SCFTDR2 is an 8-bit 16-stage FIFO register that stores data for serial transmission. If SCTSR2 is empty when transmit data has been written to SCFTDR2, the SCIF transfers the transmit data written in SCFTDR2 to SCTSR2 and starts serial transmission.
Page 816 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6—Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length. Bit 6: CHR Description 8-bit data (Initial value) 7-bit data* Note: When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted. Bit 5—Parity Enable (PE): Selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception.
Page 817 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length. Bit 3: STOP Description 1 stop bit * (Initial value) 2 stop bits * Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent.
Page 818: Serial Control Register (Scscr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.6 Serial Control Register (SCSCR2) Bit: — — — — — — — — Initial value: R/W: Bit: REIE — CKE1 — Initial value: R/W: The SCSCR2 register performs enabling or disabling of SCIF transfer operations, and interrupt requests, and selection of the serial clock source.
Page 819 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR2 is set to 1, a receive-error interrupt (ERI) request when the ER flag in SCFSR2 is set to 1, and a break interrupt (BRI) request when the BRK flag in SCFSR2 or the ORER flag in SCLSR2 is set to 1.
Page 820 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 3—Receive Error Interrupt Enable (REIE): Enables or disables generation of receive-error interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the RIE bit is 0. Bit 3: REIE Description Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled*...
Page 821: Serial Status Register (Scfsr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.7 Serial Status Register (SCFSR2) Bit: PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 Initial value: R/W: Bit: TEND TDFE Initial value: R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Only 0 can be written, to clear the flag. SCFSR2 is a 16-bit register.
Page 822 Section 16 Serial Communication Interface with FIFO (SCIF) If all 16 bytes of receive data in SCFRDR2 have framing errors, the value indicated by bits FER3 to FER0 will be 0. Bit 7—Receive Error (ER): Indicates that a framing error or parity error occurred during reception.* Note: * The ER flag is not affected and retains its previous state when the RE bit in SCSCR2 is cleared to 0.
Page 823 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6—Transmit End (TEND): Indicates that there is no valid data in SCFTDR2 when the last bit of the transmit character is sent, and transmission has been ended. Bit 6: TEND Description Transmission is in progress [Clearing conditions] •...
Page 824 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from SCFTDR2 to SCTSR2, the number of data bytes in SCFTDR2 has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2), and new transmit data can be written to SCFTDR2.
Page 825 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected. Bit 4: BRK Description A break signal has not been received (Initial value) [Clearing conditions] • Power-on reset or manual reset •...
Page 826 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 2—Parity Error (PER): Indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR2. Bit 2: PER Description There is no parity error that is to be read from SCFRDR2 (Initial value) [Clearing conditions] •...
Page 827 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 1—Receive FIFO Data Full (RDF): Indicates that the received data has been transferred from SCRSR2 to SCFRDR2, and the number of receive data bytes in SCFRDR2 is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR2).
Page 828: Bit Rate Register (Scbrr2)
Section 16 Serial Communication Interface with FIFO (SCIF) Bit 0—Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR2, and no further data has arrived for at least 15 etu after the stop bit of the last data received.
Page 829: Fifo Control Register (Scfcr2)
Section 16 Serial Communication Interface with FIFO (SCIF) The SCBRR2 setting is found from the following equation. Asynchronous mode: × 10 – 1 64 × 2 × B 2n – 1 Where B: Bit rate (bits/s) N: SCBRR2 setting for baud rate generator (0 ≤ N ≤ 255) Pck: Peripheral module operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.)
Page 830 Section 16 Serial Communication Interface with FIFO (SCIF) SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR2 can be read or written to by the CPU at all times. SCFCR2 is initialized to H'0000 by a power-on reset or manual reset.
Page 831 Section 16 Serial Communication Interface with FIFO (SCIF) Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status register (SCFSR2).
Page 832 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 3—Modem Control Enable (MCE): Enables the CTS2 and RTS2 modem control signals. Bit 3: MCE Description Modem signals disabled* (Initial value) Modem signals enabled CTS2 is fixed at active-0 regardless of the input value, and RTS2 output is also fixed at Note: Bit 2—Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state.
Page 833: Fifo Data Count Register (Scfdr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.10 FIFO Data Count Register (SCFDR2) SCFDR2 is a 16-bit register that indicates the number of data bytes stored in SCFTDR2 and SCFRDR2. The upper 8 bits show the number of transmit data bytes in SCFTDR2, and the lower 8 bits show the number of receive data bytes in SCFRDR2.
Page 834: Serial Port Register (Scsptr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.11 Serial Port Register (SCSPTR2) Bit: — — — — — — — — Initial value: R/W: Bit: RTSIO RTSDT CTSIO CTSDT — — SPB2IO SPB2DT Initial value: — — — — R/W: SCSPTR2 is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins.
Page 835 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port RTS2 pin input/output data. Input or output is specified by the RTSIO bit (see the description of bit 7, RTSIO, for details).
Page 836 Section 16 Serial Communication Interface with FIFO (SCIF) Bit 1—Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT bit, the TE bit in SCSCR2 should be cleared to 0.
Page 837: Figure 16.2 Md8/Rts2 Pin
Section 16 Serial Communication Interface with FIFO (SCIF) SCIF I/O port block diagrams are shown in figures 16.2 to 16.5. Reset RTSIO Internal data bus SPTRW Reset MD8/RTS2 RTSDT SCIF Modem control SPTRW enable signal* RTS2 signal Mode setting register SPTRR Legend: SPTRW: Write to SPTR...
Page 838: Figure 16.3 Cts2 Pin
Section 16 Serial Communication Interface with FIFO (SCIF) Reset CTSIO Internal data bus SPTRW Reset CTS2 CTSDT SCIF SPTRW CTS2 signal Modem control enable signal * SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * The CTS2 pin function is designated as modem control by the MCE bit in SCFCR2. Figure 16.3 CTS2 Pin Rev.7.00 Oct.
Page 839: Figure 16.4 Md1/Txd2 Pin
Section 16 Serial Communication Interface with FIFO (SCIF) Reset SPB2IO Internal data bus SPTRW Reset MD1/TxD2 SPB2DT SCIF Transmit enable SPTRW signal Mode setting register Serial transmit data Legend: SPTRW: Write to SPTR Figure 16.4 MD1/TxD2 Pin SCIF MD2/RxD2 Serial receive data Mode setting register...
Page 840: Line Status Register (Sclsr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.2.12 Line Status Register (SCLSR2) Bit: — — — — — — — — Initial value: R/W: Bit: — — — — — — — ORER Initial value: R/W: (R/W)* Note: Only 0 can be written, to clear the flag. Bits 15 to 1—Reserved: These bits are always read as 0, and should only be written with 0.
Page 841: Operation
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3 Operation 16.3.1 Overview The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character. See section 15.3.2, Operation in Asynchronous Mode, for details. Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead and enabling fast, continuous communication to be performed.
Page 842: Serial Operation
Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection SCSMR2 Settings SCIF Transfer Format Bit 6: Bit 5: Bit 3: Data Multiprocessor Parity Stop Bit STOP Mode Length Length Asynchronous mode 8-bit data No 1 bit 2 bits 1 bit...
Page 843: Table 16.5 Serial Transmit/Receive Formats
Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.5 Serial Transmit/Receive Formats SCSMR2 Settings Serial Transmit/Receive Format and Frame Length CHR PE STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP...
Page 844 Section 16 Serial Communication Interface with FIFO (SCIF) Data Transfer Operations SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR2 to 0, then initialize the SCIF as described below. When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 845: Figure 16.6 Sample Scif Initialization Flowchart
Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.6 shows a sample SCIF initialization flowchart. 1. Set the clock selection in SCSCR2. Initialization Be sure to clear bits RIE and TIE, and bits TE and RE, to 0. Clear TE and RE bits 2.
Page 846: Figure 16.7 Sample Serial Transmission Flowchart
Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Transmission: Figure 16.7 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. 1. SCIF status check and transmit data Start of transmission write: Read SCFSR2 and check that the...
Page 847 Section 16 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR2, the SCIF transfers the data from SCFTDR2 to SCTSR2 and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR2) is set to 1 before writing transmit data to SCFTDR2.
Page 848: Figure 16.8 Example Of Transmit Operation (Example With 8-Bit Data, Parity, One Stop Bit)
Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.8 shows an example of the operation for transmission in asynchronous mode. Start Data Parity Stop Start Data Parity Stop Serial Idle state data (mark state) TDFE TEND TXI interrupt TXI interrupt request request Data written to SCFTDR2...
Page 849: Figure 16.10 Sample Serial Reception Flowchart (1)
Section 16 Serial Communication Interface with FIFO (SCIF) Serial Data Reception: Figure 16.10 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR2, and the ORER flag...
Page 850: Figure 16.10 Sample Serial Reception Flowchart (2)
Section 16 Serial Communication Interface with FIFO (SCIF) 1. Whether a framing error or parity error Error handling has occurred that is to be read from SCFRDR2 can be ascertained from the FER and PER bits in SCFSR2. ORER = 1? 2.
Page 851 Section 16 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR2 in LSB-to-MSB order. 3.
Page 852: Figure 16.11 Example Of Scif Receive Operation (Example With 8-Bit Data, Parity, One Stop Bit)
Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.11 shows an example of the operation for reception in asynchronous mode. Start Data Parity Stop Start Data Parity Stop Serial data RXI interrupt request Data read and RDF flag ERI interrupt request read as 1 then cleared to generated by receive One frame...
Page 853: Scif Interrupt Sources And The Dmac
Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.12 shows an example of the operation when modem control is used. Start Parity Stop Start Serial data D1 D2 D7 0/1 1 RxD2 RTS2 Figure 16.12 Example of Operation Using Modem Control (RTS2) 16.4 SCIF Interrupt Sources and the DMAC The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receive-...
Page 854: Usage Notes
Section 16 Serial Communication Interface with FIFO (SCIF) When the BRK flag in SCFSR2 or the ORER flag in the line status register (SCLSR2) is set to 1, a BRI interrupt request is generated. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR2.
Page 855 Section 16 Serial Communication Interface with FIFO (SCIF) FIFO control register (SCFCR2). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR2, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR2 is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0.
Page 856: Figure 16.13 Receive Data Sampling Timing In Asynchronous Mode
Section 16 Serial Communication Interface with FIFO (SCIF) 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock –7.5 clocks +7.5 clocks...
Page 857 Section 16 Serial Communication Interface with FIFO (SCIF) SCK2/MRESET: As the manual reset pin is multiplexed with the SCK2 pin, a manual reset must not be executed while the SCIF is operating in external clock mode. When Using the DMAC: When using the DMAC for transmission/reception, inhibit output of RXI and TXI interrupt requests to the interrupt controller.
Page 858: Figure 16.14 Overrun Error Flag
Section 16 Serial Communication Interface with FIFO (SCIF) Flow chart: Framing error occurrence When flaming error (SCFSR.ER=1) is occurred, bit7 to bit0 should be read out from SCFDR2. If bit7 to bit0 Bits 7 to 0 in SCFDR2 = H'10? equals H'10, contents of the receive FIFO should be read.
Page 859: Section 17 Smart Card Interface
Section 17 Smart Card Interface Section 17 Smart Card Interface 17.1 Overview The serial communication interface (SCI) supports a subset of the ISO/IEC 7816-3 (identification cards) standard as an extended function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting.
Page 860: Block Diagram
Section 17 Smart Card Interface 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the smart card interface. Internal Module data bus data bus SCSCMR1 SCBRR1 SCRDR1 SCTDR1 SCSSR1 SCSCR1 SCRSR1 SCTSR1 Baud rate SCSMR1 Pck/4 generator SCSPTR1 Pck/16 Transmission/ reception control...
Page 861: Pin Configuration
Section 17 Smart Card Interface 17.1.3 Pin Configuration Table 17.1 shows the smart card interface pin configuration. Table 17.1 Smart Card Interface Pins Pin Name Abbreviation Function Serial clock pin MD0/SCK Clock input/output Receive data pin Input Receive data input Transmit data pin MD7/TxD Output...
Page 862: Register Descriptions
Section 17 Smart Card Interface 17.2 Register Descriptions Only registers that have been added, and bit functions that have been modified, for the smart card interface are described here. 17.2.1 Smart Card Mode Register (SCSCMR1) SCSCMR1 is an 8-bit readable/writable register that selects the smart card interface function. SCSCMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the module standby state.
Page 863: Serial Mode Register (Scsmr1)
Section 17 Smart Card Interface Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0: SMIF Description Smart card interface function is disabled (Initial value) Smart card interface function is enabled 17.2.2 Serial Mode Register (SCSMR1) Bit 7 of SCSMR1 has a different function in smart card interface mode.
Page 864: Serial Control Register (Scscr1)
Section 17 Smart Card Interface Bits 6 to 0: Operate in the same way as for the normal SCI. See section 15, Serial Communication Interface (SCI), for details. With the smart card interface, the following settings should be used: CHR = 0, PE = 1, STOP = 1, MP = 0. 17.2.3 Serial Control Register (SCSCR1) Bits 1 and 0 of SCSCR1 have a different function in smart card interface mode.
Page 865: Serial Status Register (Scssr1)
Section 17 Smart Card Interface 17.2.4 Serial Status Register (SCSSR1) Bit 4 of SCSSR1 has a different function in smart card interface mode. Coupled with this, the setting conditions for bit 2 (TEND) are also different. Bit: TDRE RDRF ORER FER/ TEND —...
Page 866: Operation
Section 17 Smart Card Interface Bit 2—Transmit End (TEND): The setting conditions for the TEND flag are as follows. Bit 2: TEND Description Transmission in progress [Clearing condition] When 0 is written to TDRE after reading TDRE = 1 Transmission has been ended (Initial value) [Setting conditions] •...
Page 867: Pin Connections
Section 17 Smart Card Interface 17.3.2 Pin Connections Figure 17.2 shows a schematic diagram of smart card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected outside the chip. The data transmission line should be pulled up on the V power supply side with a resistor.
Page 868: Data Format
Section 17 Smart Card Interface 17.3.3 Data Format Figure 17.3 shows the smart card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting side to request retransmission of the data.
Page 869: Register Settings
Section 17 Smart Card Interface 4. The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data.
Page 870: Figure 17.4 Tend Generation Timing
Section 17 Smart Card Interface Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 17.3.5, Clock. I/O data Ds Da Db Dc Dd De Dg Dh Dp Guard time 12.5 etu GM = 0 (TEND interrupt) 11.0 etu GM = 1...
Page 871: Clock
Section 17 Smart Card Interface With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data in this case is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card.
Page 872: Table 17.4 Values Of N And Corresponding Cks1 And Cks0 Settings
Section 17 Smart Card Interface Pck = Peripheral module operating frequency (MHz) n = 0 to 3 (See table 17.4) Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings CKS1 CKS0 Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) Pck (MHz) 7.1424 10.00...
Page 873: Table 17.7 Maximum Bit Rate At Various Frequencies (Smart Card Interface Mode)
Section 17 Smart Card Interface Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) Pck (MHz) Maximum Bit Rate (bits/s) 7.1424 19200 10.00 26882 10.7136 28800 16.00 43010 20.00 53763 25.0 67204 30.0 80645 33.0 88710 50.0 67204 The bit rate error is given by the following equation: ×...
Page 874: Data Transmit/Receive Operations
Section 17 Smart Card Interface Width is Width is Port value undefined undefined Port value (a) When GM = 0 Specified Specified CKE1 value width width CKE1 value (b) When GM = 1 Figure 17.6 Difference in Clock Output According to GM Bit Setting 17.3.6 Data Transmit/Receive Operations Initialization: Before transmitting and receiving data, the smart card interface must be initialized...
Page 875: Figure 17.7 Sample Initialization Flowchart
Section 17 Smart Card Interface Initialization Clear TE and RE bits in SCSCR1 to 0 Clear FER/ERS, PER, and ORER flags in SCSCR1 to 0 In SCSMR1, set parity in O/E bit, clock in CKS1 and CKS0 bits, and set GM Set SMIF, SDIR, and SINV bits in SCSCMR1 Set value in SCBRR1...
Page 876 Section 17 Smart Card Interface Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 17.8 shows a sample transmission processing flowchart. 1.
Page 877: Figure 17.8 Sample Transmission Processing Flowchart
Section 17 Smart Card Interface Start Initialization Start of transmission FER/ERS = 0? Error handling TEND = 1? Write transmit data to SCTDR1, and clear TDRE flag in SCSSR1 to 0 All data transmitted? FER/ERS = 0? Error handling TEND = 1? Clear TE bit in SCSCR1 to 0 End of transmission Figure 17.8 Sample Transmission Processing Flowchart...
Page 878 Section 17 Smart Card Interface Serial Data Reception: Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 17.9 shows a sample reception processing flowchart. 1. Perform smart card interface mode initialization as described in Initialization above. 2.
Page 879: Figure 17.9 Sample Reception Processing Flowchart
Section 17 Smart Card Interface Start Initialization Start of reception ORER = 0 and PER = 0? Error handling RDRF = 1? Read receive data from SCRDR1 and clear RDRF flag in SCSSR1 to 0 All data received? Clear RE bit in SCSCR1 to 0 End of reception Figure 17.9 Sample Reception Processing Flowchart Mode Switching Operation: When switching from receive mode to transmit mode, first confirm...
Page 880: Table 17.9 Smart Card Mode Operating States And Interrupt Sources
Section 17 Smart Card Interface Interrupt Operation: There are three interrupt sources in smart card interface mode, generating transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request cannot be used in this mode. When the TEND flag in SCSSR1 is set to 1, a TXI interrupt request is generated.
Page 881: Usage Notes
Section 17 Smart Card Interface When performing data transfer using the DMAC, it is essential to set and enable the DMAC before carrying out SCI settings. For details of the DMAC setting procedures, see section 14, Direct Memory Access Controller (DMAC). 17.4 Usage Notes The following points should be noted when using the SCI as a smart card interface.
Page 882 Section 17 Smart Card Interface The receive margin in smart card mode can therefore be expressed as shown in the following equation. | D – 0.5 | (1 + F) × 100% M = (0.5 – ) – (L – 0.5) F – M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 372) D: Clock duty cycle (D = 0 to 1.0)
Page 883: Figure 17.11 Retransfer Operation In Sci Receive Mode
Section 17 Smart Card Interface nth transfer frame Retransferred frame Transfer frame n+1 (DE) D1 D2 D3 D4 D5 D6 D7 Dp D0 D1 D5 D6 D7 Dp RDRF Figure 17.11 Retransfer Operation in SCI Receive Mode Retransfer Operation when SCI is in Transmit Mode: Figure 17.12 illustrates the retransfer operation when the SCI is in transmit mode.
Page 884: Figure 17.13 Procedure For Stopping And Restarting The Clock
Section 17 Smart Card Interface (3) Standby Mode and Clock When switching between smart card interface mode and standby mode, the following procedures should be used to maintain the clock duty cycle. Switching from Smart Card Interface Mode to Standby Mode: 1.
Page 885 Section 17 Smart Card Interface (4) Power-On and Clock The following procedure should be used to secure the clock duty cycle after powering on. 1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the potential.
Page 886 Section 17 Smart Card Interface Rev.7.00 Oct. 10, 2008 Page 802 of 1074 REJ09B0366-0700...
Page 887: Section 18 I/O Ports
Section 18 I/O Ports Section 18 I/O Ports 18.1 Overview This LSI has a 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port. 18.1.1 Features The features of the general-purpose I/O port are as follows: • 20-bit I/O port with input/output direction independently specifiable for each bit •...
Page 888: Block Diagrams
Section 18 I/O Ports 18.1.2 Block Diagrams Figure 18.1 shows a block diagram of the 16-bit general-purpose I/O port. PBnPUP Pull-up resistor PORTEN Internal bus Port 15 (input/ Dn output data output)/D47 Port 0 (input/ output)/D32 PDTRW DnDIR PBnIO Data input strobe Interrupt PTIRENn Dn input data...
Page 889: Figure 18.2 4-Bit Port
Section 18 I/O Ports Figure 18.2 shows a block diagram of the 4-bit general-purpose I/O port. PBnPUP Pull-up resistor PORTEN Internal bus Port 19 (input/ Dn output data output)/D51 Port 16 (input/ PDTRW output)/D48 DnDIR PBnIO Data input strobe Dn input data PORTEN 0: Port not available 1: Port available PBnPuP...
Page 890: Figure 18.3 Md0/Sck Pin
Section 18 I/O Ports SCI I/O port block diagrams are shown in figures 18.3 to 18.5. Reset SPB1IO Internal data bus SPTRW Reset MD0/SCK SPB1DT SPTRW Clock output enable signal Mode setting Serial clock output signal register Serial clock input signal Clock input enable signal SPTRR Legend:...
Page 891: Figure 18.4 Md7/Txd Pin
Section 18 I/O Ports Reset SPB0IO Internal data bus SPTRW Reset MD7/TxD SPB0DT Transmit enable signal SPTRW Mode setting register Serial transmit data Legend: SPTRW: Write to SPTR Figure 18.4 MD7/TxD Pin Serial receive data Internal data bus SPTRR Legend: Read SPTR Figure 18.5 RxD Pin Rev.7.00 Oct.
Page 892: Figure 18.6 Md1/Txd2 Pin
Section 18 I/O Ports SCIF I/O port block diagrams are shown in figures 18.6 to 18.9. Reset SPB2IO Internal data bus SPTRW Reset MD1/TxD2 SPB2DT SCIF Transmit enable SPTRW signal Mode setting register Serial transmit data Legend: SPTRW: Write to SPTR Figure 18.6 MD1/TxD2 Pin SCIF MD2/RxD2...
Page 893: Figure 18.8 Cts2 Pin
Section 18 I/O Ports Reset CTSIO Internal data bus SPTRW Reset CTS2 CTSDT SCIF SPTRW CTS2 signal Modem control enable signal* SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the CTS2 pin function. Figure 18.8 CTS2 Pin Rev.7.00 Oct.
Page 894: Figure 18.9 Md8/Rts2 Pin
Section 18 I/O Ports Reset RTSIO Internal data bus SPTRW Reset MD8/RTS2 RTSDT SCIF Modem control SPTRW enable signal* Mode setting register RTS2 signal SPTRR Legend: SPTRW: Write to SPTR SPTRR: Read SPTR Note: * MCE bit in SCFCR2: signal that designates modem control as the RTS2 pin function. Figure 18.9 MD8/RTS2 Pin Rev.7.00 Oct.
Page 895: Pin Configuration
Section 18 I/O Ports 18.1.3 Pin Configuration Table 18.1 shows the 20-bit general-purpose I/O port pin configuration. Table 18.1 20-Bit General-Purpose I/O Port Pins Pin Name Signal Function Port 19 pin PORT19/D51 I/O port Port 18 pin PORT18/D50 I/O port Port 17 pin PORT17/D49 I/O port...
Page 896: Table 18.2 Sci I/O Port Pins
Section 18 I/O Ports Table 18.2 shows the SCI I/O port pin configuration. Table 18.2 SCI I/O Port Pins Pin Name Abbreviation Function Serial clock pin MD0/SCK Clock input/output Receive data pin Input Receive data input Transmit data pin MD7/TxD Output Transmit data output Note: Pins MD0/SCK and MD7/TxD function as mode input pins MD0 and MD7 after a power-on...
Page 897: Register Configuration
Section 18 I/O Ports 18.1.4 Register Configuration The 20-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port have seven registers, as shown in table 18.4. Table 18.4 I/O Port Registers Area 7 Access Name Abbreviation R/W Initial Value* P4 Address Address Size Port control register A...
Page 898: Register Descriptions
Section 18 I/O Ports 18.2 Register Descriptions 18.2.1 Port Control Register A (PCTRA) Port control register A (PCTRA) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 16-bit port (port 15 pin to port 0 pin). As the initial value of port data register A (PDTRA) is undefined, all the bits in the 16-bit port should be set to output with PCTRA after writing a value to the PDTRA register.
Page 899: Port Data Register A (Pdtra)
Section 18 I/O Ports Bit 2n + 1 (n = 0–15)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 16- bit port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO.
Page 900: Port Control Register B (Pctrb)
Section 18 I/O Ports 18.2.3 Port Control Register B (PCTRB) Port control register B (PCTRB) is a 32-bit readable/writable register that controls the input/output direction and pull-up for each bit in the 4-bit port (port 19 pin to port 16 pin). As the initial value of port data register B (PDTRB) is undefined, each bit in the 4-bit port should be set to output with PCTRB after writing a value to the PDTRB register.
Page 901: Port Data Register B (Pdtrb)
Section 18 I/O Ports Bit 2n + 1 (n = 0–3)—Port Pull-Up Control (PBnPUP): Specifies whether each bit in the 4-bit port is to be pulled up with a built-in resistor. Pull-up is automatically turned off for a port pin set to output by bit PBnIO.
Page 902: Gpio Interrupt Control Register (Gpioic)
Section 18 I/O Ports 18.2.5 GPIO Interrupt Control Register (GPIOIC) The GPIO interrupt control register (GPIOIC) is a 16-bit readable/writable register that performs 16-bit interrupt input control. GPIOIC is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or in standby mode, and retains its contents.
Page 903: Serial Port Register (Scsptr1)
Section 18 I/O Ports 18.2.6 Serial Port Register (SCSPTR1) Bit: — — — SPB1IO SPB1DT SPB0IO SPB0DT Initial value: — — R/W: — — — The serial port register (SCSPTR1) is an 8-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCI) pins. Input data can be read from the RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0.
Page 904 Section 18 I/O Ports Bit 2—Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit.
Page 905: Serial Port Register (Scsptr2)
Section 18 I/O Ports 18.2.7 Serial Port Register (SCSPTR2) Bit: — — — — — — — — Initial value: R/W: Bit: RTSIO RTSDT CTSIO CTSDT — — SPB2IO SPB2DT Initial value: — — — R/W: The serial port register (SCSPTR2) is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins.
Page 906 Section 18 I/O Ports Bit 6—Serial Port RTS Port Data (RTSDT): Specifies the serial port RTS2 pin input/output data. Input or output is specified by the RTSIO pin (see the description of bit 7, RTSIO, for details). When the RTS2 pin is designated as an output, the value of the RTSDT bit is output to the RTS2 pin.
Page 907 Section 18 I/O Ports Bit 0—Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value of the SPB2DT bit is output to the TxD2 pin.
Page 908 Section 18 I/O Ports Rev.7.00 Oct. 10, 2008 Page 824 of 1074 REJ09B0366-0700...
Page 909: Section 19 Interrupt Controller (Intc)
Section 19 Interrupt Controller (INTC) Section 19 Interrupt Controller (INTC) 19.1 Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to user-set priority.
Page 910: Figure 19.1 Block Diagram Of Intc
Section 19 Interrupt Controller (INTC) Input control IRL3– IRL0 (Interrupt request) Interrupt Com- (Interrupt request) Priority request parator identifier (Interrupt request) (Interrupt request) SCIF IMASK (Interrupt request) (Interrupt request) (Interrupt request) DMAC (Interrupt request) H-UDI (Interrupt request) GPIO IPRA–IPRD INTPRI00 Bus interface INTC Legend:...
Page 911: Pin Configuration
Section 19 Interrupt Controller (INTC) 19.1.3 Pin Configuration Table 19.1 shows the INTC pin configuration. Table 19.1 INTC Pins Pin Name Abbreviation Function Nonmaskable interrupt Input Input of nonmaskable interrupt request input pin signal IRL3–IRL0 Interrupt input pins Input Input of interrupt request signals (maskable by IMASK in SR) 19.1.4 Register Configuration...
Page 912: Interrupt Sources
Section 19 Interrupt Controller (INTC) 2. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low. 3. SH7750S and SH7750R only 4. SH7750R only 19.2 Interrupt Sources There are three types of interrupt sources: NMI, RL, and on-chip peripheral modules. Each interrupt has a priority level (16–0), with level 16 as the highest and level 1 as the lowest.
Page 913: Irl Interrupts
Section 19 Interrupt Controller (INTC) 19.2.2 IRL Interrupts IRL interrupts are input by level at pins IRL3–IRL0. The priority level is the level indicated by pins IRL3–IRL0. An IRL3–IRL0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0).
Page 914: Table 19.3 Irl3-Irl0 Pins And Interrupt Levels
Section 19 Interrupt Controller (INTC) Table 19.3 IRL3–IRL0 Pins and Interrupt Levels IRL3 IRL2 IRL1 IRL0 Interrupt Priority Level Interrupt Request Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request Level 11 interrupt request Level 10 interrupt request Level 9 interrupt request Level 8 interrupt request...
Page 915: On-Chip Peripheral Module Interrupts
Section 19 Interrupt Controller (INTC) Table 19.4 SH7750 IRL3–IRL0 Pins and Interrupt Levels (When IRLM = 1) IRL3 IRL2 IRL1 IRL0 Interrupt Priority Level Interrupt Request IRL0 IRL1 IRL2 IRL3 19.2.3 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following nine modules: •...
Page 916: Interrupt Exception Handling And Priority
Section 19 Interrupt Controller (INTC) will secure the necessary timing internally. When updating a number of flags, there is no problem if only the register containing the last flag updated is read. If flag updating is performed while the BL bit is cleared to 0, the program may jump to the interrupt handling routine when the INTEVT register value is 0.
Page 917: Table 19.5 Interrupt Exception Handling Sources And Priority Order
Section 19 Interrupt Controller (INTC) Table 19.5 Interrupt Exception Handling Sources and Priority Order INTEVT Interrupt Priority IPR (Bit Priority within Default Interrupt Source Code (Initial Value) Numbers) IPR Setting Unit Priority H'1C0 — — High ↑ IRL3–IRL0 = 0 H'200 —...
Page 918 Section 19 Interrupt Controller (INTC) INTEVT Interrupt Priority IPR (Bit Priority within Default Interrupt Source Code (Initial Value) Numbers) IPR Setting Unit Priority TUNI3 * TMU3 H'B00 15–0 (0) INTPRI00 — High ↑ (11–8) ⏐ ⏐ TUNI4 * TMU4 H'B80 15–0 (0) INTPRI00 —...
Page 919: Register Descriptions
Section 19 Interrupt Controller (INTC) RCMI: Compare-match interrupt ROVI: Refresh counter overflow interrupt H-UDI: High-performance use debug interface GPIOI: I/O port interrupt DMTE0–DMTE7: DMAC transfer end interrupts DMAE: DMAC address error interrupt Notes: 1. Interrupt priority levels can only be changed in the SH7750S or SH7750R. In the SH7750, the initial values cannot be changed.
Page 920: Table 19.6 Interrupt Request Sources And Ipra-Iprd Registers
Section 19 Interrupt Controller (INTC) IPRD (SH7750S and SH7750R only) Bit: Initial value: R/W: Bit: Initial value: R/W: Table 19.6 shows the relationship between the interrupt request sources and the IPRA–IPRD register bits. Table 19.6 Interrupt Request Sources and IPRA–IPRD Registers Bits Register 15–12...
Page 921: Interrupt Control Register (Icr)
Section 19 Interrupt Controller (INTC) 19.3.2 Interrupt Control Register (ICR) The interrupt control register (ICR) is a 16-bit register that sets the input signal detection mode for external interrupt input pin NMI and indicates the input signal level at the NMI pin. This register is initialized by a power-on reset or manual reset.
Page 922 Section 19 Interrupt Controller (INTC) Bit 9—NMI Block Mode (NMIB): Specifies whether an NMI request is to be held pending or detected immediately while the SR.BL bit is set to 1. Bit 9: NMIB Description NMI interrupt requests held pending while SR.BL bit is set to 1 (Initial value) NMI interrupt requests detected while SR.BL bit is set to 1 Notes: 1.
Page 923: Interrupt-Priority-Level Setting Register 00 (Intpri00) (Sh7750R Only)
Section 19 Interrupt Controller (INTC) 19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only) The interrupt-priority-level setting register 00 (INTPRI00) sets the priority levels (levels 15−0) for the on-chip peripheral module interrupts. INTPRI00 is a 32-bit readable/writable register. It is initialized to H'00000000 by a reset, but is not initialized when the device enters standby mode. Bit: Initial value: R/W:...
Page 924: Interrupt Source Register 00 (Intreq00) (Sh7750R Only)
Section 19 Interrupt Controller (INTC) 19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only) The interrupt source register 00 (INTREQ00) indicates the origin of the interrupt request that has been sent to the INTC. The states of the bits in this register is not affected by masking of the corresponding interrupts by the settings in the INTPRI00 or INTMSK00 register.
Page 925: Interrupt Mask Register 00 (Intmsk00) (Sh7750R Only)
Section 19 Interrupt Controller (INTC) 19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only) The interrupt mask register 00 (INTMSK00) sets the masking of individual interrupt requests. INTMSK00 is a 32-bit register. It is initialized to H'000003FF by a reset, and retains this value in standby mode.
Page 926: Interrupt Mask Clear Register 00 (Intmskclr00) (Sh7750R Only)
Section 19 Interrupt Controller (INTC) 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only) The interrupt mask clear register 00 (INTMSKCLR00) clears the masking of individual interrupt requests. INTMSKCLR00 is a 32-bit write-only register. Bit: Initial value: — — — —...
Page 927: Intc Operation
Section 19 Interrupt Controller (INTC) 19.4 INTC Operation 19.4.1 Interrupt Operation Sequence The sequence of operations when an interrupt is generated is described below. Figure 19.3 shows a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2.
Page 928: Figure 19.3 Interrupt Operation Flowchart
Section 19 Interrupt Controller (INTC) Program execution state Interrupt generated? (BL bit in SR = 0) or (sleep or standby mode)? NMIB in ICR = 1 and NMI? NMI? Level 15 interrupt? Level 14 interrupt? IMASK * = level 14 or lower? Level 1 interrupt?
Page 929: Multiple Interrupts
Section 19 Interrupt Controller (INTC) 19.4.2 Multiple Interrupts When handling multiple interrupts, interrupt handling should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in the INTEVT register. The code in INTEVT can be used as a branch-offset for branching to the specific handler. 2.
Page 930: Interrupt Response Time
Section 19 Interrupt Controller (INTC) 19.5 Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception service routine is started (the interrupt response time) is shown in table 19.9. Table 19.9 Interrupt Response Time Number of States Peripheral...
Page 931: Usage Notes
Section 19 Interrupt Controller (INTC) 19.6 Usage Notes 19.6.1 NMI Interrupts (SH7750 and SH7750S Only) When multiple NMI interrupts are input to the NMI pin within a set period of time (which is dependent on the internal state of the CPU and the external bus state), subsequent interrupts may not be accepted.
Page 932 Section 19 Interrupt Controller (INTC) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; R0 : tmp ;; R1 : Original SR ;; R2 : Original ICR ;; R3 : ICR Address ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; NMIH: ; (1) Set SR.IMASK = H'F SR, R1 ; Store SR R1,R0 #H'F0,R0 R0, SR ;...
Page 933 Section 19 Interrupt Controller (INTC) R1, SR ; Restore SR NMIH3 NMIH1: NMIH2 NMIH3: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Rev.7.00 Oct. 10, 2008 Page 849 of 1074 REJ09B0366-0700...
Page 934 Section 19 Interrupt Controller (INTC) Rev.7.00 Oct. 10, 2008 Page 850 of 1074 REJ09B0366-0700...
Page 935: Section 20 User Break Controller (Ubc)
Section 20 User Break Controller (UBC) Section 20 User Break Controller (UBC) 20.1 Overview The user break controller (UBC) provides functions that simplify program debugging. When break conditions are set in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated by the CPU.
Page 936: Block Diagram
Section 20 User Break Controller (UBC) 20.1.2 Block Diagram Figure 20.1 shows a block diagram of the UBC. Access Address Data control Channel A Access BBRA comparator BARA Address BASRA comparator BAMRA Channel B Access BBRB comparator BARB Address BASRB comparator BAMRB BDRB...
Page 937: Table 20.1 Ubc Registers
Section 20 User Break Controller (UBC) Table 20.1 shows the UBC registers. Table 20.1 UBC Registers Area 7 Access Name Abbreviation Initial Value P4 Address Address Size Break address BARA Undefined H'FF200000 H'1F200000 register A Break address BAMRA Undefined H'FF200004 H'1F200004 mask register A...
Page 938: Register Descriptions
Section 20 User Break Controller (UBC) 20.2 Register Descriptions 20.2.1 Access to UBC Control Registers The access size must be the same as the control register size. If the sizes are different, a write will not be effected in a UBC register write operation, and a read operation will return an undefined value.
Page 939: Break Address Register A (Bara)
Section 20 User Break Controller (UBC) 20.2.2 Break Address Register A (BARA) Bit: BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 Initial value: R/W: Bit: BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 Initial value: R/W: Bit: BAA15 BAA14 BAA13 BAA12 BAA11 BAA10...
Page 940: Break Asid Register A (Basra)
Section 20 User Break Controller (UBC) 20.2.3 Break ASID Register A (BASRA) Bit: BASA7 BASA6 BASA5 BASA4 BASA3 BASA2 BASA1 BASA0 Initial value: R/W: Legend: *: Undefined Break ASID register A (BASRA) is an 8-bit readable/writable register that specifies the ASID used in the channel A break conditions.
Page 941: Break Bus Cycle Register A (Bbra)
Section 20 User Break Controller (UBC) Bits 3, 1, and 0—Break Address Mask A2 to A0 (BAMA2–BAMA0): These bits specify which bits of the channel A break address 31 to 0 (BAA31–BAA0) set in BARA are to be masked. Bit 3: BAMA2 Bit 1: BAMA1 Bit 0: BAMA0 Description...
Page 942 Section 20 User Break Controller (UBC) Bits 5 and 4—Instruction Access/Operand Access Select A (IDA1, IDA0): These bits specify whether an instruction access cycle or an operand access cycle is used as the bus cycle in the channel A break conditions. Bit 5: IDA1 Bit 4: IDA0 Description...
Page 943: Break Address Register B (Barb)
Section 20 User Break Controller (UBC) 20.2.6 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 20.2.7 Break ASID Register B (BASRB) BASRB is the channel B break ASID register. The bit configuration is the same as for BASRA. 20.2.8 Break Address Mask Register B (BAMRB) BAMRB is the channel B break address mask register.
Page 944: Break Data Mask Register B (Bdmrb)
Section 20 User Break Controller (UBC) Break data register B (BDRB) is a 32-bit readable/writable register that specifies the data (bits 31– 0) to be used in the channel B break conditions. BDRB is not initialized by a power-on reset or manual reset.
Page 945: Break Bus Cycle Register B (Bbrb)
Section 20 User Break Controller (UBC) Bits 31 to 0—Break Data Mask B31 to B0 (BDMB31–BDMB0): These bits specify whether the corresponding bit of the channel B break data B31 to B0 (BDB31–BDB0) set in BDRB is to be masked. Bit 31–0: BDMBn Description Channel B break data bit BDBn is included in break conditions...
Page 946 Section 20 User Break Controller (UBC) value of the PCBA, DBEB, PCBB, and SEQ bits is undefined after a power-on reset or manual reset, so these bits should be initialized by software as necessary. Bit 15—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is satisfied.
Page 947 Section 20 User Break Controller (UBC) Bit 7—Data Break Enable B (DBEB): Specifies whether the data bus condition is to be included in the channel B break conditions. This bit is not initialized by a power-on reset or manual reset. Bit 7: DBEB Description Data bus condition is not included in channel B conditions...
Page 948: Operation
Section 20 User Break Controller (UBC) 20.3 Operation 20.3.1 Explanation of Terms Relating to Accesses An instruction access is an access that obtains an instruction. An operand access is any memory access for the purpose of instruction execution. For example, the access to address PC+disp×2+4 in the instruction MOV.W @(disp,PC), Rn (an access very close to the program counter) is an operand access.
Page 949: User Break Operation Sequence
Section 20 User Break Controller (UBC) • Example of sequence of instructions with a branch (however, the example of a sequence of instructions with no branch should be applied when the branch destination of a delayed branch instruction is the instruction itself + 4): 100 Instruction A: BT/S L200 (0 instructions after instruction A) 102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B) L200 200 Instruction C (3 instructions after instruction A, 2 instructions after instruction B)
Page 950: Instruction Access Cycle Break
Section 20 User Break Controller (UBC) register to clear the flags to 0. See section 20.3.6, Condition Match Flag Setting, for the exact setting conditions for the condition match flags. 4. When sequential condition mode has been selected, and the channel B condition is matched after the channel A condition has been matched, a break is effected at the instruction at which the channel B condition was matched.
Page 951: Operand Access Cycle Break
Section 20 User Break Controller (UBC) 4. When an instruction access cycle is set for channel B, break data register B (BDRB) is ignored in judging whether there is an instruction access match. Therefore, a break condition specified by the DBEB bit in BRCR is not executed. 20.3.5 Operand Access Cycle Break 1.
Page 952: Condition Match Flag Setting
Section 20 User Break Controller (UBC) 20.3.6 Condition Match Flag Setting 1. Instruction access with post-execution condition, or operand access The flag is set when execution of the instruction that causes the break is completed. As an exception to this, however, in the case of an instruction with more than one operand access the flag may be set on detection of the match condition alone, without waiting for execution of the instruction to be completed.
Page 953: Contiguous A And B Settings For Sequential Conditions
Section 20 User Break Controller (UBC) instructions ahead of the branch instruction (when the branch is not made). In this case, the PC value saved to SPC is the address of the branch destination (when the branch is made) or the instruction following the delay slot instruction (when the branch is not made).
Page 954: Usage Notes
Section 20 User Break Controller (UBC) 2. Instruction access match on channel A, operand access match on channel B Instruction B is 0 or 1 instruction after Sequential operation is not guaranteed. instruction A Instruction B is 2 or more instructions Sequential operation is guaranteed.
Page 955 Section 20 User Break Controller (UBC) Pre- Post- Pre- Post- Execution Execution Execution Execution Instruction Instruction Instruction Instruction Operand Access SL.BL Access Access Access Access (Address/Data) 0 → 0 1 → 0 0 → 1 1 → 1 Legend: A: Accepted M: Masked e.
Page 956: User Break Debug Support Function
Section 20 User Break Controller (UBC) execution break is suppressed in accordance with the priorities of the two events. For example, in the case of contention between a TRAPA instruction and a post-execution break, the user break is suppressed. However, in this case, the CMF bit is set by the occurrence of the break condition.
Page 957: Figure 20.2 User Break Debug Support Function Flowchart
Section 20 User Break Controller (UBC) Exception/interrupt generation Hardware operation SPC ← PC SSR ← SR SR.BL ← B'1 SR.MD ← B'1 SR.RB ← B'1 Exception Trap Exception/ interrupt/trap? Interrupt EXPEVT ← H'160 EXPEVT ← exception code INTEVT ← interrupt code TRA ←...
Page 958: Examples Of Use
Section 20 User Break Controller (UBC) 20.5 Examples of Use Instruction Access Cycle Break Condition Settings • Register settings: BASRA = H'80 / BARA = H'00000404 / BAMRA = H'00 / BBRA = H'0014 / BASRB = H'70 / BARB = H'00008010 / BAMRB = H'01 / BBRB = H'0014 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0400 Conditions set: Independent channel A/channel B mode ⎯...
Page 959 Section 20 User Break Controller (UBC) Conditions set: Independent channel A/channel B mode ⎯ Channel A: ASID: H'80 / address: H'00027128 / address mask: H'00 Bus cycle: CPU, instruction access (pre-instruction-execution), write, word ⎯ Channel B: ASID: H'70 / address: H'00031415 / address mask: H'00 Data: H'00000000 / data mask: H'00000000 Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not included in conditions)
Page 960: User Break Controller Stop Function
Section 20 User Break Controller (UBC) 20.6 User Break Controller Stop Function In the SH7750S, this function stops the clock supplied to the user break controller and is used to minimize power dissipation when the chip is operating. Note that, if you use this function, you cannot use the user break controller.
Page 961: Examples Of Stopping And Restarting The User Break Controller
Section 20 User Break Controller (UBC) 20.6.3 Examples of Stopping and Restarting the User Break Controller The following are example programs: ; Transition to user break controller stopped state ; (1) Initialize BBRA and BBRB to 0. #0, R0 mov.l #BBRA, R1 mov.w R0, @R1...
Page 962 Section 20 User Break Controller (UBC) Rev.7.00 Oct. 10, 2008 Page 878 of 1074 REJ09B0366-0700...
Page 963: Section 21 High-Performance User Debug Interface (H-Udi)
Section 21 High-performance User Debug Interface (H-UDI) Section 21 High-performance User Debug Interface (H-UDI) 21.1 Overview 21.1.1 Features The high-performance user debug interface (H-UDI) is a serial input/output interface supporting a subset of the JTAG, IEEE 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture.
Page 964: Figure 21.1 Block Diagram Of H-Udi Circuit
Section 21 High-performance User Debug Interface (H-UDI) Interrupt/reset etc. Break ASEBRK/BRKACK control Decoder controller TRST SDIR SDINT SDDRH SDDRL Note: * Provided only in the SH7750R. Figure 21.1 Block Diagram of H-UDI Circuit Rev.7.00 Oct. 10, 2008 Page 880 of 1074 REJ09B0366-0700...
Page 965: Pin Configuration
Section 21 High-performance User Debug Interface (H-UDI) 21.1.3 Pin Configuration Table 21.1 shows the H-UDI pin configuration. Table 21.1 H-UDI Pins When Not Pin Name Abbreviation I/O Function Used Open * Clock pin Input Same as the JTAG serial clock input pin. Data is transferred from data input pin TDI to the H- UDI circuit, and data is read from data output pin TDO, in synchronization with this signal.
Page 966: Register Configuration
Section 21 High-performance User Debug Interface (H-UDI) the rating of the pull-up resistor. Although this current has no effect on the chip's operation, unnecessary current will be dissipated. The maximum frequency of TCK (TMS, TDI, TDO) is 20 MHz. Make the TCK or CPG setting of this LSI such that the TCK frequency is lower than that of this LSI’s on-chip peripheral module clock.
Page 967: Register Descriptions
Section 21 High-performance User Debug Interface (H-UDI) 21.2 Register Descriptions 21.2.1 Instruction Register (SDIR) The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is initialized by the TRST pin or in the TAP Test-Logic-Reset state.
Page 968 Section 21 High-performance User Debug Interface (H-UDI) Bits 11 to 0—Reserved: These bits are always read as 1, and should only be written with 1. SH7750R: Bit: Initial value: R/W: Bit: — — — — — — — — Initial value: R/W: Bits 15 to 8—Test Instruction Bits (TI7–TI0) Bit 15:...
Page 969: Data Register (Sddr)
Section 21 High-performance User Debug Interface (H-UDI) 21.2.2 Data Register (SDDR) The data register (SDDR) is a 32-bit register, comprising the two 16-bit registers SDDRH and SDDRL, that can be read and written to by the CPU. The value in this register is not initialized by a TRST or CPU reset.
Page 970: Interrupt Source Register (Sdint) (Sh7750R Only)
Section 21 High-performance User Debug Interface (H-UDI) 21.2.4 Interrupt Source Register (SDINT) (SH7750R Only) The interrupt source register (SDINT) is a 16-bit register that can be read from and written to by the CPU. From the H-UDI pins, the INTREQ bit is set to 1 when a H-UDI interrupt command is set in the SDIR register (Update-IR).
Page 971: Boundary Scan Register (Sdbsr) (Sh7750R Only)
Section 21 High-performance User Debug Interface (H-UDI) 21.2.5 Boundary Scan Register (SDBSR) (SH7750R Only) The boundary scan register (SDBSR) is a shift register that is placed on the pads to control the chip's I/O pins. This register can perform a boundary scan test equivalent to the JTAG (IEEE Std 1149.1) standard using EXTEST, SAMPLE, and PRELOAD commands.
Page 972: Table 21.3 Configuration Of The Boundary Scan Register
Section 21 High-performance User Debug Interface (H-UDI) Table 21.3 Configuration of the Boundary Scan Register Pin Name Type Pin Name Type Pin Name Type to TDO CKIO2ENB MD6/IOIS16 STATUS1 SCK2/MRESET STATUS1 SCK2/MRESET STATUS0 SCK2/MRESET STATUS0 MD7/TXD MD7/TXD MD7/TXD MD8/RTS2 MD8/RTS2 DACK1 MD8/RTS2 DACK1...
Page 973 Section 21 High-performance User Debug Interface (H-UDI) Pin Name Type Pin Name Type Pin Name Type DRAK1 DREQ1 DREQ0 WE7/CAS7/DQM7/REG WE7/CAS7/DQM7/REG WE6/CAS6/DQM6 WE6/CAS6/DQM6 WE3/CAS3/DQM3/ICIOWR CTL WE3/CAS3/DQM3/ICIOWR OUT WE2/CAS2/DQM2/ICIORD CTL WE2/CAS2/DQM2/ICIORD OUT RD/WR RD/WR RD/CASS/FRAME RD/CASS/FRAME WE0/CAS0/DQM0 WE0/CAS0/DQM0 WE1/CAS1/DQM1 WE1/CAS1/DQM1 DRAK0 WE4/CAS4/DQM4 DRAK0 WE4/CAS4/DQM4...
Page 974 Section 21 High-performance User Debug Interface (H-UDI) Pin Name Type Pin Name Type Pin Name Type WE5/CAS5/DQM5 WE5/CAS5/DQM5 BREQ/BSACK BACK/BSREQ BACK/BSREQ from TDI Note: CTL is an active-low signal. The relevant pin is driven to the OUT state when CTL is set LOW.
Page 975: Operation
Section 21 High-performance User Debug Interface (H-UDI) 21.3 Operation 21.3.1 TAP Control Figure 21.2 shows the internal states of the TAP control circuit. These conform to the state transitions specified by JTAG. • The transition condition is the TMS value at the rising edge of TCK. •...
Page 976: H-Udi Reset
Section 21 High-performance User Debug Interface (H-UDI) 21.3.2 H-UDI Reset A power-on reset is effected by an SDIR command. A reset is effected by sending an H-UDI reset assert command, and then sending an H-UDI reset negate command, from the H-UDI pin (see figure 21.3).
Page 977: Boundary Scan (Extest, Sample/Preload, Bypass) (Sh7750R Only)
Section 21 High-performance User Debug Interface (H-UDI) except by the following operations: update in the Update-IR state, initialization in the Test-Logic- Reset state, and initialization by assertion of TRST. 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only) In the SH7750R, setting a command from the H-UDI in SDIR can place the H-UDI pins in the boundary scan mode.
Page 978 Section 21 High-performance User Debug Interface (H-UDI) 6. In BYPASS mode on the SH7750 or SH7750S, the contents of the bypass register (SDBPR) are undefined in the Capture-DR state. On the SH7750R, SDBPR has a value of 0. Rev.7.00 Oct. 10, 2008 Page 894 of 1074 REJ09B0366-0700...
Page 979: Section 22 Electrical Characteristics
Section 22 Electrical Characteristics Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 Absolute Maximum Ratings Item Symbol Value Unit –0.3 to 4.2, –0.3 to 4.6 * I/O, PLL, RTC, CPG power supply voltage DD-PLL1/2 DD-RTC DD-CPG –0.3 to 2.5, –0.3 to 2.1 * Internal power supply voltage Input voltage –0.3 to V...
Page 980: Dc Characteristics
Section 22 Electrical Characteristics 22.2 DC Characteristics Table 22.2 DC Characteristics (HD6417750RBP240 (V), HD6417750RBG240 (V)) = –20 to +75°C Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC Normal mode, sleep mode, deep sleep mode, standby mode Current...
Page 981 Section 22 Electrical Characteristics Item Symbol Unit Test Conditions μA Three-state I/O, all |Isti| — — = 0.5 to V leakage output pins –0.5 V current (off state) Output All output — — = –2 mA voltage pins — — 0.55 = 2 mA Pull-up...
Page 982: Table 22.3 Dc Characteristics (Hd6417750Rf240 (V))
Section 22 Electrical Characteristics Table 22.3 DC Characteristics (HD6417750RF240 (V)) = –20 to +75°C Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC Normal mode, sleep mode, deep sleep mode, standby mode Current Normal...
Page 983 Section 22 Electrical Characteristics Item Symbol Unit Test Conditions Output All output — — = –2 mA voltage pins — — 0.55 = 2 mA Pull-up All pull-up kΩ pull resistance resistance All pins — — capacitance Notes: Connect V , and V to V , and V...
Page 984: Table 22.4 Dc Characteristics (Hd6417750Rbp200 (V), Hd6417750Rbg200 (V))
Section 22 Electrical Characteristics Table 22.4 DC Characteristics (HD6417750RBP200 (V), HD6417750RBG200 (V)) = –20 to +75°C Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC 1.35 Normal mode, sleep mode, deep sleep mode, standby mode Current...
Page 985 Section 22 Electrical Characteristics Item Symbol Unit Test Conditions Output All output — — = –2 mA voltage pins — — 0.55 = 2 mA Pull-up All pull-up kΩ pull resistance resistance All pins — — capacitance Notes: Connect V , and V to V , and connect V...
Page 986: Table 22.5 Dc Characteristics (Hd6417750Rf200 (V))
Section 22 Electrical Characteristics Table 22.5 DC Characteristics (HD6417750RF200 (V)) = –20 to +75°C Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC 1.35 Normal mode, sleep mode, deep sleep mode, standby mode Current Normal...
Page 987 Section 22 Electrical Characteristics Item Symbol Unit Test Conditions Output All output — — = –2 mA voltage pins — — 0.55 = 2 mA Pull-up All pull-up kΩ pull resistance resistance All pins — — capacitance Notes: Connect V , and V to V , and V...
Page 988: Table 22.6 Dc Characteristics (Hd6417750Sbp200 (V))
Section 22 Electrical Characteristics Table 22.6 DC Characteristics (HD6417750SBP200 (V)) = –20 to +75°C Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC 1.95 2.07 Normal mode, sleep mode, deep sleep mode, standby mode Current Normal...
Page 989 Section 22 Electrical Characteristics Item Symbol Unit Test Conditions Pull-up All pull-up kΩ pull resistance resistance All pins — — capacitance Notes: Connect V , and V to V , and V , and V to GND, DD-PLL1/2 DD-RTC DD-CPG SS-CPG SS-PLL1/2 SSQ-RTC...
Page 990: Table 22.7 Dc Characteristics (Hd6417750Sf200 (V))
Section 22 Electrical Characteristics Table 22.7 DC Characteristics (HD6417750SF200 (V)) = –20 to +75°C Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC 1.95 2.07 Normal mode, sleep mode, deep sleep mode, standby mode Current Normal...
Page 991 Section 22 Electrical Characteristics Item Symbol Unit Test Conditions Pull-up All pull-up kΩ pull resistance resistance All pins — — capacitance Notes: Connect V , and V to V , and V , and V to GND, DD-PLL1/2 DD-RTC DD-CPG SS-CPG SS-PLL1/2 SSQ-RTC...
Page 992: Table 22.8 Dc Characteristics (Hd6417750Bp200M (V))
Section 22 Electrical Characteristics Table 22.8 DC Characteristics (HD6417750BP200M (V)) = –20 to +75°C Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC 1.95 2.07 Normal mode, sleep mode, deep sleep mode, standby mode Current Normal...
Page 993 Section 22 Electrical Characteristics Notes: Connect V , and V to V , and V , and V to GND, DD-PLL1/2 DD-RTC DD-CPG SS-CPG SS-PLL1/2 SSQ-RTC regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for V min = V –...
Page 994: Table 22.9 Dc Characteristics (Hd6417750Sf167 (V))
Section 22 Electrical Characteristics Table 22.9 DC Characteristics (HD6417750SF167 (V)) = –20 to +75°C Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC Normal mode, sleep mode, deep sleep mode, standby mode Current Normal...
Page 995 Section 22 Electrical Characteristics Item Symbol Unit Test Conditions Pull-up All pull-up kΩ pull resistance resistance All pins — — capacitance Notes: Connect V , and V to V , and V , and V to GND, DD-PLL1/2 DD-RTC DD-CPG SS-CPG SS-PLL1/2 SSQ-RTC...
Page 996: Table 22.10 Dc Characteristics (Hd6417750F167 (V))
Section 22 Electrical Characteristics Table 22.10 DC Characteristics (HD6417750F167 (V)) = –20 to +75°C Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC Normal mode, sleep mode, deep sleep mode, standby mode Current Normal...
Page 997 Section 22 Electrical Characteristics Notes: Connect V , and V to V , and V , and V to GND, DD-PLL1/2 DD-RTC DD-CPG SS-CPG SS-PLL1/2 SSQ-RTC regardless of whether or not the PLL circuits and RTC are used. The current dissipation values are for V min = V –...
Page 998: Table 22.11 Dc Characteristics (Hd6417750Svf133 (V))
Section 22 Electrical Characteristics Table 22.11 DC Characteristics (HD6417750SVF133 (V)) = –20 to +75°C Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC Normal mode, sleep mode, deep sleep mode, standby mode Current Normal...
Page 999 Section 22 Electrical Characteristics Item Symbol Unit Test Conditions Pull-up All pull-up kΩ pull resistance resistance All pins — — capacitance Notes: Connect V , and V to V , and V , and V to GND, DD-PLL1/2 DD-RTC DD-CPG SS-CPG SS-PLL1/2 SSQ-RTC...
Page 1000: Table 22.12 Dc Characteristics (Hd6417750Svbt133 (V))
Section 22 Electrical Characteristics Table 22.12 DC Characteristics (HD6417750SVBT133 (V)) = –30 to +70°C Item Symbol Unit Test Conditions Power supply Normal mode, sleep voltage mode, deep sleep DD-PLL1/2 mode, standby mode DD-CPG DD-RTC Normal mode, sleep mode, deep sleep mode, standby mode Current Normal...

This manual is also suitable for:

Sh7750Sh7750s Sh7750r

Renesas SH7750 Series Hardware Manual

Quick Links

Related Manuals for Renesas SH7750 Series

Summary of Contents for Renesas SH7750 Series