Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7706 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series SH7706 HD6417706F HD6417706BP Rev. 5.00 Revision Date: May 29, 2006...
Page 2 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 3: General Precautions On Handling Of Product
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 4: Table Of Contents
Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents.
Page 5: Preface
Preface The SH7706 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems.
Page 6 Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ SH7706 manuals: Document Title Document No. SH7706 Hardware Manual This manual SH-3/SH-3E/SH3-DSP Programming Manual...
Page 7 Abbreviations ACIA Asynchronous Communication Interface Adapter Analog to Digital Converter Advanced User Debugger Bus State Controller Clock Pulse Generator Compare Match Timer Digital to Analog Converter Direct Memory Access DMAC Direct Memory Access Controller DRAM Dynamic Random Access Memory Elementary Time Unit FIFO First-In First-Out H-UDI...
Page 8 Rev. 5.00 May 29, 2006 page viii of xlviii...
Page 9 Main Revisions for This Edition Item Page Revision (See Manual for Details) 1.3 Pin Assignment Figure amended Figure 1.2 Pin Assignment (FP-176C) AN[0]/PTJ[0] INDEX MARK AN[1]/PTJ[1] AN[2]/DA[1]/PTJ[2] AN[3]/DA[0]/PTJ[3] 1.4 Pin Function Table amended Number of Pins FP-176C TBP-208A Pin Name Description AUDATA[0]/PTF[0] AUD data / input/output port F...
Page 10 Item Page Revision (See Manual for Details) 6.3.2 IRQ Interrupt Description amended When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1 from the corresponding bit in IRR0, then write 0 to the bit. It is not necessary to clear the bit to 0 when using level-sensing.
Page 11 Item Page Revision (See Manual for Details) 6.4.4 Interrupt Table amended Request Register 0 Bit Name Initial Value R/W Description (IRR0) IRQ2R IRQ2 Interrupt Request Indicates whether an interrupt request is input to the IRQ2 pin. When edge detection mode is set for IRQ2, an interrupt request is cleared by clearing the IRQ2R bit.
Page 12 Item Page Revision (See Manual for Details) 8.4.6 PCMCIA Table title amended Control Register (PCR) Table 8.10 Area 6 Wait Control (PCMCIA I/F) 8.5.4 Synchronous Description added DRAM Interface If an external bus access request (in order to perform 2) below conflicts with an auto-refresh request, self-refresh request, or bus release request internal to the LSI under the following conditions, SDRAM all-bank precharge may not be executed...
Page 13 Item Page Revision (See Manual for Details) 8.5.4 Synchronous Figure amended and note added DRAM Interface TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 Figure 8.27 CKIO Synchronous DRAM A15 to A13 Mode Write Timing or (A14 to A12) * A11 (A10) * A12 (A11) * A10 to A2...
Page 14 Item Page Revision (See Manual for Details) 9.5.2 Register Description amended Description The compare match timer control/status register (CMCSR) is a Compare Match Timer 16-bit register that indicates the occurrence of compare Control/Status matches, and establishes the clock used for Register (CMCSR) incrementation.
Page 15 Item Page Revision (See Manual for Details) 9.6.1 Example of Table amended DMA Transfer between Items Address reload on Address reload off A/D Converter and SAR_2 H'04000080 H'04000090 External Memory DAR_2 H'003FFFF0 H'003FFFF0 DMATCR_2 H'0000007C H'0000007C (Address Reload on) Table 9.7 Values in the DMAC after the Fourth Transfer Ends 9.7 Cautions...
Page 16 Item Page Revision (See Manual for Details) 10.3 Clock Operating 308, Table amended and note 1 added Modes Clock Rate * Clock CKIO Frequency Mode FRQCR * PLL1 PLL2 (I:B:P) Range Input Frequency Range Table 10.3 Available Combination of Clock Notes: 1.
Page 17 Item Page Revision (See Manual for Details) 14.3.8 SC Port Table amended Control Register Bit Name Initial Value Description (SCPCR) SCP5MD1 See section 17.1.10, SC Port Control Register (SCPCR). SCP5MD0 SCP4MD1 SCP4MD0 SCP3MD1 SCP3MD0 SCP2MD1 SCP2MD0 16.1 Feature Figure amended Figure 16.1 SCIF SCPCR Block Diagram...
Page 18 Item Page Revision (See Manual for Details) Section 17 Pin Table amended Function Controller Port Function Other Function Port (Related Module) (Related Module) (PFC) PTF2 I/O (port) AUDATA[2] I/O (AUD) Table 17.1 List of PTF1 input (port) AUDATA[1] I/O (AUD) Multiplexed Pins PTF0 I/O (port) AUDATA[0] I/O (AUD)
Page 19 Item Page Revision (See Manual for Details) Section 22 Power- Table amended and note 5 added Down Modes State On-Chip Table 22.1 Power- Transition Reg- On-Chip Peripheral External Canceling Mode Conditions ister Memory Modules Pins Memory Procedure Down Modes Module Set MSTP bit of Runs Runs Held...
Page 20 Item Page Revision (See Manual for Details) 24.3.6 Synchronous Figure amended and note added DRAM Timing TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 CKIO Figure 24.39 Synchronous DRAM Mode Register Write A11 (A10) * Cycle A12 (A11) * A10 to A2 (A9 to A1) * CSD3 CSD3...
Page 21 Item Page Revision (See Manual for Details) B.1 Pin Functions Table amended and note 12 added Reset Power-Down Table B.1 Pin States Power-On Manual during Resets, Power- Category Reset Reset Standby Sleep Released Down States, and Bus- Clock EXTAL Released State XTAL IO * IO *...
Page 22 Item Page Revision (See Manual for Details) C. Product Lineup Table amended Model Marking Package HD6417706F133 176-pin plastic LQFP (FP-176C/PLQP0176KD-A) HD6417706BP133 208-pin TFBGA (TBP-208A/TTBG0208JA-A) D. Package Figure replaced Dimensions Figure D.1 Package Dimensions (FP-176C/ PLQP0176KD-A) Figure D.2 Package Figure replaced Dimensions (TBP-208A/ TTBG0208JA-A)
Page 23: Contents
Contents Section 1 Overview ......................Feature ..........................Block Diagram ........................Pin Assignment ......................... Pin Function ........................Section 2 CPU ........................13 Register Description......................13 2.1.1 Privileged Mode and Banks ................. 13 2.1.2 General Registers ....................15 2.1.3 System Registers....................16 2.1.4 Control Registers ....................
Page 24 3.3.3 TLB Address Comparison ................... 63 3.3.4 Page Management Information................65 MMU Functions........................ 66 3.4.1 MMU Hardware Management ................66 3.4.2 MMU Software Management ................66 3.4.3 MMU Instruction (LDTLB)................. 67 3.4.4 Avoiding Synonym Problems ................68 MMU Exceptions......................70 3.5.1 TLB Miss Exception ....................
Page 25 4.4.2 General Exceptions ....................92 4.4.3 Interrupts......................95 Usage Note........................97 Section 5 Cache ........................99 Feature ..........................99 5.1.1 Cache Structure....................99 Register Description......................101 5.2.1 Cache Control Register (CCR) ................101 5.2.2 Cache Control Register 2 (CCR2)................ 102 Operation ..........................
Page 26 Interrupt Response Time....................135 Section 7 User Break Controller ..................139 Feature ..........................139 Register Description......................141 7.2.1 Break Address Register A (BARA) ..............141 7.2.2 Break Address Mask Register A (BAMRA)............142 7.2.3 Break Bus Cycle Register A (BBRA) ..............142 7.2.4 Break Address Register B (BARB)..............
Page 27 8.4.7 Synchronous DRAM Mode Register (SDMR) ............ 193 8.4.8 Refresh Timer Control/Status Register (RTCSR) ..........193 8.4.9 Refresh Timer Counter (RTCNT)................ 196 8.4.10 Refresh Time Constant Register (RTCOR) ............196 8.4.11 Refresh Count Register (RFCR) ................197 Operation .......................... 197 8.5.1 Endian/Access Size and Data Alignment.............
Page 28 9.6.2 Example of DMA Transfer between External Memory and SCIF Transmitter (Indirect Address on) ................... 299 Cautions ..........................301 Section 10 Clock Pulse Generator (CPG) ..............303 10.1 Feature ..........................303 10.2 Input/Output Pin........................ 306 10.3 Clock Operating Modes ....................306 10.4 Register Description......................
Page 29 12.5.1 Status Flag Set Timing..................337 12.5.2 Status Flag Clear Timing ..................337 12.5.3 Interrupt Sources and Priorities................338 12.6 Usage Note........................338 12.6.1 Writing to Registers ..................... 338 12.6.2 Reading Registers ....................338 Section 13 Realtime Clock (RTC) .................. 339 13.1 Feature ..........................
Page 30 14.3 Register Description......................367 14.3.1 Receive Shift Register (SCRSR)................368 14.3.2 Receive Data Register (SCRDR) ................. 368 14.3.3 Transmit Shift Register (SCTSR) ................ 368 14.3.4 Transmit Data Register (SCTDR)................ 368 14.3.5 Serial Mode Register (SCSMR)................369 14.3.6 Serial Control Register (SCSCR)................. 372 14.3.7 Serial Status Register (SCSSR)................
Page 31 16.3.5 Serial Mode Register 2 (SCSMR2)..............447 16.3.6 Serial Control Register 2 (SCSCR2)..............449 16.3.7 Serial Status Register 2 (SCSSR2)............... 452 16.3.8 Bit Rate Register 2 (SCBRR2)................460 16.3.9 FIFO Control Register 2 (SCFCR2) ..............466 16.3.10 FIFO Data Count Set Register 2 (SCFDR2) ............468 16.3.11 SC Port Control Register (SCPCR)..............
Page 32 18.5.2 Port E Data Register (PEDR)................516 18.6 Port F..........................517 18.6.1 Register Description..................... 517 18.6.2 Port F Data Register (PFDR) ................518 18.7 Port G..........................519 18.7.1 Register Description..................... 519 18.7.2 Port G Data Register (PGDR) ................520 18.8 Port H..........................521 18.8.1 Register Description.....................
Page 33 Section 20 D/A Converter (DAC) .................. 549 20.1 Feature ..........................549 20.2 Input/Output Pin........................ 550 20.3 Register Description......................550 20.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)..........550 20.3.2 D/A Control Register (DACR) ................550 20.4 Operation .......................... 552 Section 21 User Debugging Interface (H-UDI) ............
Page 34: List Of Registers
Section 23 List of Registers ....................585 23.1 Register Address Map ....................... 585 23.2 Register Bits........................591 23.3 Register States in Processing Mode .................. 602 Section 24 Electrical Characteristics ................607 24.1 Absolute Maximum Ratings ..................... 607 24.2 DC Characteristics ......................609 24.3 AC Characteristics ......................
Page 35 Figures Section 1 Overview Figure 1.1 SH7706 Block Diagram..................Figure 1.2 Pin Assignment (FP-176C) .................. Figure 1.3 Pin Assignment (TBP-208A) ................Section 2 CPU Figure 2.1 Register Configuration..................14 Figure 2.2 General Registers ....................15 Figure 2.3 System Registers....................16 Figure 2.4 Control Registers ....................
Page 36 Section 6 Interrupt Controller (INTC) Figure 6.1 INTC Block Diagram................... 114 Figure 6.2 Example of IRL Interrupt Connection ..............117 Figure 6.3 Interrupt Operation Flowchart ................134 Figure 6.4 Example of Pipeline Operations when IRL Interrupt Is Accepted....... 138 Section 7 User Break Controller Figure 7.1 Block Diagram of User Break Controller ............
Page 37 Figure 8.31 Example of PCMCIA Interface................238 Figure 8.32 Basic Timing for PCMCIA Memory Card Interface ........... 239 Figure 8.33 Wait Timing for PCMCIA Memory Card Interface..........240 Figure 8.34 Basic Timing for PCMCIA Memory Card Interface Burst Access...... 241 Figure 8.35 Wait Timing for PCMCIA Memory Card Interface Burst Access.......
Page 38 Figure 9.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)........286 Figure 9.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles)........286 Figure 9.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4 Cycles) ......... 286 Figure 9.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) 287 Figure 9.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles)........
Page 39 Figure 13.3 Reading the Time....................358 Figure 13.4 Using the Alarm Function..................359 Figure 13.5 Example of Crystal Oscillator Circuit Connection ..........360 Figure 13.6 Using Periodic Interrupt Function................ 361 Section 14 Serial Communication Interface (SCI) Figure 14.1 SCI Block Diagram....................364 Figure 14.2 SCPT[1]/SCK0 Pin ....................
Page 40 Figure 15.10 Retransmission in SCI Transmit Mode ..............440 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.1 SCIF Block Diagram.................... 442 Figure 16.2 SCPT[3]/SCK2 Pin ....................443 Figure 16.3 SCPT[2]/TxD2 Pin....................444 Figure 16.4 SCPT[2]/RxD2 Pin ....................444 Figure 16.5 Sample SCIF Initialization Flowchart..............
Page 41: Electrical Characteristics
Figure 19.8 A/D Conversion Timing ..................544 Figure 19.9 External Trigger Input Timing................545 Figure 19.10 Definitions of A/D Conversion Accuracy............546 Figure 19.11 Example of Analog Input Protection Circuit ............547 Figure 19.12 Analog Input Pin Equivalent Circuit..............547 Section 20 D/A Converter (DAC) Figure 20.1 D/A Converter Block Diagram ................
Page 42 Figure 24.9 PLL Synchronization Settling Time at the Returning from Standby Mode (Return by IRQ/IRL Interrupt)................617 Figure 24.10 PLL Synchronization Settling Time when Frequency Multiplication Rate Modified ...................... 618 Figure 24.11 Reset Input Timing ....................620 Figure 24.12 Interrupt Signal Input Timing ................620 Figure 24.13 IRQOUT Timing....................
Page 43 Figure 24.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) ..... 645 Figure 24.38 Synchronous DRAM Self-Refresh Cycle (TPC = 0) ........... 645 Figure 24.39 Synchronous DRAM Mode Register Write Cycle ..........646 Figure 24.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) ......647 Figure 24.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait) ...
Page 44 Tables Section 2 CPU Table 2.1 Initial Register Values .................... 15 Table 2.2 Addressing Modes and Effective Addresses ............23 Table 2.3 Instruction Formats ....................27 Table 2.4 Classification of Instructions.................. 30 Table 2.5 Data Transfer Instructions ..................34 Table 2.6 Arithmetic Instructions...................
Page 45 Table 6.7 Interrupt Response Time ..................136 Section 7 User Break Controller Table 7.1 Data Access Cycle Addresses and Operand Size Comparison Conditions .... 154 Section 8 Bus State Controller (BSC) Table 8.1 Pin Configuration ....................165 Table 8.2 Physical Address Space Map ................. 168 Table 8.3 Correspondence between External Pins (MD4 and MD3) and Memory Size ..
Page 46 Table 10.3 Available Combination of Clock Mode and FRQCR Values......... 308 Section 12 Timer Unit (TMU) Table 12.1 Pin Configuration ....................325 Table 12.2 TMU Interrupt Sources ..................338 Section 13 Realtime Clock (RTC) Table 13.1 RTC Pin Configuration ..................341 Table 13.2 Recommended Oscillator Circuit Constants (Recommended Values) ....
Page 47 Table 16.4 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode).................... 465 Table 16.5 Maximum Bit Rates during External Clock Input (Asynchronous Mode) ..... 465 Table 16.6 SCSMR2 Settings and SCIF Communication Formats .......... 469 Table 16.7 SCSCR2 and SCSCR2 Settings and SCIF Clock Source Selection .......
Page 48 Table 22.3 Register States in Software Standby Mode ............574 Section 24 Electrical Characteristics Table 24.1 Absolute Maximum Ratings................... 607 Table 24.2 DC Characteristics....................609 Table 24.3 Permitted Output Current Values ................611 Table 24.4 Operating Frequency Range................... 612 Table 24.5 Clock Timing ......................
Page 49: Section 1 Overview
Section 1 Overview Section 1 Overview The SH7706 is a RISC microprocessor that integrates a Renesas Technology-original RISC-type SuperH™ architecture SH-3 CPU as its core that has peripheral functions required for system configuration. The CPU of this LSI has upper compatibility with the SH-1 and SH-2 at object code level.
Page 50 Section 1 Overview • 32-bit internal data bus • Logical address space: 4 Gbytes • Space identifier ASID: 8 bits, 256 logical address space • Abundant Peripheral Functions  Memory Management Unit (MMU)  User Break Controller (UBC)  Bus state Controller (BSC) ...
Page 51: Block Diagram
Section 1 Overview Block Diagram CACHE BRIDGE H-UDI SCIF INTC DMAC CPG/WDT I/O port External bus interface Legend: : A/D converter DMAC : Direct memory access controller : Advanced user debugger H-UDI : User debugging interface : Bus state controller INTC : Interrupt controller CACHE...
Page 52: Pin Assignment
Section 1 Overview Pin Assignment CS3/PTC[4] STATUS0/PTE[4] CS2/PTC[3] STATUS1/PTE[5] TCLK/PTE[6] IRQOUT/PTE[7] CKIO RD/WR WE3/DQMUU/ICIOWR/PTC[2] WE2/DQMUL/ICIORD/PTC[1] TxD0/SCPT[0] WE1/DQMLU/WE SCK0/SCPT[1] WE0/DQMLL TxD2/SCPT[2] SCK2/SCPT[3] RTS2/SCPT[4] BS/PTC[0] RxD0/SCPT[0] RxD2/SCPT[2] CTS2/IRQ5/SCPT[5] RESETM IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] IRQ2/IRL2/PTH[2] IRQ3/IRL3/PTH[3] SH-7706 IRQ4/PTH[4] FP-176C (Top view) AUDCK/PTG[4] DREQ0/PTH[5] DREQ1/PTH[6] ADTRG/PTG[5] RESETP AN[0]/PTJ[0] AN[1]/PTJ[1]...
Page 53: Figure 1.3 Pin Assignment (Tbp-208A)
Section 1 Overview SH7706 TBP-208A (Top view) INDEX MARK Note: Section in the dotted lines are perspective view. Figure 1.3 Pin Assignment (TBP-208A) Rev. 5.00 May 29, 2006 page 5 of 698 REJ09B0146-0500...
Page 54: Pin Function
Section 1 Overview Pin Function Number of Pins FP-176C TBP-208A Pin Name Description -RTC * — RTC power supply (1.9 V) XTAL2 On-chip RTC crystal oscillator pin EXTAL2 On-chip RTC crystal oscillator pin -RTC * — RTC power supply (0 V) D31/PTB[7] Data bus / input/output port B D30/PTB[6]...
Page 55 Section 1 Overview Number of Pins FP-176C TBP-208A Pin Name Description Data bus Data bus Data bus Data bus Data bus Data bus Data bus — Input/output power supply (0 V) Data bus — Input/output power supply (3.3 V) Data bus Data bus Data bus Data bus...
Page 56 Section 1 Overview Number of Pins FP-176C TBP-208A Pin Name Description Address bus — Input/output power supply (0 V) Address bus — Input/output power supply (3.3 V) Address bus Address bus Address bus Address bus Address bus Address bus Address bus —...
Page 57 Section 1 Overview Number of Pins FP-176C TBP-208A Pin Name Description — Input/output power supply (0 V) Chip select 0 — Input/output power supply (3.3 V) CS2/PTC[3] O / I/O Chip select 2 / input/output port C CS3/PTC[4] O / I/O Chip select 3 / input/output port C CS4/PTC[5] O / I/O...
Page 58 Section 1 Overview Number of Pins FP-176C TBP-208A Pin Name Description DRAK0/PTE[2] O / I/O DMA request acknowledge / input/output port E DRAK1/PTE[3] O / I/O DMA request acknowledge / input/output port E AUDATA[0]/PTF[0] AUD data / input/output port F AUDATA[1]/PTF[1] AUD data / input port F AUDATA[2]/PTF[2]...
Page 59 Section 1 Overview Number of Pins FP-176C TBP-208A Pin Name Description STATUS0/PTE[4] O / I/O Processor status / input/output port E STATUS1/PTE[5] O / I/O Processor status / input/output port E TCLK/PTE[6] TMU or RTC clock input/output / input/output port E IRQOUT/PTE[7] O / I/O Interrupt request notification /...
Page 60 Section 1 Overview Number of Pins FP-176C TBP-208A Pin Name Description Nonmaskable interrupt request — Input/output power supply (3.3 V) AUDCK/PTG[4] AUD clock / input port G DREQ0/PTH[5] I / I/O DMA request / input/output port H DREQ1/PTH[6] I / I/O DMA request / input/output port H ADTRG/PTG[5] Analog trigger / input port G...
Page 61: Section 2 Cpu
Section 2 CPU Section 2 CPU Register Description 2.1.1 Privileged Mode and Banks Processor Modes: There are two processor modes: user mode and privileged mode. The SH7706 normally operates in user mode, and enters privileged mode when an exception occurs or an interrupt is accepted.
Page 62: Figure 2.1 Register Configuration
Section 2 CPU Switching between user mode and privileged mode is controlled by the processor mode bit (MD) in the status register. R0_BANK0 * R0_BANK1 * R0_BANK0 * R1_BANK0 * R1_BANK0 * R1_BANK1 * R2_BANK0 * R2_BANK0 * R2_BANK1 * R3_BANK0 * R3_BANK1 * R3_BANK0 *...
Page 63: General Registers
Section 2 CPU Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type Registers Initial Value* General registers R0 to R15 Undefined Control registers MD bit = 1, RB bit = 1, BL bit = 1, I3 to I0 = 1111 (H'F), reserved bits = 0, others undefined GBR, SSR, SPC...
Page 64: System Registers
Section 2 CPU 2.1.3 System Registers System registers can be accessed by the LDS and STS instructions. When an exception occurs, the contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC contents are restored to the PC by the RTE instruction used at the end of the exception handling. There are three system registers, as follows.
Page 65: Control Registers
Section 2 CPU 2.1.4 Control Registers Control registers can be accessed in privileged mode using the LDC and STC instructions. The GBR register can also be accessed in user mode. There are five control registers, as follows: • Status register (SR) •...
Page 66 Section 2 CPU • Status Register (SR) The information of system status are set in this register. Bit Name Initial Value Description  Reserved These bits always read as 0, and the write value should always be 0. Processor operation mode bit Indicates the processor operation mode.
Page 67 Section 2 CPU Bit Name Initial Value Description  11, 10 All 0 Reserved These bits always read as 0, and the write value should always be 0.  M bit  Q bit Used by the DIV0S/U and DIV1 instructions. Interrupt mask bits 4-bit field indicating the interrupt request mask level.
Page 68: Data Formats
Section 2 CPU • Global Base Register (GBR) Stores base address of GBR-indirect addressing mode. The GBR-indirect addressing mode is used for on-chip supporting module register area data transfers and logic operations. The GBR register can also be accessed in user mode. Initialized to undefined by a reset.
Page 69: Instruction Features
Section 2 CPU The data format in memory is shown in figure 2.5. Address A + 1 Address A + 3 Address A + 10 Address A + 8 Address A Address A + 2 Address A + 11 Address A + 9 Address A Address A + 8 Byte0...
Page 70 Section 2 CPU T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To improve processing speed, the T bit logic state is modified only by specific operations. An example of how the T bit may be used in a sequence of operations is shown below.
Page 71: Addressing Modes
Section 2 CPU 2.3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in table 2.2. Table 2.2 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula Register Effective address is register Rn. (Operand —...
Page 72 Section 2 CPU Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula Register @(disp:4, Effective address is register Rn contents Byte: Rn + disp indirect with with 4-bit displacement disp added. Word: Rn + disp × 2 displacement After disp is zero-extended, it is multiplied Longword: Rn + disp ×...
Page 73 Section 2 CPU Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula Word: PC + disp × 2 PC-relative @(disp:8, Effective address is register PC contents with with 8-bit displacement disp added. Longword: displacement After disp is zero-extended, it is multiplied PC &...
Page 74 Section 2 CPU Addressing Instruction Mode Format Effective Address Calculation Method Calculation Formula PC-relative Effective address is sum of register PC and PC + Rn Rn contents. PC + R0 Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, —...
Page 75: Instruction Formats
Section 2 CPU 2.3.3 Instruction Formats Table 2.3 explains the meaning of instruction formats and source and destination operands. The meaning of the operands depends on the operation code. The following symbols are used. xxxx: Operation code mmmm: Source register nnnn: Destination register iiii:...
Page 76 Section 2 CPU Source Destination Instruction Instruction Format Operand Operand Example mmmm: register nnnn: register format direct direct Rm,Rn xxxx nnnn mmmm xxxx mmmm: register nnnn: register MOV.L indirect indirect Rm,@Rn mmmm: register MACH,MACL MAC.W indirect with post- @Rm+,@Rn+ increment (multiply-and- accumulate operation)
Page 77 Section 2 CPU Source Destination Instruction Instruction Format Operand Operand Example mmmm: register nnnndddd: MOV.L format direct register indirect Rm,@(disp,Rn) xxxx nnnn mmmm dddd with displacement mmmmdddd: nnnn: register MOV.L register indirect direct @(disp,Rm),Rn with displacement d format dddddddd: GBR R0 (register MOV.L xxxx...
Page 78: Instruction Set
Section 2 CPU Instruction Set 2.4.1 Instruction Set Classified by Function The SH7706 instruction set includes 68 basic instruction types, as listed in table 2.4. Table 2.4 Classification of Instructions Operation No. of Classification Types Code Function Instructions Data transfer Data transfer MOVA Effective address transfer...
Page 79 Section 2 CPU Operation No. of Classification Types Code Function Instructions Arithmetic Double-precision multiplication (32 × 32 bits) operations Signed multiplication (16 × 16 bits) MULS Unsigned multiplication (16 × 16 bits) MULU Negation NEGC Negation with borrow Binary subtraction SUBC Binary subtraction with borrow SUBV...
Page 80 Section 2 CPU Operation No. of Classification Types Code Function Instructions Branch Conditional branch, delayed conditional branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch BRAF Unconditional branch Branch to subroutine procedure BSRF Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure...
Page 81 Section 2 CPU Item Format Explanation Instruction OP.Sz SRC,DEST OP: Operation code mnemonic Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement MSB ↔ LSB Instruction mmmm: Source register code nnnn: Destination register 0000: R0 0001: R1 ...
Page 82: Table 2.5 Data Transfer Instructions
Section 2 CPU Table 2.5 lists the data transfer instructions Table 2.5 Data Transfer Instructions Privileged Instruction Operation Code Mode Cycles T Bit imm → Sign extension — — #imm,Rn 1110nnnniiiiiiii → Rn (disp × 2 + PC) → Sign —...
Page 83 Section 2 CPU Privileged Instruction Operation Code Mode Cycles T Bit Rm → (R0 + Rn) — — MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rm → (R0 + Rn) — — MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 (R0 + Rm) → Sign — — MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 extension →...
Page 84: Table 2.6 Arithmetic Instructions
Section 2 CPU Table 2.6 lists the arithmetic instructions. Table 2.6 Arithmetic Instructions Privileged Instruction Operation Code Mode Cycles T Bit Rn + Rm → Rn — — Rm,Rn 0011nnnnmmmm1100 Rn + imm → Rn — — #imm,Rn 0111nnnniiiiiiii Rn + Rm + T → Rn, —...
Page 85 Section 2 CPU Privileged Instruction Operation Code Mode Cycles T Bit Signed operation of — 2 to (5)* — DMULS.L Rm,Rn 0011nnnnmmmm1101 Rn × Rm → MACH, MACL 32 × 32 → 64 bits Unsigned operation of — 2 to (5)* — DMULU.L Rm,Rn 0011nnnnmmmm0101 Rn ×...
Page 86 Section 2 CPU Privileged Instruction Operation Code Mode Cycles T Bit Rn–Rm → Rn — — Rm,Rn 0011nnnnmmmm1000 Rn–Rm–T → Rn, — Borrow SUBC Rm,Rn 0011nnnnmmmm1010 Borrow → T Rn–Rm → Rn, — Underflow SUBV Rm,Rn 0011nnnnmmmm1011 Underflow → T Note: * The normal number of execution cycles is shown.
Page 87: Table 2.7 Logic Operation Instructions
Section 2 CPU Table 2.7 lists the logic operation instructions. Table 2.7 Logic Operation Instructions Privileged Instruction Operation Code Mode Cycles T Bit Rn & Rm → Rn — — Rm,Rn 0010nnnnmmmm1001 R0 & imm → R0 — — #imm,R0 11001001iiiiiiii (R0 + GBR) &...
Page 88: Table 2.8 Shift Instructions
Section 2 CPU Table 2.8 lists the shift instructions. Table 2.8 Shift Instructions Privileged Instruction Operation Code Mode Cycles T Bit T ← Rn ← MSB — ROTL 0100nnnn00000100 LSB → Rn → T — ROTR 0100nnnn00000101 T ← Rn ← T —...
Page 89: Table 2.9 Branch Instructions
Section 2 CPU Table 2.9 lists the branch instructions. Table 2.9 Branch Instructions Privileged Instruction Operation Code Mode Cycles T Bit If T = 0, disp × 2 + PC → PC; — 3/1* — label 10001011dddddddd if T = 1, nop (where label is disp + PC) Delayed branch, if T = 0, —...
Page 90: Table 2.10 System Control Instructions
Section 2 CPU Table 2.10 lists the system control instructions. Table 2.10 System Control Instructions Privileged Instruction Operation Code Mode Cycles T Bit 0 → MACH, MACL — — CLRMAC 0000000000101000 0 → S — — CLRS 0000000001001000 0 → T —...
Page 91 Section 2 CPU Privileged Instruction Operation Code Mode Cycles T Bit √ (Rm) → R4_BANK, — LDC.L @Rm+, 0100mmmm11000111 Rm + 4 → Rm R4_BANK √ (Rm) → R5_BANK, — LDC.L @Rm+, 0100mmmm11010111 Rm + 4 → Rm R5_BANK √ (Rm) →...
Page 92 Section 2 CPU Privileged Instruction Operation Code Mode Cycles T Bit √ R4_BANK→ Rn — R4_BANK,Rn 0000nnnn11000010 √ R5_BANK→ Rn — R5_BANK,Rn 0000nnnn11010010 √ R6_BANK→ Rn — R6_BANK,Rn 0000nnnn11100010 √ R7_BANK→ Rn — R7_BANK,Rn 0000nnnn11110010 √ Rn–4 → Rn, SR → (Rn) —...
Page 93 Section 2 CPU Notes: The table shows the minimum number of execution cycles. The actual number of instruction execution cycles will increase in cases such as the followings: a. When there is contention between an instruction fetch and data access b.
Page 94: Instruction Code Map
Section 2 CPU 2.4.2 Instruction Code Map Table 2.11 shows the instruction code map. Table 2.11 Instruction Code Map Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111 MD: 00 MD: 01 MD: 10 MD: 11 0000 0000 0000 0001...
Page 95 Section 2 CPU Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111 MD: 00 MD: 01 MD: 10 MD: 11 0100 0000 SHLL SHAL 0100 0001 SHLR CMP/PZ SHAR 0100 0010 STS.L MACH,@-Rn STS.L MACL,@-Rn STS.L PR,@-Rn 0100 00MD 0011 STC.L SR,@-Rn...
Page 96 Section 2 CPU Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111 MD: 00 MD: 01 MD: 10 MD: 11 0110 10MD SWAP.B Rm,Rn SWAP.W Rm,Rn NEGC Rm,Rn Rm,Rn 0110 11MD EXTU.B Rm,Rn EXTU.W Rm,Rn EXTS.B Rm,Rn EXTS.W Rm,Rn 0111...
Page 97: Processor States And Processor Modes
Section 2 CPU Processor States and Processor Modes 2.5.1 Processor States The SH7706 has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The CPU enters the power-on reset state if the RESETP pin is low, or the manual reset state if the RESETM pin is low.
Page 98: Processor Modes
Section 2 CPU From any state when From any state but hardware standby RESETP = 0 mode or bus-released state when RESETM = 0 RESETP = 0 Power-on reset Manual reset state state Reset state RESETP = 1 RESETM = 1 Exception-handling state Interrupt End of exception...
Page 99: Section 3 Memory Management Unit (Mmu)
Section 3 Memory Management Unit (MMU) Section 3 Memory Management Unit (MMU) This LSI has an on-chip memory management unit (MMU) that implements address translation. This LSI's features a resident translation look-aside buffer (TLB) that caches information for user- created address translation tables located in external memory. It enables high-speed translation of virtual addresses into physical addresses.
Page 100: Figure 3.1 Mmu Functions
Section 3 Memory Management Unit (MMU) Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would result in poor efficiency. For this reason, a buffer for address translation (translation look-aside buffer: TLB) is provided in hardware to hold frequently used address translation information.
Page 101: This Lsi's Mmu
Section 3 Memory Management Unit (MMU) 3.1.1 This LSI's MMU Virtual Address Map: This LSI uses 32-bit virtual addresses to access a 4-Gbyte virtual address space that is divided into several areas. Address space mapping is shown in figure 3.2. In the privileged mode, the virtual address space is divided into five areas.
Page 102: Figure 3.2 Virtual Address Space Mapping
Section 3 Memory Management Unit (MMU) H'00000000 H'00000000 2-Gbyte virtual space, 2-Gbyte virtual space, cacheable Area P0 cacheable Area U0 (write-back/write-through) (write-back/write-through) H'80000000 H'80000000 0.5-Gbyte fixed physical space, cacheable Area P1 (write-back/write-through) H'A0000000 0.5-Gbyte fixed physical space, Area P2 non-cacheable CPU Address error H'C0000000 0.5-Gbyte virtual space,...
Page 103 Section 3 Memory Management Unit (MMU) Physical Address Space: This LSI supports a 32-bit physical address space, but the upper 3 bits are actually ignored and treated as a shadow. See section 8, Bus State Controller (BSC), for details. Address Translation: When the MMU is enabled, the virtual address space is divided into units called pages.
Page 104: Register Description
Section 3 Memory Management Unit (MMU) Address Space Identifier (ASID): In multiple virtual memory mode, the address space identifier (ASID) is used to differentiate between processes running in parallel and sharing virtual address space. The ASID is 8 bits in length and can be set by software setting of the ASID of the currently running process in page table entry register high (PTEH) within the MMU.
Page 105: Page Table Entry Register High (Pteh)
Section 3 Memory Management Unit (MMU) 3.2.1 Page Table Entry Register High (PTEH) The page table entry register high (PTEH) consists of a virtual page number (VPN) and ASID. The VPN is set the VPN of the virtual address at which the exception is generated in case of an MMU exception or CPU address error exception.
Page 106: The Translation Table Base Register (Ttb)
Section 3 Memory Management Unit (MMU) 3.2.3 The Translation Table Base Register (TTB) The translation table base register (TTB) is a 32-bit register. TTB is used to store the base address of the current page table. The contents of this register are only modified in response to a software command.
Page 107 Section 3 Memory Management Unit (MMU) Initial Bit Name Value Description 31 to 9  All 0 Reserved These bits are always read as 0. The write value should always be 0.  Single virtual memory mode 0: multiple virtual memory mode 1: single virtual memory mode ...
Page 108: Tlb Functions
Section 3 Memory Management Unit (MMU) TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the physical page number translated from the virtual page number and the control information for the page, which is the unit of address translation.
Page 109: Figure 3.4 Virtual Address And Tlb Structure
Section 3 Memory Management Unit (MMU) Offset Virtual address (1-kbyte page) Offset Virtual address (4-kbyte page) (15) (22) (1) (1) VPN (31–17) VPN (11, 10) ASID TLB entry Legend VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual address for a 4-kbyte page.
Page 110: Tlb Indexing
Section 3 Memory Management Unit (MMU) 3.3.2 TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16 to 12 and ASID bits in PTEH 4 to 0 are used as the index number regardless of the page size. The index number can be generated in two different ways depending on the setting of the IX bit in MMUCR.
Page 111: Tlb Address Comparison
Section 3 Memory Management Unit (MMU) Virtual address Index Ways 0 to 3 VPN(31–17) VPN(11, 10) ASID(7–0) PPN(31–10) PR(1, 0) SZ C D SH Address array Data array Figure 3.6 TLB Indexing (IX = 0) 3.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB.
Page 112: Figure 3.7 Objects Of Address Comparison
Section 3 Memory Management Unit (MMU) When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged (SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared when single virtual memory is supported and privileged mode is engaged. The objects of address comparison are shown in figure 3.7.
Page 113: Page Management Information
Section 3 Memory Management Unit (MMU) 3.3.4 Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attempt to write to the page results in an initial page write exception.
Page 114: Mmu Functions
Section 3 Memory Management Unit (MMU) MMU Functions 3.4.1 MMU Hardware Management There are two kinds of MMU hardware management as follows: 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the MMUCR settings. 2.
Page 115: Mmu Instruction (Ldtlb)
Section 3 Memory Management Unit (MMU) 3.4.3 MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the index number.
Page 116: Avoiding Synonym Problems
Section 3 Memory Management Unit (MMU) 3.4.4 Avoiding Synonym Problems When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of virtual addresses are mapped onto a single physical address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity.
Page 117: Figure 3.9 Synonym Problem
Section 3 Memory Management Unit (MMU) When using a 4-kbyte page Virtual address 12 11 Offset Virtual address (11 to 4) Physical address 12 11 Cache address array Offset Physical address (31 to 10) When using a 1-kbyte page Virtual address Offset Virtual address (11 to 4) Physical address...
Page 118: Mmu Exceptions
Section 3 Memory Management Unit (MMU) MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5.1 TLB Miss Exception A TLB miss results when the virtual address and the address array of the selected TLB entry are compared and no match is found.
Page 119: Tlb Protection Violation Exception
Section 3 Memory Management Unit (MMU) Software (TLB Miss Handler) Operations: The software searches the page tables in external memory and allocates the required page table entry. Upon retrieving the required page table entry, software must execute the following operations: 1.
Page 120: Tlb Invalid Exception
Section 3 Memory Management Unit (MMU) Software (TLB Protection Violation Handler) Operations: Software resolves the TLB protection violation and issues the RTE (return from exception handler) instruction to terminate the handler and return to the instruction stream. Note that the RTE instruction should be issued after the two instructions following the LDTLB instruction.
Page 121: Initial Page Write Exception
Section 3 Memory Management Unit (MMU) 4. Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. 3.5.4 Initial Page Write Exception An initial page write exception results in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to).
Page 122: Figure 3.10 Mmu Exception Generation Flowchart
Section 3 Memory Management Unit (MMU) Figure 3.10 shows the flowchart for MMU exceptions. Start SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? VPNs match? VPNs and ASIDs match? V = 1? TLB miss TLB invalid exception exception User mode Privileged mode...
Page 123: Processing Flow In Event Of Mmu Exception (Same Processing Flow For Cpu Address Error)
Section 3 Memory Management Unit (MMU) 3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for CPU Address Error) Figure 3.11 shows the MMU exception signals in the instruction fetch mode. Handler transition processing MMU exception handler : Exception source stage Legend: = Instruction fetch = Instruction decode...
Page 124: Figure 3.12 Mmu Exception Signals In Data Access
Section 3 Memory Management Unit (MMU) Figure 3.12 shows the MMU exception signals in the data access mode. Handler transition processing MMU exception handler : Exception source stage : Stage cancellation for instruction that has begun execution Legend: = Instruction fetch = Instruction decode = Instruction execution = Memory access...
Page 125: Configuration Of The Memory-Mapped Tlb
Section 3 Memory Management Unit (MMU) Configuration of the Memory-Mapped TLB In order for TLB operations to be managed by software, TLB contents can be read or written to in the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the virtual address space.
Page 126: Figure 3.13 Specifying Address And Data For Memory-Mapped Tlb Access
Section 3 Memory Management Unit (MMU) Both reading and writing use the longword of the data array specified by the entry address and way number. The access size of the data array is fixed at longword. (1) TLB Address Array Access Read access Address field 11110010...
Page 127: Usage Examples
Section 3 Memory Management Unit (MMU) 3.6.3 Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry's V bit. R0 specifies the write data and R1 specifies the address. ; R0=H'1547 381C R1=H'F201 3000 ;...
Page 128: Use Of Tlb
Section 3 Memory Management Unit (MMU) 3.7.2 Use of TLB An erroneous value is set in the RC bit in MMUCR when all of the following conditions are satisfied. 1. MMU is on (AT bit in MMUCR is 1) 2. Same VPN exists in more than one ways in a single entry in a TLB address array 3.
Page 129: Section 4 Exception Processing
Section 4 Exception Processing Section 4 Exception Processing Exception Processing Function Exception processing is separate from normal program processing, and is performed by a routine separate from the normal program. In response to an exception processing request due to abnormal termination of the executing instruction, control is passed to a user-written exception handler.
Page 130: Exception Processing Vector Addresses
Section 4 Exception Processing 4.1.2 Exception Processing Vector Addresses The reset vector address is fixed at H'A0000000. The other three events are assigned offsets from the vector base address by software. Translation look-aside buffer (TLB) miss exceptions have an offset from the vector base address of H'00000400. The vector address offset for general exception events other than TLB miss exceptions is H'00000100.
Page 131: Acceptance Of Exceptions
Section 4 Exception Processing Exception Current Exception Vector Vector Priority * Type Instruction Exception Event Order Address Offset General Aborted TLB protection violation — H'00000100 exception and retried (instruction access) events General illegal — H'00000100 instruction exception Illegal slot — H'00000100 instruction exception CPU Address error...
Page 132: Figure 4.2 Example Of Acceptance Order Of General Exceptions
Section 4 Exception Processing All general exception events occur in a relative order in the execution sequence of an instruction (i.e. execution order), but are handled at priority level 2 in instruction-stream order (i.e. program order), where an exception detected in a preceding instruction is accepted prior to an exception detected in a subsequent instruction.
Page 133: Exception Codes
Section 4 Exception Processing All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction boundaries. However, an exception is not accepted between a delayed branch instruction and the delay slot. A re-execution type exception detected in a delay slot is accepted before execution of the delayed branch instruction.
Page 134: Exception Request And Bl Bit
Section 4 Exception Processing Exception Type Exception Event Exception Code General interrupt requests Nonmaskable interrupt H'1C0 H-UDI interrupt H'5E0 External hardware interrupts: IRL3–IRL0 = 0000 H'200 IRL3–IRL0 = 0001 H'220 IRL3–IRL0 = 0010 H'240 IRL3–IRL0 = 0011 H'260 IRL3–IRL0 = 0100 H'280 IRL3–IRL0 = 0101 H'2A0...
Page 135: Register Description
Section 4 Exception Processing If the SPC and SSR have been saved in the external memory, set the BL bit in SR to 1, then restore the SPC and SSR, and issue an RTE instruction. Register Description There are four registers related to exception processing. These are peripheral module registers, and therefore reside in area P4.
Page 136: Interrupt Event Register (Intevt)
Section 4 Exception Processing 4.2.2 Interrupt Event Register (INTEVT) The interrupt event register (INTEVT) contains a 12-bit interrupt exception code or a code indicating the interrupt priority. Which is set when an interrupt occurs depends on the interrupt source (refer to section 6, Interrupt Controller (INTC)). The exception code or interrupt priority code is set automatically by hardware when an exception occurs.
Page 137: Trapa Exception Register (Tra)
Section 4 Exception Processing 4.2.4 TRAPA Exception Register (TRA) The TRAPA exception register (TRA) contains 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. Bit Name Initial Value R/W Description...
Page 138: Interrupts
Section 4 Exception Processing 4.3.2 Interrupts An interrupt processing request is accepted on completion of the current instruction. The interrupt acceptance sequence consists of the following operations: 1. The contents of the PC and SR are saved in SPC and SSR, respectively. 2.
Page 139: Individual Exception Operations
Section 4 Exception Processing Individual Exception Operations This section describes the conditions for specific exception processing, and the processor operations. 4.4.1 Resets • Power-On Reset  Conditions: RESETP low  Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000.
Page 140: General Exceptions
Section 4 Exception Processing Table 4.3 Types of Reset Internal State Conditions for Transition Type to Reset State On-Chip Supporting Modules RESETP = Low Power-on reset Initialized (See register configuration in relevant sections) RESETM = Low Manual reset Initialized H-UDI reset H-UDI reset command input Initialized 4.4.2...
Page 141 Section 4 Exception Processing • Initial page write exception  Conditions: A hit occurred to the TLB for a store access, but D = 0. (This occurs for initial writes to the page registered by the load.)  Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31 to 10).
Page 142 Section 4 Exception Processing  Operations: The virtual address (32 bits) that caused the exception is set in TEA. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. If the exception occurred during a read, H'0E0 is set in EXPEVT; if the exception occurred during a write, H'100 is set in EXPEVT.
Page 143: Interrupts
Section 4 Exception Processing C. When a privileged instruction in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions.  Operations: The PC of the previous delay branch instruction is saved to the SPC. SR of the instruction that generated the exception is saved to SSR.
Page 144 Section 4 Exception Processing • IRL Interrupts  Conditions: The value of the interrupt mask bits in SR is lower than the IRL3 to IRL0 level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. ...
Page 145: Usage Note
Section 4 Exception Processing Usage Note • Return from exception processing  Check the BL bit in SR with software. When the SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them. ...
Page 146 Section 4 Exception Processing SR.MD = 1, SR.BL = 1, SR.RB = 1, SR.I3 to SR.I0 = H'F, SR.CL = 0. Other SR bits are undefined. PC = H'A0000000 • Ensure that an exception is not generated at an RTE instruction delay slot, as operation is not guaranteed in this case.
Page 147: Section 5 Cache
Section 5 Cache Section 5 Cache Feature • Instruction/data mixed, 16-byte cache • 256 entries/way, 4-way set associative, 16-byte block • Write-back/write-through selectable • LRU replacing algorithm • 1-stage write-back buffer • A maximum of two ways lockable 5.1.1 Cache Structure The cache uses a 4-way set associative system.
Page 148: Table 5.1 Lru And Way Replacement
Section 5 Cache Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in write- back mode.
Page 149: Register Description
Section 5 Cache Register Description The cache includes the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. • Cache control register (CCR) • Cache control register 2 (CCR2) 5.2.1 Cache Control Register (CCR) The cache is enabled or disabled using the CE bit of the cache control register (CCR).
Page 150: Cache Control Register 2 (Ccr2)
Section 5 Cache 5.2.2 Cache Control Register 2 (CCR2) Cache control register 2 (CCR2) enables or disables the cache locking mechanism. This register setting is valid only in cache locking mode. Cache locking mode is enabled when the cache locking bit (bit 12) of the status register (SR) is set to 1, and disabled when it is cleared to 0. If a cache miss occurs during prefetch instruction (PREF) execution in cache locking mode, one line size of data pointed by Rn is loaded into the cache according to the W3LOAD, W3LOCK, W2LOAD, and W2LOCK bit settings of CCR2 (bits 9, 8, 1, and 0).
Page 151: Table 5.2 Way To Be Replaced When Cache Miss Occurs During Pref Instruction
Section 5 Cache Bit Name Initial Value Description W2LOAD W3LOAD: Way 2 load W2LOCK W3LOCK: Way 2 Lock When W3LOACK = 1 & W3LOAD = 1 & SR.CL is 1, the prefetched data will always be loaded into Way2. In all other conditions, the prefetched data will be loaded into the way pointed by LRU.
Page 152: Table 5.3 Way To Be Replaced When Cache Miss Occurs During Execution Of Instruction Other Than Pref Instruction
Section 5 Cache Table 5.3 Way to be Replaced when Cache Miss Occurs during Execution of Instruction Other than PREF Instruction CL bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced According to LRU (table 5.1) According to LRU (table 5.1) According to LRU (table 5.4) According to LRU (table 5.5) According to LRU (table 5.6)
Page 153: Operation
Section 5 Cache Operation 5.3.1 Searching the Cache If the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 5.2 illustrates the method by which the cache is searched.
Page 154: Read Access
Section 5 Cache Virtual address 12 11 4 3 2 1 0 Entry selection Longword (LW) selection Ways 0 to 3 Ways 0 to 3 V U Tag address Physical address CMP0 CMP1 CMP2 CMP3 Legend: CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 Hit signal 1...
Page 155: Prefetch Operation
Section 5 Cache 5.3.3 Prefetch Operation Prefetch Hit: LRU is updated so that the way that has been hit to be the latest. Other contents of the cache are not updated. Instruction or data is not transferred to the CPU. Prefetch Miss: Instruction or data is not transferred to the CPU.
Page 156: Coherency Of Cache And External Memory
Section 5 Cache 5.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. To allocate memory shared by this LSI and the external device to an address area to be cached, invalidate the entries by operating the memory allocating cache as required.
Page 157: Data Array
Section 5 Cache bit specified in the data field are written to. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. Address Array Write (with associative operation): When writing while the associative bit (bit A) is 1, the addresses of four entries selected by the entry addresses are compared to the tag addresses specified in the data field.
Page 158: Figure 5.4 Specifying Address And Data For Memory-Mapped Cache Access
Section 5 Cache (1) Address array access Address specification Read access * ………… * 1111 0000 Entry address Write access * ………… * 1111 0000 Entry address Data specification (both read and write accesses) 313029 0 0 0 Address tag (28–10) (2) Data array access (both read and write accesses) Address specification * …………...
Page 159: Usage Examples
Section 5 Cache 5.4.3 Usage Examples 1. Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry's U and V bit. When the A bit is 1, the address tag specified by the write data is compared to the address tag within the cache selected by the entry address, and data is written when a match is found.
Page 160 Section 5 Cache Rev. 5.00 May 29, 2006 page 112 of 698 REJ09B0146-0500...
Page 161: Section 6 Interrupt Controller (Intc)
Section 6 Interrupt Controller (INTC) Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt, and interrupt requests are handled according to the priorities set in these registers.
Page 162: Figure 6.1 Intc Block Diagram
Section 6 Interrupt Controller (INTC) Figure 6.1 is a block diagram of the INTC. IRQOUT IRL3 to IRL0 Input control IRQ0 to IRQ5 Interrupt Com- request parator (Interrupt request) DMAC (Interrupt request) SCIF Priority identifier (Interrupt request) 2 1 0 (Interrupt request) (Interrupt request) (Interrupt request)
Page 163: Input/Output Pin
Section 6 Interrupt Controller (INTC) Input/Output Pin Table 6.1 lists the INTC pin configuration. Table 6.1 Pin Configuration Name Abbreviation Description Nonmaskable interrupt input pin Nonmaskable interrupt request signal input Interrupt input pins IRQ5 to IRQ0 Interrupt request signal input (Maskable by interrupt mask bits in IRL3 to IRL0 IRQOUT...
Page 164: Irq Interrupt
Section 6 Interrupt Controller (INTC) It is possible to wake the chip up from the software standby state with an NMI interrupt (except when the MAI bit of the ICR1 register is set to 1). 6.3.2 IRQ Interrupt IRQ interrupts are input by priority from pins IRQ0 to IRQ5 with a level or an edge. The priority level can be set by priority setting registers C to D (IPRC to IPRD) in a range from levels 0 to 15.
Page 165: Irl Interrupts
Section 6 Interrupt Controller (INTC) 6.3.3 IRL Interrupts IRL interrupts are input by level at pins IRL3 to IRL0. The priority level is the higher of those indicated by pins IRL3 to IRL0. An IRL3 to IRL0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15).
Page 166: On-Chip Peripheral Module Interrupts
Section 6 Interrupt Controller (INTC) A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that no transient level on the IRL pin change is detected. In the software standby mode, as the peripheral clock is stopped, noise cancellation is performed using the 32-kHz clock for the RTC instead.
Page 167: Interrupt Exception Processing And Priority
Section 6 Interrupt Controller (INTC) 6.3.5 Interrupt Exception Processing and Priority Tables 6.3 and 6.4 lists the codes for the interrupt event register (INTEVT and INTEVT2), and the order of interrupt priority. Each interrupt source is assigned unique code. The start address of the interrupt service routine is common to each interrupt source.
Page 168 Section 6 Interrupt Controller (INTC) Interrupt Priority INTEVT Code Priority IPR (Bit within IPR Default Interrupt Source (INTEVT2 Code) (Initial Value) Numbers) Setting Unit Priority H'200 to 3C0 * (H'980) 0 to 15 (0) IPRE (3 to 0) — High TMU0 TUNI0 H'400 (H'400)
Page 169: Table 6.4 Interrupt Exception Handling Sources And Priority (Irl Mode)
Section 6 Interrupt Controller (INTC) Table 6.4 Interrupt Exception Handling Sources and Priority (IRL Mode) Interrupt Priority INTEVT Code Priority IPR (Bit within IPR Default Interrupt Source (INTEVT2 Code) (Initial Value) Numbers) Setting Unit Priority H'1C0 (H'1C0) — — High H-UDI H'5E0 (H'5E0) —...
Page 170 Section 6 Interrupt Controller (INTC) Interrupt Priority INTEVT Code Priority IPR (Bit within IPR Default Interrupt Source (INTEVT2 Code) (Initial Value) Numbers) Setting Unit Priority TMU0 TUNI0 H'400 (H'400) 0 to 15 (0) IPRA (15 to 12) — High TMU1 TUNI1 H'420 (H'420) 0 to 15 (0)
Page 171: Register Description
Section 6 Interrupt Controller (INTC) Table 6.5 Interrupt Level and INTEVT Code Interrupt level INTEVT Code H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0 Register Description The INTC has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes.
Page 172: Interrupt Priority Registers A To E (Ipra To Ipre)
Section 6 Interrupt Controller (INTC) 6.4.1 Interrupt Priority Registers A to E (IPRA to IPRE) The interrupt priority level setting registers A to E (IPRA to IPRE) are 16-bit read/write registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. These registers are initialized to H'0000 at power-on reset, manual reset, or in hardware standby mode, but is not initialized in standby mode.
Page 173: Interrupt Control Register 0 (Icr0)
Section 6 Interrupt Controller (INTC) 6.4.2 Interrupt Control Register 0 (ICR0) The interrupt control register 0 (ICR0) is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level to the NMI pin. This register is initialized to H'0000 at power-on reset or manual reset, but is not initialized in standby mode.
Page 174: Interrupt Control Register 1 (Icr1)
Section 6 Interrupt Controller (INTC) 6.4.3 Interrupt Control Register 1 (ICR1) The interrupt control register 1 (ICR1) is a 16-bit register that specifies the detection mode to external interrupt input pins, IRQ0 to IRQ5 individually: rising edge, falling edge, or low level. Bit Name Initial Value Description...
Page 175 Section 6 Interrupt Controller (INTC) Bit Name Initial Value Description IRQ51S IRQ5 Sense Select IRQ50S Select whether the interrupt signal to the IRQ5 pin is detected at the rising edge, at the falling edge, or at low level. 00: An interrupt request is detected at IRQ5 input falling edge 01: An interrupt request is detected at IRQ5 input rising edge...
Page 176 Section 6 Interrupt Controller (INTC) Bit Name Initial Value Description IRQ21S IRQ2 Sense Select IRQ20S Select whether the interrupt signal to the IRQ2 pin is detected at the rising edge, at the falling edge, or at low level. 00: An interrupt request is detected at IRQ2 input falling edge 01: An interrupt request is detected at IRQ2 input rising edge...
Page 177: Interrupt Request Register 0 (Irr0)
Section 6 Interrupt Controller (INTC) 6.4.4 Interrupt Request Register 0 (IRR0) The interrupt request register 0 (IRR0) is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5. To clear one of bits IRQ5R to IRQ0R to 0, first read the bit to confirm it is set to 1, then write 0 only to the bit to be cleared while writing 1 to all the other bits.
Page 178 Section 6 Interrupt Controller (INTC) Bit Name Initial Value R/W Description IRQ2R IRQ2 Interrupt Request Indicates whether an interrupt request is input to the IRQ2 pin. When edge detection mode is set for IRQ2, an interrupt request is cleared by clearing the IRQ2R bit.
Page 179: Interrupt Request Register 1 (Irr1)
Section 6 Interrupt Controller (INTC) 6.4.5 Interrupt Request Register 1 (IRR1) The interrupt request register 1 (IRR1) is an 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests are generated. Bit Name Initial Value R/W Description 7 to 4 —...
Page 180: Interrupt Request Register 2 (Irr2)
Section 6 Interrupt Controller (INTC) 6.4.6 Interrupt Request Register 2 (IRR2) The interrupt request register 2 (IRR2) is an 8-bit read-only register that indicates whether A/D converter, or SCIF interrupt requests are generated. Bit Name Initial Value R/W Description 7 to 5 —...
Page 181: Operation
Section 6 Interrupt Controller (INTC) Operation 6.5.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers A to E (IPRA to IPRE).
Page 182: Figure 6.3 Interrupt Operation Flowchart
Section 6 Interrupt Controller (INTC) source flag after it has been cleared, then wait for the interval shown in "Time for priority decision and SR mask bit comparison" in table 6.7 before clearing the BL bit or executing an RTE instruction. Program execution state ICR1.MAI = 1?
Page 183: Multiple Interrupts
Section 6 Interrupt Controller (INTC) 6.5.2 Multiple Interrupts When multiple interrupts are used, the structure of the interrupt service routine should be as follows. 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2. The code in INTEVT and INTEVT2 can be used as a branch-offset for branching to the specific handler.
Page 184: Table 6.7 Interrupt Response Time
Section 6 Interrupt Controller (INTC) Table 6.7 Interrupt Response Time Number of States Item Notes Peripheral Modules Time for priority 0.5 × Icyc 1.5 × Icyc 0.5 × Icyc 0.5 × Icyc + 1.5 × Pcyc * decision and SR + 1.5 ×...
Page 185 Section 6 Interrupt Controller (INTC) Number of States Item Notes Peripheral Modules Response Total (5.5 + X) (6.5 + X) (5.5 + X) (5.5 + X) × Icyc × Icyc × Icyc × Icyc time + 1.5 × Bcyc + 0.5 × Bcyc + 0.5 ×...
Page 186: Figure 6.4 Example Of Pipeline Operations When Irl Interrupt Is Accepted
Section 6 Interrupt Controller (INTC) Interrupt Start of interrupt acceptance processing 0.5 × Icyc + 0.5 × Bcyc + 3.5 × Pcyc 5 × Icyc Instruction (instruction replaced by interrupt exception processing) Overrun fetch First instruction of interrupt handler Legend: IF: Instruction fetch: Instruction is fetched from memory in which program is stored.
Page 187: Section 7 User Break Controller
Section 7 User Break Controller Section 7 User Break Controller The UBC provides functions that simplify program debugging. Using this function, a self-monitor debugger can be easily prepared, and a program can be debugged using this LSI alone, without using an in-circuit emulator. Instruction fetches, data read/write, data size, data contents, address values, and the timing to stop execution at instruction fetch can be set to the UBC.
Page 188: Figure 7.1 Block Diagram Of User Break Controller
Section 7 User Break Controller Access Control Access comparator BBRA BARA Address comparator BAMRA ASID comparator BASRA Channel A Access BBRB comparator BARB Address comparator BAMRB ASID comparator BASRB BDRB Data comparator BDMRB Channel B BETR BRSR PC Trace BRDR BRCR CONTROL LDB/IDB...
Page 189: Register Description
Section 7 User Break Controller Register Description The UBC has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. • Break address register A (BARA) • Break address mask register A (BAMRA) •...
Page 190: Break Address Mask Register A (Bamra)
Section 7 User Break Controller 7.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address specified by BARA. Bit Name Initial Value Description 31 to 0 BAMA31 to All 0 Break Address Mask Bit BAMA0 Specifies bits masked in the channel A break...
Page 191 Section 7 User Break Controller Bit Name Initial Value Description 15 to 8 — All 0 Reserved These bits are always read as 0. The write value should always be 0. CDA1 CPU Cycle/DMAC Cycle Select A CDA0 Selects the CPU cycle or DMAC cycle as the bus cycle of the channel A break condition.
Page 192: Break Address Register B (Barb)
Section 7 User Break Controller 7.2.4 Break Address Register B (BARB) BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in channel B. Bit Name Initial Value Description 31 to 0 BAB31 to All 0 Break Address BAB0 Stores the address of LAB or IAB that specifies...
Page 193: Break Data Mask Register B (Bdmrb)
Section 7 User Break Controller 7.2.7 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified by BDRB. Bit Name Initial Value R/W Description 31 to 0 BDMB31 to All 0 Break Data Mask BDMB0...
Page 194 Section 7 User Break Controller Bit Name Initial Value Description IDB1 Instruction Fetch/Data Access Select B IDB0 Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle...
Page 195: Break Control Register (Brcr)
Section 7 User Break Controller 7.2.9 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channels condition or under the sequential condition. 2. A break is set before or after instruction execution. 3.
Page 196 Section 7 User Break Controller Bit Name Initial Value Description SCMFCA CPU Condition Match Flag A When the CPU bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit.
Page 197 Section 7 User Break Controller Bit Name Initial Value Description PCTE PC Trace Enable Enables PC trace. 0: Disables PC trace 1: Enables PC trace PCBA PC Break Select A (PCBA) Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution.
Page 198: Execution Times Break Register (Betr)
Section 7 User Break Controller Bit Name Initial Value Description Sequence Condition Select Selects two conditions of channels A and B as independent or sequential. 0: Channels A and B are compared under the independent condition 1: Channels A and B are compared under the sequential condition 2, 1 —...
Page 199: Branch Source Register (Brsr)
Section 7 User Break Controller 7.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed instruction.
Page 200: Branch Destination Register (Brdr)
Section 7 User Break Controller 7.2.12 Branch Destination Register (BRDR) BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and also initialized by power-on resets or manual resets.
Page 201: Break Asid Register B (Basrb)
Section 7 User Break Controller 7.2.14 Break ASID Register B (BASRB) Break ASID register B (BASRB) is an 8-bit read/write register that specifies the ASID that serves as the break condition for channel B. It is not initialized by resets. It is located in CCN. Bit Name Initial Value Description...
Page 202: Break On Instruction Fetch Cycle
Section 7 User Break Controller 7.3.2 Break on Instruction Fetch Cycle 1. When CPU/instruction fetch/read/word or longword is set in the break bus cycle registers (BBRA/BBRB), the break condition becomes the CPU instruction fetch cycle. Whether it then breaks before or after the execution of the instruction can then be selected with the PCBA/PCBB bits of the break control register (BRCR) for the appropriate channel.
Page 203: Sequential Break
Section 7 User Break Controller Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions on B channel: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle registers (BBRA and BBRB).
Page 204: Pc Trace
Section 7 User Break Controller 2. When instruction fetch (after instruction execution) is specified as a break condition: The PC value saved is the address of the instruction to be executed following the instruction in which the break condition matches. The fetched instruction is executed, and a break occurs before the execution of the next instruction.
Page 205 Section 7 User Break Controller If the PID value is odd, instruction buffer indicates PID+2 buffer. However, these expressions in this table are accounted for it. Therefore, the true branch source address is calculated with BSA and PID values stored in BRSR. 3.
Page 206: Usage Examples
Section 7 User Break Controller 7.3.7 Usage Examples Break Condition Specified to a CPU Instruction Fetch Cycle 1. Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300400 Specified conditions: Channel A/channel B independent mode •...
Page 207 Section 7 User Break Controller 3. Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300000 Specified conditions: Channel A/channel B independent mode •...
Page 208 Section 7 User Break Controller 5. Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode •...
Page 209 Section 7 User Break Controller Break Condition Specified to a CPU Data Access Cycle 1. Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode •...
Page 210: Usage Note
Section 7 User Break Controller Usage Note 1. Only CPU can read/write UBC registers. 2. UBC cannot monitor CPU and DMAC access in the same channel. 3. Notes in specification of sequential break are described below: A. A condition match occurs when a channel B match occurs in a bus cycle after a channel A match occurs in another bus cycle in sequential break setting.
Page 211: Section 8 Bus State Controller (Bsc)
Section 8 Bus State Controller (BSC) Section 8 Bus State Controller (BSC) The bus state controller (BSC) divides physical address space and output control signals for various types of memory and bus interface specifications. BSC functions enable this LSI to link directly with DRAM, synchronous DRAM, SRAM, ROM, and other memory storage devices without an external circuit.
Page 212: Figure 8.1 Bsc Functional Block Diagram
Section 8 Bus State Controller (BSC)  Bus sizing function for I/O bus width (only in the little endian mode) • Refresh function  Refresh cycles will be automatically maintained in the sleep mode even after the external bus frequency is reduced to 1/4 of its normal operating frequency •...
Page 213: Input/Output Pin
Section 8 Bus State Controller (BSC) Input/Output Pin Table 8.1 lists the BSC pin configuration. Table 8.1 Pin Configuration Pin Name Signal Description Address bus A25 to A0 Address output Data bus D15 to D0 Data I/O D31 to D16 When 32-bit bus width, data I/O Bus cycle start Shows start of bus cycle.
Page 214: Area Overview
Section 8 Bus State Controller (BSC) Pin Name Signal Description WE2/DQMUL/ Data enable 2 When memory other than synchronous DRAM is ICIORD used, selects D23 to D16 write strobe signal. When synchronous DRAM is used, selects D23 to D16. When PCMCIA is used, strobe signal indicating I/O read.
Page 215: Figure 8.2 Corresponding To Logical Address Space And Physical Address Space
Section 8 Bus State Controller (BSC) H'00000000 Area 0 (CS0) H'00000000 Internal I/O H'04000000 H'20000000 Area 2 (CS2) H'08000000 Area 3 (CS3) H'0C000000 P0, U0 H'40000000 Area 4 (CS4) H'10000000 Area 5 (CS5) H'14000000 H'60000000 Area 6 (CS6) H'18000000 Reserved area H'80000000 Physical address space H'A0000000...
Page 216: Table 8.2 Physical Address Space Map
Section 8 Bus State Controller (BSC) Table 8.2 Physical Address Space Map Area Connectable Memory Physical Address Capacity Access Size 8, 16, 32 * Ordinary memory * H'00000000 to H'03FFFFFF 64 Mbytes H'00000000 + H'20000000 × n to Shadow n: 1 to 6 burst ROM H'03FFFFFF + H'20000000 ×...
Page 217: Figure 8.3 Physical Space Allocation
Section 8 Bus State Controller (BSC) Area 0: H'00000000 Ordinary memory/ burst ROM Area 1: H'04000000 Internal I/O Area 2: H'08000000 Ordinary memory/ synchronous DRAM Area 3: H'0C000000 Ordinary memory/ synchronous DRAM Area 4: H'10000000 Ordinary memory Area 5: H'14000000 Ordinary memory/ The PCMCIA interface is shared burst ROM/PCMCIA...
Page 218: Pcmcia Support
Section 8 Bus State Controller (BSC) Shadow Space: Areas 0, 2 to 6 are decoded by physical addresses A28 to A26, which correspond to areas 000 to 110. Address bits 31 to 29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space obtained by adding to it H'20000000 ×...
Page 219: Table 8.5 Pcmcia Support Interface
Section 8 Bus State Controller (BSC) Table 8.5 PCMCIA Support Interface IC Memory Card Interface I/O Card Interface Signal Function Signal Function SH7706 Pin — Ground — Ground — Data Data Data Data Data Data Data Data Data Data CE1A or CE1B Card enable Card enable Address...
Page 220 Section 8 Bus State Controller (BSC) IC Memory Card Interface I/O Card Interface Signal Function Signal Function SH7706 Pin Data Data Data Data Data Data IOIS16 IOIS16 WP * Write protect 16-bit I/O port Ground Ground — Ground Ground — Card detection Card detection —...
Page 221: Register Description
Section 8 Bus State Controller (BSC) IC Memory Card Interface I/O Card Interface Signal Function Signal Function SH7706 Pin INPACK Reserved Input acknowledge — Attribute memory Attribute memory — space select space select SPKR BVD2 Battery voltage Digital voice signal — detection STSCHG O BVD1...
Page 222: Bus Control Register 1 (Bcr1)
Section 8 Bus State Controller (BSC) 8.4.1 Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 16-bit read/write register that sets the functions and bus cycle state for each area. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by standby mode.
Page 223 Section 8 Bus State Controller (BSC) Bit Name Initial Value Description A0BST1 Area 0 Burst ROM Control A0BST0 Specify whether to use burst ROM in physical space area 0. When burst ROM is used, set the number of burst transfers. 00: Access area 0 as ordinary memory 01: Access area 0 as burst ROM (4 consecutive accesses).
Page 224 Section 8 Bus State Controller (BSC) Bit Name Initial Value Description DRAMTP2 Area 2, Area 3 Memory Type DRAMTP1 Designate the types of memory connected to physical space areas 2 and 3. Ordinary memory, such as ROM, DRAMTP0 SRAM, or flash ROM, can be directly connected. Synchronous DRAM can also be directly connected.
Page 225: Bus Control Register 2 (Bcr2)
Section 8 Bus State Controller (BSC) 8.4.2 Bus Control Register 2 (BCR2) The bus control register 2 (BCR2) is a 16-bit read/write register that selects the bus-size width and 8-bit port of each area. It is initialized to H'3FF0 by a power-on reset, but is not initialized by a manual reset or by standby mode.
Page 226 Section 8 Bus State Controller (BSC) Bit Name Initial Value Description A4SZ1 Area 4 Bus Size Specification A4SZ0 Specify the bus sizes of physical space area 4. • When port A/B is unused. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Longword (32-bit) size •...
Page 227: Wait State Control Register 1 (Wcr1)
Section 8 Bus State Controller (BSC) Bit Name Initial Value Description A2SZ1 Area 2 Bus Size Specification A2SZ0 Specify the bus sizes of physical space area 2. • When port A/B is unused. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Longword (32-bit) size •...
Page 228 Section 8 Bus State Controller (BSC) Bit Name Initial Value Description WAITSEL WAIT Sampling Timing Select Specifies the WAIT signal sampling timing. 0: Set 1 to use the WAIT signal. 1: The WAIT signal is sampled at the falling edge of CKIO.
Page 229 Section 8 Bus State Controller (BSC) Bit Name Initial Value Description A3IW1 Area 3 Intercycle Idle Specification A3IW0 Specify the number of idles inserted between bus cycles when switching between physical space area 3 to another space or between a read access to a write access in the same physical space.
Page 230: Wait State Control Register 2 (Wcr2)
Section 8 Bus State Controller (BSC) 8.4.4 Wait State Control Register 2 (WCR2) Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory accesses.
Page 231 Section 8 Bus State Controller (BSC) Bit Name Initial Value Description A2W1 Area 2 Wait Control A2W0 Specify the number of wait states inserted into physical space area 2. • For Ordinary memory WAIT Pin Inserted Wait States Ignored Enabled Enabled Enabled •...
Page 232: Table 8.6 Area 6 Wait Control (Normal Memory I/F)
Section 8 Bus State Controller (BSC) Table 8.6 Area 6 Wait Control (Normal Memory I/F) Description Burst Cycle WCR2's bits First Cycle (Excluding First Cycle) Bit 15: Bit 14: Bit 13: Inserted Number of States WAIT Pin WAIT Per Data Transfer WAIT WAIT Pin WAIT WAIT...
Page 233: Table 8.8 Area 4 Wait Control
Section 8 Bus State Controller (BSC) Table 8.8 Area 4 Wait Control WCR2's bits Description WAIT WAIT WAIT WAIT Pin Bit 9: A4W2 Bit 8: A4W1 Bit 7: A4W0 Inserted Wait State Ignored Enable Enable Enable Enable Enable Enable Enable Table 8.9 Area 0 Wait Control Description...
Page 234: Individual Memory Control Register (Mcr)
Section 8 Bus State Controller (BSC) 8.4.5 Individual Memory Control Register (MCR) The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address multiplexing, and controls refresh.
Page 235 Section 8 Bus State Controller (BSC) Bit Name Initial Value Description RCD1 RAS-CAS Delay RCD0 When synchronous DRAM interface is selected as connected memory, sets the bank active read/write command delay time. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles TRWL1 Write-Precharge Delay...
Page 236 Section 8 Bus State Controller (BSC) Bit Name Initial Value Description AMX3 Address Multiplex AMX2 The AMX bits specify address multiplexing for synchronous DRAM. The actual address shift value AMX1 differs between DRAM interface and synchronous AMX0 DRAM interface. For Synchronous DRAM interface: 0000: Reserved (Setting prohibited) 0001: Reserved (Setting prohibited) 0010: Reserved (Setting prohibited)
Page 237 Section 8 Bus State Controller (BSC) Bit Name Initial Value Description RFSH Refresh Control The RFSH bit determines whether or not the refresh operation of the DRAM and synchronous DRAM is performed. The timer for generation of the refresh request frequency can also be used as an interval timer.
Page 238: Pcmcia Control Register (Pcr)
Section 8 Bus State Controller (BSC) 8.4.6 PCMCIA Control Register (PCR) The PCMCIA control register (PCR) is a 16-bit read/write register that specifies the timing for the assertion or negation of the OE and WE signals for the PCMCIA interface connected to areas 5 and 6.
Page 239 Section 8 Bus State Controller (BSC) Bit * Bit Name Initial Value Description Area 6 Address OE/WE Assert Delay A6TED2 The A6TED bits specify the address to OE/WE A6TED1 assert delay time for the PCMCIA interface A6TED0 connected to area 6. 000: 0.5-cycle delay 001: 1.5-cycle delay 010: 2.5-cycle delay...
Page 240: Table 8.10 Area 6 Wait Control (Pcmcia I/F)
Section 8 Bus State Controller (BSC) Table 8.10 Area 6 Wait Control (PCMCIA I/F) Description Top Cycle Burst Cycle Number of Inserted States per WCR2 Wait One-data WAIT WAIT Pin WAIT Pin WAIT WAIT WAIT WAIT WAIT A6W3 A6W2 A6W1 A6W0 State Transfer...
Page 241: Synchronous Dram Mode Register (Sdmr)
Section 8 Bus State Controller (BSC) 8.4.7 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is written to via the synchronous DRAM address bus and is an 8-bit write-only register. It sets synchronous DRAM mode for areas 2 and 3. SDMR must be set before synchronous DRAM is accessed.
Page 242 Section 8 Bus State Controller (BSC) Bit Name Initial Value Description 15 to 8 — All 0 Reserved These bits are always read as 0. The write value should always be 0. Compare Match Flag The CMF status flag indicates that the values of RTCNT and RTCOR match.
Page 243 Section 8 Bus State Controller (BSC) Bit Name Initial Value Description Refresh Count Overflow Flag The OVF status flag indicates when the number of refresh requests indicated in the refresh count register (RFCR) exceeds the limit set in the LMTS bit of RTCSR.
Page 244: Refresh Timer Counter (Rtcnt)
Section 8 Bus State Controller (BSC) 8.4.9 Refresh Timer Counter (RTCNT) RTCNT is a 16-bit read/write register. RTCNT is an 8-bit counter that counts up with input clocks. The clock select bits (CKS2 to CKS0) of RTCSR select the input clock. When RTCNT matches RTCOR, the CMF bit of RTCSR is set and RTCNT is cleared.
Page 245: Refresh Count Register (Rfcr)
Section 8 Bus State Controller (BSC) 8.4.11 Refresh Count Register (RFCR) The refresh count register (RFCR) is a 16-bit read/write register. It is a 10-bit counter that increments every time RTCOR and RTCNT match. When RFCR exceeds the count limit value set in the LMTS of RTCSR, RTCSR's OVF bit is set and RFCR clears.
Page 246: Table 8.11 32-Bit External Device/Big Endian Access And Data Alignment
Section 8 Bus State Controller (BSC) Table 8.11 32-Bit External Device/Big Endian Access and Data Alignment Data Bus Strobe Signals WE3, WE2, WE1, WE0, D31 to D23 to D15 to D7 to DQMUU DQMUU DQMUU DQMUU DQMUL DQMUL DQMUL DQMUL DQMLU DQMLU DQMLU...
Page 247: Table 8.13 8-Bit External Device/Big Endian Access And Data Alignment
Section 8 Bus State Controller (BSC) Table 8.13 8-Bit External Device/Big Endian Access and Data Alignment Data Bus Strobe Signals WE3, WE2, WE1, WE0, D31 to D23 to D15 to D7 to DQMUU DQMUU DQMUU DQMUU DQMUL DQMUL DQMUL DQMUL DQMLU DQMLU DQMLU...
Page 248: Table 8.14 32-Bit External Device/Little Endian Access And Data Alignment
Section 8 Bus State Controller (BSC) Table 8.14 32-Bit External Device/Little Endian Access and Data Alignment Data Bus Strobe Signals WE3, WE2, WE1, WE0, D31 to D23 to D15 to D7 to DQMUU DQMUU DQMUU DQMUU DQMUL DQMUL DQMUL DQMUL DQMLU DQMLU DQMLU...
Page 249: Table 8.16 8-Bit External Device/Little Endian Access And Data Alignment
Section 8 Bus State Controller (BSC) Table 8.16 8-Bit External Device/Little Endian Access and Data Alignment Data Bus Strobe Signals WE3, WE2, WE1, WE0, D31 to D23 to D15 to D7 to DQMUU DQMUU DQMUU DQMUU DQMUL DQMUL DQMUL DQMUL DQMLU DQMLU DQMLU...
Page 250: Description Of Areas
Section 8 Bus State Controller (BSC) 8.5.2 Description of Areas Area 0: Area 0 physical addresses A28 to A26 are 000. Addresses A31 to A29 are ignored and the address range is H'00000000 + H'20000000 × n – H'03FFFFFF + H'20000000 × n (n = 0 to 6 and n = 1 to 6 are the shadow spaces).
Page 251 Section 8 Bus State Controller (BSC) When synchronous DRAM is connected, the RASU, RASL signal, CASU, CASL signal, RD/WR signal, and byte controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed. Control of RASU, RASL, CASU, CASL, data timing, and address multiplexing is set with MCR.
Page 252 Section 8 Bus State Controller (BSC) interface address range comprises the 32 Mbytes at H'16000000 + H'20000000 × n to H'17FFFFFF + H'20000000 x n (where n = 0 to 6, and n = 1 to 6 represents shadow space). For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width using the A5SZ1 to A5SZ0 bits of BCR2.
Page 253: Basic Interface
Section 8 Bus State Controller (BSC) to A6W0 bits of WCR2 and the A6W3 bit of PCR. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). The bus cycle pitch of the burst cycle is determined within a range of 2 to 11 (2 to 39 for the PCMCIA interface) according to the number of waits.
Page 254: Figure 8.5 Basic Timing Of Basic Interface
Section 8 Bus State Controller (BSC) CKIO A25 to A0 RD/WR Read D31 to D0 Write D31 to D0 Figure 8.5 Basic Timing of Basic Interface Rev. 5.00 May 29, 2006 page 206 of 698 REJ09B0146-0500...
Page 255: Figure 8.6 Example Of 32-Bit Data-Width Static Ram Connection
Section 8 Bus State Controller (BSC) Figures 8.6, 8.7, and 8.8 show examples of connection to 32, 16, and 8-bit data-width static RAM, respectively. 128k × 8-bit This LSI SRAM I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 I/O7 I/O0 Figure 8.6 Example of 32-Bit Data-Width Static RAM Connection Rev.
Page 256: Figure 8.7 Example Of 16-Bit Data-Width Static Ram Connection
Section 8 Bus State Controller (BSC) 128k × 8-bit This LSI SRAM I/O7 I/O0 I/O7 I/O0 Figure 8.7 Example of 16-Bit Data-Width Static RAM Connection 128k × 8-bit This LSI SRAM I/O7 I/O0 Figure 8.8 Example of 8-Bit Data-Width Static RAM Connection Rev.
Page 257: Figure 8.9 Basic Interface Wait Timing (Software Wait Only)
Section 8 Bus State Controller (BSC) Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. For details, see section 8.4.4, Wait State Control Register 2 (WCR2) The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing shown in figure 8.9.
Page 258: Figure 8.10 Basic Interface Wait State Timing
Section 8 Bus State Controller (BSC) However, the WAIT signal is ignored in the following cases: • In 16-byte DMA transfer or dual addressing mode, or when writing data to the external address area • In 16-byte DMA transfer or single addressing mode, or when transferring data from an external device with DACK to the external address area •...
Page 259: Synchronous Dram Interface
Section 8 Bus State Controller (BSC) 8.5.4 Synchronous DRAM Interface Synchronous DRAM Direct Connection Since synchronous DRAM can be selected by the CS signal, physical space areas 2 and 3 can be connected using RAS and other control signals in common. If the memory type bits (DRAMTP2 to 0) in BCR1 are set to 010, area 2 is ordinary memory space and area 3 is synchronous DRAM space;...
Page 260: Figure 8.11 Example Of 64-Mbit Synchronous Dram Connection (32-Bit Bus Width)
Section 8 Bus State Controller (BSC) 64M synchronous DRAM (1M × 16-bit × 4-bank) This LSI CKIO RASx CASx RD/WR DQ15 DQMU DQMUU DQML DQMUL DQMLU DQMLL DQ15 DQMU DQML Note: "x" is U or L Figure 8.11 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width) Rev.
Page 261: Figure 8.12 Example Of 64-Mbit Synchronous Dram (16-Bit Bus Width)
Section 8 Bus State Controller (BSC) 64M synchronous DRAM 1M × 16-bit × 4-bank This LSI CKIO RASx CASx RD/WR DQ15 DQMU DQMLU DQML DQMLL Figure 8.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width) Address Multiplexing Synchronous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMX3-AMX0 in MCR.
Page 262: Table 8.17 Relationship Between Bus Width, Amx, And Address Multiplex Output
Section 8 Bus State Controller (BSC) Table 8.17 Relationship between Bus Width, AMX, and Address Multiplex Output Setting External Address Pins Output Memory Timing Width Type AMX3 AMX2 AMX1 AMX0 A1 to A8 L/H * A24 * A25 * 32 bits 4M ×...
Page 263: Table 8.18 Example Of Correspondence Between This Lsi And Synchronous Dram Address Pins (Amx (3 To 0) = 0100 (32-Bit Bus Width))
Section 8 Bus State Controller (BSC) Table 8.18 Example of Correspondence between this LSI and Synchronous DRAM Address Pins (AMX (3 to 0) = 0100 (32-Bit Bus Width)) Address Pin of this LSI Synchronous DRAM Address Pin RAS Cycle CAS Cycle Function A13(BA1) BANK select address...
Page 264: Figure 8.13 Basic Timing For Synchronous Dram Burst Read
Section 8 Bus State Controller (BSC) The example in figure 8.13 shows the basic timing. To connect low-speed synchronous DRAM, the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by the RCD bit in MCR, with a values of 0 to 3 specifying 1 to 4 cycles, respectively.
Page 265: Figure 8.14 Synchronous Dram Burst Read Wait Specification Timing
Section 8 Bus State Controller (BSC) Figure 8.14 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10, and TPC is set to 1. The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal space access, is asserted in each of cycles Td1 to Td4 in a synchronous DRAM cycle.
Page 266: Figure 8.15 Basic Timing For Synchronous Dram Single Read
Section 8 Bus State Controller (BSC) Single Read Figure 8.15 shows the timing when a single address read is performed. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed.
Page 267: Figure 8.16 Basic Timing For Synchronous Dram Burst Write
Section 8 Bus State Controller (BSC) Tc1, Tc2, and Tc3 cycles, and a WRITA command that performs auto-precharge is issued in the Tc4 cycle. In the write cycle, the write data is output at the same time as the write command. In case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed.
Page 268: Figure 8.17 Basic Timing For Synchronous Dram Single Write
Section 8 Bus State Controller (BSC) Single Write The basic timing chart for write access is shown in figure 8.17. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle.
Page 269 Section 8 Bus State Controller (BSC) Bank Active The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends.
Page 270 Section 8 Bus State Controller (BSC) A Tnop cycle, in which no operation is performed, is inserted before the Tc1 cycle in which the READ command is issued in figure 8.19, but when synchronous DRAM is read, there is a two- cycle latency for the DQMxx signal that performs the byte specification.
Page 271: Figure 8.18 Burst Read Timing (No Precharge)
Section 8 Bus State Controller (BSC) Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO Address upper bits A12 or A11 * Address lower bits * CS2 or CS3 RASx CASx RD/WR DQMxx D31 to D0 Notes: 1. Command bit Column address Figure 8.18 Burst Read Timing (No Precharge) Rev.
Page 272: Figure 8.19 Burst Read Timing (Same Row Address)
Section 8 Bus State Controller (BSC) Tnop Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO Address upper bits A12 or A11 * Address lower bits * CS2 or CS3 RASx CASx RD/WR DQMxx D31 to D0 Notes: 1. Command bit Column address Figure 8.19 Burst Read Timing (Same Row Address) Rev.
Page 273: Figure 8.20 Burst Read Timing (Different Row Addresses)
Section 8 Bus State Controller (BSC) Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO Address upper bits A12 or A11 * Address lower bits * CS2 or CS3 RASx CASx RD/WR DQMxx D31 to D0 Notes: 1. Command bit Column address Figure 8.20 Burst Read Timing (Different Row Addresses) Rev.
Page 274: Figure 8.21 Burst Write Timing (No Precharge)
Section 8 Bus State Controller (BSC) CKIO Address upper bits A12 or A11 * Address lower bits * CS2 or CS3 RASx CASx RD/WR DQMxx D31 to D0 Notes: 1. Command bit Column address Figure 8.21 Burst Write Timing (No Precharge) Rev.
Page 275: Figure 8.22 Burst Write Timing (Same Row Address)
Section 8 Bus State Controller (BSC) CKIO Address upper bits A12 or A11 * Address lower bits * CS2 or CS3 RASx CASx RD/WR DQMxx D31 to D0 Notes: 1. Command bit Column address Figure 8.22 Burst Write Timing (Same Row Address) Rev.
Page 276: Figure 8.23 Burst Write Timing (Different Row Addresses)
Section 8 Bus State Controller (BSC) CKIO Address upper bits A12 or A11 * Address lower bits * CS2 or CS3 RASx CASx RD/WR DQMxx D31 to D0 Notes: 1. Command bit Column address Figure 8.23 Burst Write Timing (Different Row Addresses) Refreshing The bus state controller is provided with a function for controlling synchronous DRAM refreshing.
Page 277: Figure 8.24 Auto-Refresh Operation
Section 8 Bus State Controller (BSC) 1. Auto-Refreshing Figure 8.24 shows the auto-refreshing operation. Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to 0 in RTCSR, and the value set in RTCOR. The value of bits CKS2 to 0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the synchronous DRAM used.
Page 278: Figure 8.25 Synchronous Dram Auto-Refresh Timing
Section 8 Bus State Controller (BSC) TRrw TRrw (Tpc) CKIO RASU, RASL CASU, CASL RD/WR Figure 8.25 Synchronous DRAM Auto-Refresh Timing 2. Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1.
Page 279: Figure 8.26 Synchronous Dram Self-Refresh Timing
Section 8 Bus State Controller (BSC) When using synchronous DRAM, use the following procedure to initiate self-refreshing. 1. Clear the refresh control bit to 0. 2. Write H'00 to the RTCNT register. 3. Set the refresh control bit and refresh mode bit to 1. TRs1 (TRs2) (TRs2)
Page 280 Section 8 Bus State Controller (BSC) Power-On Sequence In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the RAS, CAS, and RD/WR signals.
Page 281: Figure 8.27 Synchronous Dram Mode Write Timing
Section 8 Bus State Controller (BSC) Before mode register setting, a 100 µs idle time (depending on the memory manufacturer) must be guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width is greater than this idle time, there is no problem in performing mode register setting immediately. The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed.
Page 282: Burst Rom Interface
Section 8 Bus State Controller (BSC) 8.5.5 Burst ROM Interface Setting bits A0BST (1 to 0), A5BST (1 to 0), and A6BST (1 to 0) in BCR1 to a non-zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high- speed access to ROM that has a nibble access function.
Page 283: Figure 8.28 Burst Rom Wait Access Timing
Section 8 Bus State Controller (BSC) CKIO A25 to A4 A3 to A0 RD/WR D31 to WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 8.28 Burst ROM Wait Access Timing Rev. 5.00 May 29, 2006 page 235 of 698 REJ09B0146-0500...
Page 284: Pcmcia Interface
Section 8 Bus State Controller (BSC) CKIO A25 to A4 A3 to A0 RD/WR D31 to D0 WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 8.29 Burst ROM Basic Access Timing 8.5.6 PCMCIA Interface In this LSI, setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical space area 5 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2 (PCMCIA2.1).
Page 285: Figure 8.30 Pcmcia Space Allocation
Section 8 Bus State Controller (BSC) Figure 8.31 shows an example of PCMCIA card connection to this LSI. To enable active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between this LSI bus interface and the PCMCIA cards. As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications, the PCMCIA interface for this LSI in big-endian mode is stipulated independently.
Page 286: Figure 8.31 Example Of Pcmcia Interface
Section 8 Bus State Controller (BSC) A24 to A0 A25 to A0 D15 to D0 D7 to D0 RD/WR CE1B/(CS6) D15 to D0 CE1A/(CS5) CE2B CE2A D15 to D8 PC card (memory/IO) This LSI WE/PGM ICIORD (IORD) ICIOWR (IOWR) WAIT WAIT IOIS16 (IOIS16)
Page 287: Figure 8.32 Basic Timing For Pcmcia Memory Card Interface
Section 8 Bus State Controller (BSC) Memory Card Interface Basic Timing: Figure 8.32 shows the basic timing for the PCMCIA IC memory card interface. When physical space areas 5 and 6 are designated as PCMCIA interface areas, bus accesses are automatically performed as IC memory card interface accesses. With a high external bus frequency (CKIO), the setup and hold times for the address (A24 to A0), card enable (CS5, CE2A, CS6, CE2B), and write data (D15 to D0) in a write cycle, become insufficient with respect to RD and WR (the WE pin in this LSI).
Page 288: Figure 8.33 Wait Timing For Pcmcia Memory Card Interface
Section 8 Bus State Controller (BSC) Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A0 CExx RD/WR (read) D15 to D0 (read) (write) D15 to D0 (write) WAIT Figure 8.33 Wait Timing for PCMCIA Memory Card Interface Rev. 5.00 May 29, 2006 page 240 of 698 REJ09B0146-0500...
Page 289: Figure 8.34 Basic Timing For Pcmcia Memory Card Interface Burst Access
Section 8 Bus State Controller (BSC) Memory Card Interface Burst Timing: In this LSI, when the IC memory card interface is selected, page mode burst access mode can be used, for read access only, by setting bits A5BST1 and A5BST0 in BCR1 for physical space area 5, or bits A6BST1 and A6BST0 in BCR1 for area 6.
Page 290: Figure 8.35 Wait Timing For Pcmcia Memory Card Interface Burst Access
Section 8 Bus State Controller (BSC) Tpcm0 Tpcm1 Tpcm1wTpcm1wTpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A4 A3 to A0 CExx RD/WR (read) D15 to D0 (read) WAIT Figure 8.35 Wait Timing for PCMCIA Memory Card Interface Burst Access When the entire 32-Mbyte memory space is used as IC memory card interface space, the common memory/attribute memory switching signal REG is generated using a port, etc.
Page 291 Section 8 Bus State Controller (BSC) I/O Card Interface Timing: Figures 8.36 and 8.37 show the timing for the PCMCIA I/O card interface. Switching between the I/O card interface and the IC memory card interface is performed according to the accessed address. When PCMCIA is designed for physical space area 5, the bus access is automatically performed as an I/O card interface access when a physical address from H'16000000 to H'17FFFFFF is accessed.
Page 292: Figure 8.36 Basic Timing For Pcmcia I/O Card Interface
Section 8 Bus State Controller (BSC) Tpci1 Tpci2 CKIO A25 to A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) Figure 8.36 Basic Timing for PCMCIA I/O Card Interface Rev. 5.00 May 29, 2006 page 244 of 698 REJ09B0146-0500...
Page 293: Figure 8.37 Wait Timing For Pcmcia I/O Card Interface
Section 8 Bus State Controller (BSC) Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO A25 to A0 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) WAIT IOIS16 Figure 8.37 Wait Timing for PCMCIA I/O Card Interface Rev.
Page 294: Figure 8.38 Dynamic Bus Sizing Timing For Pcmcia I/O Card Interface
Section 8 Bus State Controller (BSC) Tpci0 Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w CKIO A25 to A1 CExx RD/WR ICIORD (read) D15 to D0 (read) ICIOWR (write) D15 to D0 (write) WAIT IOIS16 Figure 8.38 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.
Page 295: Waits Between Access Cycles
Section 8 Bus State Controller (BSC) 8.5.7 Waits between Access Cycles A problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with data in the next access.
Page 296: Bus Arbitration
Section 8 Bus State Controller (BSC) Twait Twait CKIO A25 to A0 RD/WR D31 to D0 Area m read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification Figure 8.39 Waits between Access Cycles 8.5.8 Bus Arbitration When a bus release request (BREQ) is received from an external device, buses are released after...
Page 297: Bus Pull-Up
Section 8 Bus State Controller (BSC) IRQOUT IRQOUT IRQOUT IRQOUT Pin Assertion Conditions: • When a memory refresh request has been generated but the refresh cycle has not yet begun • When an interrupt is generated with an interrupt request level higher than the setting of the interrupt mask bits (I3 to I0) in the status register (SR).
Page 298: Figure 8.41 Pins D31 To D0 Pull-Up Timing (Read Cycle)
Section 8 Bus State Controller (BSC) CKIO Pull-up Pull-up D31 to D0 Figure 8.41 Pins D31 to D0 Pull-Up Timing (Read Cycle) CKIO Pull-up Pull-up D31 to D0 Figure 8.42 Pins D31 to D0 Pull-Up Timing (Write Cycle) Rev. 5.00 May 29, 2006 page 250 of 698 REJ09B0146-0500...
Page 299: Section 9 Direct Memory Access Controller (Dmac)
Section 9 Direct Memory Access Controller (DMAC) Section 9 Direct Memory Access Controller (DMAC) This chip includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip peripheral modules (SCIF, A/D converter, and D/A converter).
Page 300 Section 9 Direct Memory Access Controller (DMAC) • Reload function: The value that was specified in the source address register can be automatically reloaded every 4 DMA transfers. This function is only valid in channel 2. • Three types of Transfer requests ...
Page 301: Figure 9.1 Dmac Block Diagram
Section 9 Direct Memory Access Controller (DMAC) DMAC module Interation SAR_n control Register DAR_n control On-chip DMATCR_n peripheral Start-up module control CHCR_n DMAOR DREQ0, DREQ1 SCIF Request A/D converter priority control DEI_n DACK0, DACK1 DRAK0, DRAK1 External Bus interface External Legend: External I/O DMAOR:...
Page 302: Input/Output Pin
Section 9 Direct Memory Access Controller (DMAC) Input/Output Pin Table 9.1 shows the DMAC pins. Table 9.1 Pin Configuration Channel Name Symbol Function DREQ0 DMA transfer request DMA transfer request input from external device to channel 0 DREQ acknowledge DACK0 Strobe output to an external I/O at DMA transfer request from external device to channel 0...
Page 303: Dma Source Address Registers 0 To 3 (Sar_0 To Sar_3)
Section 9 Direct Memory Access Controller (DMAC) Channel 2 • DMA source address register 2 (SAR2) • DMA destination address register 2 (DAR2) • DMA transfer count register 2 (DMATCR2) • DMA channel control register 2 (CHCR2) Channel 3 • DMA source address register 3 (SAR3) •...
Page 304: Dma Transfer Count Registers 0 To 3 (Dmatcr_0 To Dmatcr_3)
Section 9 Direct Memory Access Controller (DMAC) 9.3.3 DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3) DMA transfer count registers 0 to 3 (DMATCR_0 to DMATCR_3) are 24-bit read/write registers that specify the DMA transfer count (bytes, words, or longwords) in each channel. The number of transfers is 1 when the setting is H'000001, and 16777216 (the maximum) when H'000000 is set.
Page 305 Section 9 Direct Memory Access Controller (DMAC) Bit Name Initial Value Description 31 to — All 0 Reserved These bits are always read as 0. The write value should always be 0. (R/W) * Direct/Indirect Selection DI selects direct address mode or indirect address mode in channel 3.
Page 306 Section 9 Direct Memory Access Controller (DMAC) Bit Name Initial Value Description (R/W) * Acknowledge Mode AM specifies whether DACK is output in data read cycle or in data write cycle in dual address mode. This bit is only valid in CHCR_0 and CHCR_1. Writing to this bit is invalid in CHCR_2 and CHCR_3;...
Page 307 Section 9 Direct Memory Access Controller (DMAC) Bit Name Initial Value Description Source Address Mode SM1 and SM0 select whether the DMA source address is incremented, decremented, or left fixed. 00: Fixed source address 01: Source address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 10: Source address is decremented (–1 in 8-bit...
Page 308 Section 9 Direct Memory Access Controller (DMAC) Bit Name Initial Value Description Resource Select RS3 to RS0 specify which transfer requests will be sent to the DMAC. 0000: External request, dual address mode 0001: Reserved (Setting prohibited) 0010: External request / Single address mode External address space →...
Page 309 Section 9 Direct Memory Access Controller (DMAC) Bit Name Initial Value Description — Reserved This bit is always read 0. The write value should always be 0. DREQ Select Bit (R/W) * DS selects the sampling method of the DREQ pin that is used in external request mode is detection in low level or at the falling edge.
Page 310 Section 9 Direct Memory Access Controller (DMAC) Bit Name Initial Value Description R/(W) * Transfer End TE is set to 1 when data transfer ends by the count specified in DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. Before this bit is set to 1, if data transfer ends due to an NMI interrupt, a DMAC address error, or clearing the DE bit or the DME bit in DMAOR, this...
Page 311: Dma Operation Register (Dmaor)
Section 9 Direct Memory Access Controller (DMAC) 9.3.5 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMAC transfer mode. This register's values are initialized to 0s by resets. The previous value is held in standby mode. Bit Name Initial Value Description...
Page 312 Section 9 Direct Memory Access Controller (DMAC) Bit Name Initial Value Description R/(W) * NMI Flag NMIF NMIF indicates that an NMI interrupt occurred. This bit is set regardless of whether DMAC is in operating or halt state. If this bit is set during data transfer, the transfer on all channels are suspended.
Page 313: Operation
Section 9 Direct Memory Access Controller (DMAC) Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request.
Page 314: Figure 9.2 Dmac Transfer Flowchart
Section 9 Direct Memory Access Controller (DMAC) Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and NMIF, TE = 0? Transfer request occurs? * Bus mode, transfer request mode, DREQ detection selection system Transfer (1 transfer unit); DMATCR –...
Page 315: Dma Transfer Requests
Section 9 Direct Memory Access Controller (DMAC) 9.4.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by external devices and on-chip peripheral modules that are neither the source nor the destination.
Page 316: Table 9.3 Selecting On-Chip Peripheral Module Request Modes With The Rs Bit
Section 9 Direct Memory Access Controller (DMAC) On-Chip Peripheral Module Request: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. This mode cannot be set in case of 16-byte transfer. The transfer request signals include 4 signals: the receive data full interrupts (RXI) and the transmit data empty interrupts (TXI) from serial communication interfaces (SCIF), the A/D conversion end interrupt (ADI) of the A/D converter, and the compare match timer interrupt (CMI) of the CMT.
Page 317: Channel Priority
Section 9 Direct Memory Access Controller (DMAC) The DMA transfer request signals of table 9.3 are automatically withdrawn when the corresponding DMA transfer is performed. If the cycle-steal mode is being used, they are withdrawn at the first transfer; if the burst mode is being used, they are withdrawn at the last transfer.
Page 318: Figure 9.3 Round-Robin Mode
Section 9 Direct Memory Access Controller (DMAC) (1) When channel 0 transfers Initial priority order Channel 0 becomes bottom CH0 > CH1 > CH2 > CH3 priority Priority order CH1 > CH2 > CH3 > CH0 afrer transfer (2) When channel 1 transfers Channel 0 becomes bottom Initial priority order CH0 >...
Page 319: Figure 9.4 Changes In Channel Priority In Round-Robin Mode
Section 9 Direct Memory Access Controller (DMAC) Figure 9.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1.
Page 320: Dma Transfer Types
Section 9 Direct Memory Access Controller (DMAC) 9.4.4 DMA Transfer Types The DMAC supports the transfers shown in table 9.4. The dual address mode has the direct address mode and the indirect address mode. In the direct address mode, an output address value is the data transfer target address;...
Page 321: Figure 9.5 Operation In The Direct Address Mode In The Dual Address Mode
Section 9 Direct Memory Access Controller (DMAC) Address Modes: • Dual Address Mode In the dual address mode, both the transfer source and destination are accessed (selectable) by an address. The source and destination can be located externally or internally. The dual address mode has (1) direct address transfer mode and (2) indirect address transfer mode.
Page 322: Figure 9.6 Example Of Dma Transfer Timing In The Direct Address Mode In The Dual Address Mode (Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)
Section 9 Direct Memory Access Controller (DMAC) CKIO Transfer source Transfer destination A25 to A0 address address D31 to D0 DACKn Data read cycle Data write cycle (1st cycle) (2nd cycle) Note: Transfer between external memories, DACK output in a read cycle DACK output timing is the same as that of CSn.
Page 323: Figure 9.7 Example Of Dma Transfer Timing In The Direct Address Mode In The Dual Address Mode (16-Byte Transfer, Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)
Section 9 Direct Memory Access Controller (DMAC) CKIO A25 to A0 Transfer Transfer source address destination address D31 to D0 DACKn Data read cycle (1st cycle) (2nd cycle) Note: Transfer between external memories, DACK output in a read cycle DACK output timing is the same as that of CSn.
Page 324 Section 9 Direct Memory Access Controller (DMAC) (2) In the indirect address transfer mode, the address of memory in which data to be transferred is stored is specified in the transfer source address register (SAR_3) in the DMAC. In this mode, the address value specified in the transfer source address register in the DMAC is read first.
Page 325: Figure 9.9 Operation In The Indirect Address Mode In The Dual Address Mode (When The External Memory Space Has A 16-Bit Width)
Section 9 Direct Memory Access Controller (DMAC) SAR_3 Memory DAR_3 Transfer source module Temporary buffer Transfer destination Data module buffer When the value in SAR_3 is an address, the memory data is read and the value is stored in the temporary buffer. The value to be read must be 32 bits since it is used for the address.
Page 326: Figure 9.10 Example Of Transfer Timing In The Indirect Address Mode In The Dual Address Mode
Section 9 Direct Memory Access Controller (DMAC) Transfer source Transfer source Transfer destination A25 to A0 Indirect address address (H) address (L) address Transfer Transfer Indirect Indirect D31 to D0 data data address(H) address(L) Transfer source Internal Indirect address * addresu bus address Internal...
Page 327: Figure 9.11 Data Flow In The Single Address Mode
Section 9 Direct Memory Access Controller (DMAC) • Single Address Mode In the single address mode, either the transfer source or transfer destination external device is accessed (selected) by means of the DACK signal, and the other device is accessed by address. In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer.
Page 328: Figure 9.12 Example Of Dma Transfer Timing In The Single Address Mode
Section 9 Direct Memory Access Controller (DMAC) Figures 9.12 to 9.14 show examples of DMA transfer timing in the single address mode. CKI0 Address output to external memory space A25 to A0 Write strobe signal to external memory space D31 to D0 Data output from external device with DACK DACKn DACK signal (active-low) to external device with DACK...
Page 329: Figure 9.13 Example Of Dma Transfer Timing In The Single Address Mode (16-Byte Transfer, External Memory Space (Ordinary Memory) → External Device With Dack)
Section 9 Direct Memory Access Controller (DMAC) CKIO A25 to A0 Transfer source address D31 to D0 DACKn Figure 9.13 Example of DMA Transfer Timing in the Single Address Mode (16-Byte Transfer, External Memory Space (Ordinary Memory) → → → → External Device with DACK) Rev.
Page 330: Figure 9.14 Dma Transfer Example In The Cycle-Steal Mode
Section 9 Direct Memory Access Controller (DMAC) Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of CHCR_0 to CHCR_3 (one byte, word, or longword, or 16-byte data). • Cycle-Steal Mode In the cycle-steal mode, the bus right is given to another bus master after a one-transfer-unit (8-, 16-, or 32-bit unit) DMA transfer.
Page 331: Table 9.5 Relationship Of Request Modes And Bus Modes By Dma Transfer Category
Section 9 Direct Memory Access Controller (DMAC) Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 9.5 shows the relationship between request modes and bus modes by DMA transfer category. Table 9.5 Relationship of Request Modes and Bus Modes by DMA Transfer Category Address Request Transfer...
Page 332: Number Of Bus Cycle States And Dreq Pin Sampling Timing
Section 9 Direct Memory Access Controller (DMAC) Bus Mode and Channel Priority Order: When a given channel 1 is transferring in the burst mode and there is a transfer request to a channel 0 with a higher priority, the transfer of channel 0 will begin immediately.
Page 333 Section 9 Direct Memory Access Controller (DMAC) Operation • Cycle-Steal Mode In the cycle-steal mode, the DREQ sampling timing is the same regardless of whether level or edge detection is used. For example, in figure 9.17 (cycle-steal mode, level detection), DMAC transfer begins, at the earliest, three cycles after the first sampling is performed.
Page 334: Figure 9.17 Cycle-Steal Mode, Level Input (Cpu Access: 2 Cycles)
Section 9 Direct Memory Access Controller (DMAC) 1st sampling 2nd sampling 3rd sampling CKIO DREQ DRAK (High active) DMAC(Read) DMAC(Write) DMAC(Read) DMAC(Write) Bus cycle DACK Figure 9.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) 1st sampling 2nd sampling 3rd sampling CKIO DREQ DRAK...
Page 335: Figure 9.20 Cycle-Steal Mode, Level Input (Cpu Access: 2 Cycles, Dreq Input Delayed)
Section 9 Direct Memory Access Controller (DMAC) 2nd sampling is performed, 3rd sampling is performed, but since DREQ is high, but since DREQ is high, per-cycle sampling starts per-cycle sampling starts 1st sampling 2nd sampling 3rd sampling CKIO DREQ DRAK (High active) Bus cycle DMAC(Write)
Page 336: Source Address Reload Function
Section 9 Direct Memory Access Controller (DMAC) 1st sampling CKIO DREQ DRAK (High active) DMAC(Read) DMAC(Write) DMAC(Read) DMAC(Write) DMAC(Read) Bus cycle DACK Figure 9.23 Burst Mode, Edge Input 9.4.6 Source Address Reload Function Channel 2 includes a reload function, in which the value returns to the value set in the SAR_2 for each four transfers by setting the RO bit in CHCR_2 to 1.
Page 337: Figure 9.25 Timing Chart Of Source Address Reload Function
Section 9 Direct Memory Access Controller (DMAC) Internal SAR_2 DAR_2 SAR_2+2 DAR_2 SAR_2+4 DAR_2 SAR_2+6 DAR_2 SAR_2 address bus Internal SAR_2 data SAR_2+2 data SAR_2+4 data SAR_2+6 data data bus First transfer of channel 2 Second transfer Third transfer Fourth transfer Fifth transfer SAR_2 output SAR_2+2 output...
Page 338: Dma Transfer Ending Conditions
Section 9 Direct Memory Access Controller (DMAC) 9.4.7 DMA Transfer Ending Conditions The DMA transfer ending conditions vary for individual channels ending and all channels ending together. At transfer end, the following conditions are applied except the case where the value set in the DMATCR reaches 0.
Page 339 Section 9 Direct Memory Access Controller (DMAC) Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel's DMATCR is 0, or when the DE bit of the channel's CHCR is cleared to •...
Page 340: Compare Match Timer (Cmt)
Section 9 Direct Memory Access Controller (DMAC) Compare Match Timer (CMT) DMAC has an on-chip compare match timer (CMT) to generate DMA transfer request. The CMT has 16-bit counter. Figure 9.26 shows a CMT block diagram. 9.5.1 Feature The CMT has the following features: •...
Page 341: Register Description
Section 9 Direct Memory Access Controller (DMAC) 9.5.2 Register Description The CMT has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. • Compare match timer start register (CMSTR) • Compare match timer control/status register (CMCSR) •...
Page 342 Section 9 Direct Memory Access Controller (DMAC) Compare Match Timer Control/Status Register (CMCSR) The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, and establishes the clock used for incrementation. Bit Name Initial Value Description 15 to 8...
Page 343: Operation
Section 9 Direct Memory Access Controller (DMAC) Compare Match Counter (CMCNT) The compare match counter (CMCNT) is a 16-bit register used as an up-counter. When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR and the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock.
Page 344: Figure 9.28 Count Timing
Section 9 Direct Memory Access Controller (DMAC) CMCNT Count Timing One of four clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) obtained by dividing the peripheral clock (Pφ) can be selected by the CKS1 and CKS0 bits of the CMCSR. Figure 9.28 shows the timing. Peripheral clock (Pφ) CMT clock CMCNT0 input clock...
Page 345: Figure 9.29 Cmf Set Timing
Section 9 Direct Memory Access Controller (DMAC) Peripheral clock (Pφ) CMCNT input clock CMCNT CMCOR Compare match signal Figure 9.29 CMF Set Timing Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared by writing 0 to it after reading 1. Figure 9.30 shows the timing when the CMF bit is cleared by the CPU.
Page 346: Examples Of Use
Section 9 Direct Memory Access Controller (DMAC) Examples of Use 9.6.1 Example of DMA Transfer between A/D Converter and External Memory (Address Reload on) In this example, DMA transfer is performed between the on-chip A/D converter (transfer source) and the external memory (transfer destination) with address reload function on. Table 9.6 shows the transfer conditions and register settings.
Page 347: (Indirect Address On)
Section 9 Direct Memory Access Controller (DMAC) DAR_2 continues being decremented regardless of whether the address reload function is on or off. As a result, the values in the DMAC are as shown in table 9.7 when the fourth transfer ends, depending on whether the address reload function is on or off.
Page 348: Table 9.8 Transfer Conditions And Register Settings For Transfer Between External Memory And Scif Transmitter
Section 9 Direct Memory Access Controller (DMAC) Table 9.8 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter Transfer Conditions Register Setting Transfer source: external memory SAR_3 H'00400000 Value stored in address H'00400000 — H'00450000 Value stored in address H'04500000 —...
Page 349: Cautions
Section 9 Direct Memory Access Controller (DMAC) Cautions 1. CHCR_0 to CHCR_3 can be accessed in any data size. The DMA operation register (DMAOR) must be accessed in byte (eight bits) or word (16 bits); other registers must be accessed in word (16 bits) or longword (32 bits). 2.
Page 350 Section 9 Direct Memory Access Controller (DMAC) Note that no problem occurs if the clock ratio for Iφ:Bφ is 1:1 after modification of the bits. Furthermore, no problem occurs if the frequency multiplication ratio bits (STC[2:0]) are modified at the same time as IFC[2:0]. These problems may be avoided by either of the following measures.
Page 351: Section 10 Clock Pulse Generator (Cpg)
Section 10 Clock Pulse Generator (CPG) Section 10 Clock Pulse Generator (CPG) The clock pulse generator (CPG) supplies all clocks to the processor and controls the power-down modes. A block diagram of the clock pulse generator is shown in figure 10.1. 10.1 Feature The CPG has the following features:...
Page 352: Figure 10.1 Block Diagram Of Clock Pulse Generator
Section 10 Clock Pulse Generator (CPG) Clock pulse generator CAP1 Divider 1 × 1 PLL circuit 1 × 1/2 (× 1, 2, 3, 4) clock (Iφ) × 1/3 Cycle = Icyc CKIO × 1/4 Cycle = Bcyc CAP2 Divider 2 Crystal XTAL ×...
Page 353 Section 10 Clock Pulse Generator (CPG) The clock pulse generator blocks function as follows: 1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, or leaves unchanged the input clock frequency from the CKIO pin or PLL circuit 2. The multiplication rate is set by the frequency control register.
Page 354: Input/Output Pin
Section 10 Clock Pulse Generator (CPG) 10.2 Input/Output Pin Table 10.1 lists the CPG pins and their functions. Table 10.1 Clock Pulse Generator Pins and Functions Pin Name Symbol Description Mode control pins Set the clock operating mode. Crystal I/O pins (clock XTAL Connects a crystal oscillator.
Page 355: Table 10.2 Clock Operating Modes
Section 10 Clock Pulse Generator (CPG) Table 10.2 Clock Operating Modes Pin Values Clock I/O PLL2 PLL1 Divider 1 Divider 2 CKIO On/Off On/Off Input Input Frequency Mode MD2 MD1 MD0 Source Output EXTAL CKIO PLL1 output PLL1 (EXTAL) multiplication ratio: 1 (EXTAL) ×...
Page 356: Table 10.3 Available Combination Of Clock Mode And Frqcr Values
Section 10 Clock Pulse Generator (CPG) As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for connection of synchronous DRAM. Table 10.3 Available Combination of Clock Mode and FRQCR Values Clock Rate * Clock CKIO Frequency Mode FRQCR *...
Page 357 Section 10 Clock Pulse Generator (CPG) Clock Rate * Clock CKIO Frequency Mode FRQCR * PLL1 PLL2 (I:B:P) Input Frequency Range Range H'0100 ON (× 1) 1:1:1 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz H'0101 ON (× 1) 1:1:1/2 25 MHz to 66.67 MHz 25 MHz to 66.67 MHz...
Page 358: Register Description
Section 10 Clock Pulse Generator (CPG) 6. × 1, × 2, × 3, or × 4 can be used as the multiplication ratio of PLL circuit 1. × 1, × 1/2, × 1/3, and × 1/4 can be selected as the division ratios of dividers 1 and 2. Set the rate in the frequency control register.
Page 359 Section 10 Clock Pulse Generator (CPG) Bit Name Initial Value Description IFC2 CPU Clock Frequency Division Ratio IFC1 These bits specify the frequency division ratio (Divider 1) of the CPU clock with respect to the IFC0 output frequency of PLL circuit 1. 000: ×...
Page 360: Operation
Section 10 Clock Pulse Generator (CPG) 10.5 Operation The frequency of the CPU clock and peripheral clock can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of dividers 1 and 2. All of these are controlled by software through the frequency control register.
Page 361: Usage Note
Section 10 Clock Pulse Generator (CPG) 10.6 Usage Note When Using an External Crystal Oscillator: Place the crystal oscillator, capacitors CL1 and CL2, close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the oscillator, and do not locate a wiring pattern near these components.
Page 362: Figure 10.3 Points For Attention When Using Pll Oscillator Circuit
Section 10 Clock Pulse Generator (CPG) Avoid crossing signal lines (PLL2) Power supply CAP2 (PLL2) Reference values C1 = 470 pF C2 = 470 pF (PLL1) CAP1 (PLL1) Figure 10.3 Points for Attention when Using PLL Oscillator Circuit −PLL1, V −PLL2, Notes on Wiring Power Supply Pins: To avoid crossing signal lines, wire V −PLL2 as three patterns from the power supply source on the board so that they are...
Page 363: Section 11 Watchdog Timer (Wdt)
Section 11 Watchdog Timer (WDT) Section 11 Watchdog Timer (WDT) The WDT is a single-channel timer that counts the clock settling time and is used when clearing software standby mode and temporary standbys, such as frequency changes. It can also be used as an ordinary watchdog timer or interval timer.
Page 364: Register Description
Section 11 Watchdog Timer (WDT) 11.2 Register Description The WDT has two registers that select the clock, switch the timer mode, and perform other functions. Refer to section 23, List of Registers, for more details of the addresses and access sizes. •...
Page 365 Section 11 Watchdog Timer (WDT) Bit Name Initial Value R/W Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT in software standby mode or when changing the clock frequency. 0: Timer disabled: Count-up stops and WTCNT value is retained 1: Timer enabled WT/IT...
Page 366: Notes On Register Access
Section 11 Watchdog Timer (WDT) Bit Name Initial Value R/W Description 2 to 0 CKS2 to Clock Select 2 to 0 CKS0 These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock.
Page 367: Operation
Section 11 Watchdog Timer (WDT) WTCNT write Address: H'FFFFFF84 H'5A Write data WTCSR write Address: H'FFFFFF86 H'A5 Write data Figure 11.2 Writing to WTCNT and WTCSR 11.3 Operation 11.3.1 Canceling Software Standbys The WDT can be used to cancel software standby mode with an NMI or other interrupts. The procedure is described below.
Page 368: Changing The Frequency
Section 11 Watchdog Timer (WDT) 11.3.2 Changing the Frequency To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
Page 369: Using Interval Timer Mode
Section 11 Watchdog Timer (WDT) 11.3.4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in the WTCSR register to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter.
Page 370 Section 11 Watchdog Timer (WDT) Rev. 5.00 May 29, 2006 page 322 of 698 REJ09B0146-0500...
Page 371: Section 12 Timer Unit (Tmu)
Section 12 Timer Unit (TMU) Section 12 Timer Unit (TMU) This LSI uses a three-channel (channels 0 to 2) 32-bit timer unit (TMU). Figure 12.1 shows a block diagram of the TMU. 12.1 Feature The TMU has the following features: •...
Page 372: Figure 12.1 Tmu Block Diagram
Section 12 Timer Unit (TMU) Bus interface Prescaler Pφ TOCR TCLK Clock controller RTCCLK TSTR Ch. 0 TCR_0 Counter controller TCNT_0 TCOR_0 Interrupt TUNI0 controller Ch. 1 TCR_1 Counter controller TCNT_1 TCOR_1 Interrupt TUNI1 controller Ch. 2 TCR_2 Counter TCPR_2 controller TCNT_2 TCOR_2...
Page 373: Input/Output Pin
Section 12 Timer Unit (TMU) 12.2 Input/Output Pin Table 12.1 shows the pin configuration of the TMU. Table 12.1 Pin Configuration Channel Description Clock input/clock output TCLK External clock input pin/input capture control input pin/realtime clock (RTC) output pin 12.3 Register Description The TMU has the following registers.
Page 374: Timer Output Control Register (Tocr)
Section 12 Timer Unit (TMU) 12.3.1 Timer Output Control Register (TOCR) TOCR is an 8-bit read/write register that selects whether to use the external TCLK pin as an external clock or an input capture control usage input pin, or an output pin for the on-chip RTC output clock.
Page 375: Timer Start Register (Tstr)
Section 12 Timer Unit (TMU) 12.3.2 Timer Start Register (TSTR) TSTR is an 8-bit read/write register that selects whether to run or halt the timer counters (TCNT_0 to TCNT_2) for channels 0 to 2. TSTR is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode when the input clock selected for the channel is the on-chip RTC clock (RTCCLK).
Page 376: Timer Control Registers 0 To 2 (Tcr_0 To Tcr_2)
Section 12 Timer Unit (TMU) 12.3.3 Timer Control Registers 0 to 2 (TCR_0 to TCR_2) The timer control registers (TCR_0 to TCR_2) control the timer counters (TCNT_0 to TCNT_2) and interrupts. The TMU has three TCR_0 to TCR_2 registers for each channel. The TCR_0 to TCR_2R registers are 16-bit read/write registers that control the issuance of interrupts when the flag indicating timer counter (TCNT_0 to TCNT_2) underflow has been set to 1, and also carry out counter clock selection.
Page 377 Section 12 Timer Unit (TMU) Bit Name Initial Value Description CKEG1 Clock Edge 1 and 0 CKEG0 These bits select the external clock edge when the external clock is selected, or when the input capture function is used. 00: Count/capture register set on rising edge 01: Count/capture register set on falling edge 1X: Count/capture register set on both rising and falling edge...
Page 378 Section 12 Timer Unit (TMU) Bit Name Initial Value Description ICPF Input Capture Interrupt Flag A function of channel 2 only: the flag is set when input capture is requested via the TCLK pin. 0: No input capture request has been issued. Clearing condition: When 0 is written to ICPF 1: Input capture has been requested via the TCLK pin.
Page 379: Timer Constant Registers 0 To 2 (Tcor_0 To Tcor_2)
Section 12 Timer Unit (TMU) Bit Name Initial Value Description UNIE Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT_2 underflow has been set to 1. 0: Interrupt due to UNF (TUNI) is not enabled. 1: Interrupt due to UNF (TUNI) is enabled.
Page 380: Timer Counters 0 To 2 (Tcnt_0 To Tcnt_2)
Section 12 Timer Unit (TMU) 12.3.5 Timer Counters 0 to 2 (TCNT_0 to TCNT_2) TCNT counts down according to the input of a clock. The timer counters are 32-bit read/write registers. The TMU has three timer counters, one for each channel.The clock input is selected using the TPSC2 to TPSC0 bits in the TCR_0 to TCR_2.
Page 381: Counter Operation
Section 12 Timer Unit (TMU) 12.4.1 Counter Operation When the STR0 to STR2 bits in TSTR are set to 1, the corresponding timer counter (TCNT) starts counting. When a TCNT underflows, the UNF flag of the corresponding timer control register (TCR) is set.
Page 382: Figure 12.3 Auto-Reload Count Operation
Section 12 Timer Unit (TMU) Auto-reload count operation Figure 12.3 shows the TCNT auto-reload operation. TCOR value set to TCNT value TCNT during underflow TCOR H'00000000 Time STR0 to STR2 Figure 12.3 Auto-Reload Count Operation TCNT count timing 1. Internal Clock Operation: Set the TPSC2 to TPSC0 bits in TCR to select whether peripheral module clock Pφ...
Page 383: Figure 12.5 Count Timing When External Clock Is Operating (Both Edges Detected)
Section 12 Timer Unit (TMU) 2. External Clock Operation: Set the TPSC2 to TPSC0 bits in TCR to select the external clock (TCLK) as the timer clock. Use the CKEG1 and CKEG0 bits in TCR to select the detection edge. Rise, fall or both may be selected. The pulse width of the external clock must be at least 1.5 peripheral module clock cycles for single edges or 2.5 peripheral module clock cycles for both edges.
Page 384: Input Capture Function
Section 12 Timer Unit (TMU) 12.4.2 Input Capture Function Channel 2 has an input capture function (figure 12.7). When using the input capture function, set the TCLK pin to input mode with the TCOE bit in the timer output control register (TOCR) and set the timer operation clock to internal clock or on-chip RTC clock with the TPCS2 to TPCS0 bits in the timer control register (TCR_2).
Page 385: Interrupts
Section 12 Timer Unit (TMU) 12.5 Interrupts There are two sources of TMU interrupts: underflow interrupts (TUNI) and interrupts when using the input capture function (TICPI2). 12.5.1 Status Flag Set Timing UNF is set to 1 when the TCNT underflows. Figure 12.8 shows the timing. Pφ...
Page 386: Interrupt Sources And Priorities
Section 12 Timer Unit (TMU) 12.5.3 Interrupt Sources and Priorities The TMU produces underflow interrupts for each channel. When the interrupt request flag and interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the exception event register (INTEVT, INTEVT2) for these interrupts and interrupt processing occurs according to the codes.
Page 387: Section 13 Realtime Clock (Rtc)
Section 13 Realtime Clock (RTC) Section 13 Realtime Clock (RTC) This LSI has a realtime clock (RTC) with its own 32.768-kHz crystal oscillator. A block diagram of the RTC is shown in figure 13.1. 13.1 Feature The RTC has following features: •...
Page 388: Figure 13.1 Rtc Block Diagram
Section 13 Realtime Clock (RTC) Externally connected circuit EXTAL2 second Reset 128 Hz Oscillator circuit XTAL2 R64CNT 32.768 kHz interface RSECCNT Prescaler RMINCNT (÷ 2) RHRCNT 16.384 kHz RTCCLK RWKCNT RDAYCNT Prescaler (÷ 128) RMONCNT RYRCNT Interrupt Comparator control circuit RSECAR RMINAR Carry...
Page 389: Input/Output Pin
Section 13 Realtime Clock (RTC) 13.2 Input/Output Pin Table 13.1 shows the RTC pin configuration. Table 13.1 RTC Pin Configuration Abbreviation Description Connects crystal to RTC oscillator * RTC oscillator crystal pin EXTAL2 Connects crystal to RTC oscillator * RTC oscillator crystal pin XTAL2 Clock input/clock output TCLK...
Page 390: 64-Hz Counter (R64Cnt)
Section 13 Realtime Clock (RTC) • Month alarm register (RMONAR) • RTC control register 1 (RCR1) • RTC control register 2 (RCR2) 13.3.1 64-Hz Counter (R64CNT) The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the state of the RTC divider circuit between 64 Hz and 1 Hz.
Page 391: Second Counter (Rseccnt)
Section 13 Realtime Clock (RTC) 13.3.2 Second Counter (RSECCNT) The second counter (RSECCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded second section of the RTC. The count operation is performed by a carry for each second of the 64-Hz counter. The range of second can be set is 00 to 59 (decimal).
Page 392: Hour Counter (Rhrcnt)
Section 13 Realtime Clock (RTC) 13.3.4 Hour Counter (RHRCNT) The hour counter (RHRCNT) is an 8-bit read/write register used for setting/counting in the BCD- coded hour section of the RTC. The count operation is performed by a carry for each 1 hour of the minute counter.
Page 393: Date Counter (Rdaycnt)
Section 13 Realtime Clock (RTC) Bit Name Initial Value Description  7 to 3 All 0 Always read as 0.   2 to 0 Counter for the day of week in the BCD-code. The range can be set from 0 to 6 (decimal). Code Day of Week Sunday...
Page 394: Month Counter (Rmoncnt)
Section 13 Realtime Clock (RTC) 13.3.7 Month Counter (RMONCNT) The month counter (RMONCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded month section of the RTC. The count operation is performed by a carry for each month of the date counter. The range of month can be set is 00 to 12 (decimal).
Page 395: Second Alarm Register (Rsecar)
Section 13 Realtime Clock (RTC) 13.3.9 Second Alarm Register (RSECAR) The second alarm register (RSECAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded second section counter RSECCNT of the RTC. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated.
Page 396: Hour Alarm Register (Rhrar)
Section 13 Realtime Clock (RTC) Bit Name Initial Value Description Minute Alarm Enable 0: No compared 1: Compared   6 to 4 Setting value for 10-unit of minute alarm in the BCD-code. The range can be set from 0 to 5 (decimal). ...
Page 397: Day Of The Week Alarm Register (Rwkar)
Section 13 Realtime Clock (RTC) 13.3.12 Day of the Week Alarm Register (RWKAR) The day of the week alarm register (RWKAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded day of week section counter RWKCNT of the RTC. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed.
Page 398: Date Alarm Register (Rdayar)
Section 13 Realtime Clock (RTC) 13.3.13 Date Alarm Register (RDAYAR) The date alarm register (RDAYAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded date section counter RDAYCNT of the RTC. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among the registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated.
Page 399: Month Alarm Register (Rmonar)
Section 13 Realtime Clock (RTC) 13.3.14 Month Alarm Register (RMONAR) The month alarm register (RMONAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded month section counter RMONCNT of the RTC. When the ENB bit is set to 1, a comparison with the RMONCNT value is performed. From among the registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated.
Page 400: Rtc Control Register 1 (Rcr1)
Section 13 Realtime Clock (RTC) 13.3.15 RTC Control Register 1 (RCR1) RTC control register 1 (RCR1) affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. Because flags are sometimes set after an operand read, do not use this register in read-modify-write processing.
Page 401 Section 13 Realtime Clock (RTC) Bit Name Initial Value Description Alarm Interrupt Enable Flag When the alarm flag (AF) is set to 1, the AIE bit allows interrupts. 0: An alarm interrupt is not generated when the AF flag is set to 1 1: An alarm interrupt is generated when the AF flag is set to 1 2, 1...
Page 402: Rtc Control Register 2 (Rcr2)
Section 13 Realtime Clock (RTC) 13.3.16 RTC Control Register 2 (RCR2) The RTC control register 2 (RCR2) is an 8-bit read/write register for periodic interrupt control, 30- second adjustment ADJ, divider circuit RESET, and RTC count start/stop control. It is initialized to H'09 by a power-on reset.
Page 403 Section 13 Realtime Clock (RTC) Bit Name Initial Value Description 30 Second Adjustment When 1 is written to the ADJ bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. The divider circuit will be simultaneously reset.
Page 404: Rtc Operation
Section 13 Realtime Clock (RTC) 13.4 RTC Operation 13.4.1 Initial Settings of Registers after Power-On All the registers should be set after the power is turned on. 13.4.2 Setting the Time Figures 13.2(a) and 13.2(b) show how to set the time after stopping the clock. This procedure can be used to set the entire calendar and clock function.
Page 405: Figure 13.2(A) Setting The Time
Section 13 Realtime Clock (RTC) Confirm R64CNT is not 0 Stop clock Write 1 to RESET and Reset divider circuit 0 to START in the RCR2 register Set seconds, minutes, hour, day, day of the Order is irrelevant week, month and year Confirm R64CNT is 0 Start clock Write 1 to START in the RCR2 register...
Page 406: Reading The Time
Section 13 Realtime Clock (RTC) 13.4.3 Reading the Time Figure 13.3 shows how to read the time. If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 13.3 shows the method of reading the time without using interrupts;...
Page 407: Alarm Function
Section 13 Realtime Clock (RTC) 13.4.4 Alarm Function Figure 13.4 shows how to use the alarm function. Alarms can be generated using seconds, minutes, hours, day of the week, date, month, or any combination of these. Set the ENB bit (bit 7) in the register on which the alarm is placed to 1, and then set the alarm time in the lower bits.
Page 408: Crystal Oscillator Circuit
Section 13 Realtime Clock (RTC) 13.4.5 Crystal Oscillator Circuit Crystal oscillator circuit constants (recommended values) are shown in table 13.2, and the RTC crystal oscillator circuit in figure 13.5. Table 13.2 Recommended Oscillator Circuit Constants (Recommended Values) 32.768 kHz 10 to 22 pF 10 to 22 pF SH7706 EXTAL2...
Page 409: Usage Note
Section 13 Realtime Clock (RTC) 13.5 Usage Note 13.5.1 Register Writing during RTC Count The following RTC registers cannot be written to during an RTC count (while bit 0 = 1 in RCR2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCNT The RTC count must be halted before writing to any of the above registers.
Page 410: Timing For Setting Adj Bit In Rcr2
Section 13 Realtime Clock (RTC) 13.5.3 Timing for Setting ADJ Bit in RCR2 After the ADJ bit in RCR2 of the RTC is set to 1, it takes a maximum of approximately 91.6 µs (when a 32.768-kHz crystal resonator is connected to the EXTAL2 pin) for the setting to affect the value read from the second counter (RSECCNT).
Page 411: Section 14 Serial Communication Interface (Sci)
Section 14 Serial Communication Interface (SCI) Section 14 Serial Communication Interface (SCI) This LSI has an on-chip serial communication interface (SCI) that supports both asynchronous and clock synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. A block diagram of SCI is shown in figure 14.1, and the I/O ports are shown in figures 14.2 to 14.4.
Page 412: Figure 14.1 Sci Block Diagram
Section 14 Serial Communication Interface (SCI) • On-chip baud rate generator with selectable bit rates • Internal or external transmit/receive clock source From either baud rate generator (internal) or SCK0 pin (external) • Four types of interrupts Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently.
Page 413: Figure 14.2 Scpt[1]/Sck0 Pin
Section 14 Serial Communication Interface (SCI) Reset SCP1MD0 Internal data bus PCRW Reset SCP1MD1 PCRW Clock input enable Reset SCPT[1]/SCK0 SCP1DT1 PDRW Output enable Serial clock output PDRR * Serial clock input Legend: PDRW: SCPDR write PDRR: SCPDR read PCRW: SCPCR write Note: * When reading the SCK0 pin, clear the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR to 0, and set the SCP1MD1 bit in SCPCR to 1.
Page 414: Figure 14.3 Scpt[0]/Txd0 Pin
Section 14 Serial Communication Interface (SCI) Reset SCP0MD0 Internal data bus PCRW Reset SCP0MD1 PCRW Reset SCPT[0]/TxD0 SCP0DT1 PDRW Output enable Serial Legend: transmission PCRW: SCPCR write output PDRW: SCPDR write Figure 14.3 SCPT[0]/TxD0 Pin SCPT[0]/RxD0 Serial receive data Internal data bus PDRR * Legend: PDRR: PDR read...
Page 415: Input/Output Pin
Section 14 Serial Communication Interface (SCI) 14.2 Input/Output Pin The SCI has the serial pins summarized in table 14.1. Table 14.1 SCI Pins Pin Name Abbreviation Function Serial clock pin SCK0 Clock I/O Receive data pin RxD0 Input Receive data input Transmit data pin TxD0 Output...
Page 416: Receive Shift Register (Scrsr)
Section 14 Serial Communication Interface (SCI) 14.3.1 Receive Shift Register (SCRSR) The receive shift register (SCRSR) is an 8-bit register that receives serial data. Data input at the RxD pin is loaded into the SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form.
Page 417: Serial Mode Register (Scsmr)
Section 14 Serial Communication Interface (SCI) 14.3.5 Serial Mode Register (SCSMR) The serial mode register (SCSMR) is an eight-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write the SCSMR. Bit Name Initial Value Description...
Page 418 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description Parity Mode Selects even or odd parity when parity bits are added and checked. The O/E setting is available only when the PE is set to 1 to enable parity addition and check in asynchronous mode.
Page 419 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description Multiprocessor Mode Selects multiprocessor format. When multiprocessor format is selected, settings of the PE and O/E bits are ignored. The MP setting is used available in the asynchronous mode; it is ignored in the clock synchronous mode.
Page 420: Serial Control Register (Scscr)
Section 14 Serial Communication Interface (SCI) 14.3.6 Serial Control Register (SCSCR) The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock output in the asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write the SCSCR. Bit Name Initial Value Description...
Page 421 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description Transmit Enable Enables or disables the SCI serial transmitter. 0: Transmission disabled Note: The TDRE in SCSSR is fixed to 1. 1: Transmission enabled Note: Serial transmission starts when TDRE bit in SCSSR is cleared to 0 after writing of transmit data into the SCTDR.
Page 422 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description MPIE Multiprocessor Interrupt Enable Enables or disables multiprocessor interrupts. The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SCSMR) is set to 1 during reception.
Page 423 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description CKE1 Clock Enable 1 and 0 CKE0 These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input.
Page 424: Serial Status Register (Scssr)
Section 14 Serial Communication Interface (SCI) 14.3.7 Serial Status Register (SCSSR) The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating state. The CPU can always read and write the SCSSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER).
Page 425 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description R/(W) * Overrun Error ORER Indicates that data reception aborted due to an overrun error. 0: Receiving is in progress or has ended normally * [Clearing conditions] 1. The chip is reset or enters standby mode. 2.
Page 426 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description R/(W) * Framing Error Indicates that data reception aborted due to a framing error in the asynchronous mode. 0: Receiving is in progress or has ended normally [Clearing conditions] 1.
Page 427 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description R/(W) * Parity Error Indicates that data reception (with parity) aborted due to a parity error in the asynchronous mode. 0: Receiving is in progress or has ended normally [Clearing conditions] 1.
Page 428 Section 14 Serial Communication Interface (SCI) Bit Name Initial Value Description Multiprocessor Bit Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is a read-only bit and cannot be written. 0: Multiprocessor bit value in receive data is 0 If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous value.
Page 429: Sc Port Control Register (Scpcr)
Section 14 Serial Communication Interface (SCI) 14.3.8 SC Port Control Register (SCPCR) The SC port control register (SCPCR) controls the direction of I/O signals on the SCI and SCIF pins. SCPCR settings are used to perform I/O direction control, enabling data written in SCPDR to be output to the TxD0 pin, data read from the RxD0 pin to be input, and the breaking of serial transmission/reception.
Page 430: Sc Port Data Register (Scpdr)
Section 14 Serial Communication Interface (SCI) 14.3.9 SC Port Data Register (SCPDR) The SC port data register (SCPDR) controls data on the SCI and SCIF pins. The data controls on the SCI and SCIF pins are performed using bits 1 and 0, and bits 5 and 2 in SCPDR, respectively. Bit Name Initial Value Description...
Page 431: Bit Rate Register (Scbrr)
Section 14 Serial Communication Interface (SCI) 14.3.10 Bit Rate Register (SCBRR) The bit rate register (SCBRR) is an eight-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in SCSMR, determines the serial transmit/receive bit rate.
Page 432: Table 14.3 Bit Rates And Scbrr Settings In Asynchronous Mode
Section 14 Serial Communication Interface (SCI) Table 14.3 lists examples of SCBRR settings in the asynchronous mode; table 14.4 lists examples of SCBRR settings in the clock synchronous mode. Table 14.3 Bit Rates and SCBRR Settings in Asynchronous Mode Pφ φ φ φ (MHz) 7.3728 9.8304 Bit Rate (bits/s) n...
Page 433 Section 14 Serial Communication Interface (SCI) Pφ φ φ φ (MHz) 14.7456 19.6608 Bit Rate Error Error Error Error (bits/s) 0.70 0.03 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00 0.16 2400 0.00...
Page 434 Section 14 Serial Communication Interface (SCI) Pφ φ φ φ (MHz) 33.34 Bit Rate Error (bits/s) 0.00 –0.43 0.03 –0.43 1200 0.03 2400 –0.43 4800 0.03 9600 –0.43 19200 0.49 31250 1.03 38400 0.49 Rev. 5.00 May 29, 2006 page 386 of 698 REJ09B0146-0500...
Page 435: Table 14.4 Bit Rates And Scbrr Settings In Clock Synchronous Mode
Section 14 Serial Communication Interface (SCI) Table 14.4 Bit Rates and SCBRR Settings in Clock Synchronous Mode Pφ φ φ φ (MHz) 28.7 Bit Rate (bits/s) n — — — — — — — — — — — — 2.5k 100k 250k —...
Page 436: Table 14.5 Maximum Bit Rates For Various Frequencies With Baud Rate Generator
Section 14 Serial Communication Interface (SCI) Table 14.5 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is used. Tables 14.6 and 14.7 list the maximum rates for external clock input. Table 14.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ...
Page 437: Table 14.6 Maximum Bit Rates During External Clock Input (Asynchronous Mode)
Section 14 Serial Communication Interface (SCI) Table 14.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode) Pφ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2.0000 125000 9.8304 2.4576 153600 3.0000 187500 14.7456 3.6864 230400 4.0000 250000 19.6608...
Page 438: Operation
Section 14 Serial Communication Interface (SCI) 14.4 Operation For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous/clock synchronous mode and the transmission format are selected in SCSMR, as listed in table 14.8.
Page 439: Table 14.8 Serial Mode Register Settings And Sci Communication Formats
Section 14 Serial Communication Interface (SCI) Table 14.8 Serial Mode Register Settings and SCI Communication Formats SCSMR Settings SCI Communication Format Bit 7 Bit 6 Bit 5 Bit 2 Bit 3 Data Parity Multipro- Stop Bit C/A A A A Mode STOP Length...
Page 440: Operation In Asynchronous Mode
Section 14 Serial Communication Interface (SCI) 14.4.1 Operation in Asynchronous Mode In the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible.
Page 441: Table 14.10 Serial Communication Formats (Asynchronous Mode)
Section 14 Serial Communication Interface (SCI) Transmit/Receive Formats: Table 14.10 lists the 11 communication formats that can be selected in the asynchronous mode. The format is selected by settings in the SCSMR. Table 14.10 Serial Communication Formats (Asynchronous Mode) SCSMR Bits Serial Transmit/Receive Format and Frame Length CHR PE STOP 1...
Page 442: Figure 14.6 Output Clock And Serial Data Timing (Asynchronous Mode)
Section 14 Serial Communication Interface (SCI) Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK0 pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SCSMR and bits CKE1 and CKE0 in the SCSCR (table 14.9). When an external clock is input on the SCK0 pin, it must have a frequency equal to 16 times the desired bit rate.
Page 443: Figure 14.7 Sample Flowchart For Sci Initialization
Section 14 Serial Communication Interface (SCI) Transmitting and Receiving Data (SCI Initialization (Asynchronous Mode)): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below.
Page 444: Figure 14.8 Sample Flowchart For Transmitting Serial Data
Section 14 Serial Communication Interface (SCI) Transmitting Serial Data (Asynchronous Mode): Figure 14.8 shows a sample flowchart for transmitting serial data. Serial data transmission should be carried out in the following procedure after setting the SCI in a transmission-enabled state. Start transmission Read TDRE bit in SCSSR SCI status check and transmit data write:...
Page 445 Section 14 Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (SCTDR) contains new data, and loads this data from the SCTDR into the SCTSR.
Page 446: Figure 14.9 Sci Transmit Operation In Asynchronous Mode
Section 14 Serial Communication Interface (SCI) Start Parity Stop Parity Stop Start Data Data Serial Idling data (marking) TDRE TEND TXI interrupt Writes data to TXI interrupt TEI interrupt request SCTDR with the request request generated TXI interrupt generated generated processing routine and clear TDRE bit to 0...
Page 447: Figure 14.10 Sample Flowchart For Receiving Serial Data
Section 14 Serial Communication Interface (SCI) Receiving Serial Data (Asynchronous Mode): Figure 14.10 shows a sample flowchart for receiving serial data. Serial data reception should be carried out in the following procedure after setting the SCI in a reception-enabled state. Start reception Receive error processing and break Read ORER, PER, and FER...
Page 448 Section 14 Serial Communication Interface (SCI) Error processing ORER = 1? Overrun error processing FER = 1? Break? Framing error processing Clear RE bit in SCSCR to 0 PER = 1? Parity error processing Clear ORER, PER, and FER bits in SCSSR to 0 Figure 14.10 Sample Flowchart for Receiving Serial Data (cont) Rev.
Page 449: Table 14.11 Receive Error Conditions And Sci Operation
Section 14 Serial Communication Interface (SCI) In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is stored into the SCRSR in order from the LSB to the MSB. 3.
Page 450: Multiprocessor Communication
Section 14 Serial Communication Interface (SCI) Figure 14.11 shows an example of SCI receive operation in the asynchronous mode. Start Parity Stop Parity Stop Start Data Data Serial Idling data (marking) RDRF RXI interrupt request generated 1 frame Reads data with ERI interrupt the RXI interrupt request generated...
Page 451: Figure 14.12 Communication Among Processors Using Multiprocessor Format
Section 14 Serial Communication Interface (SCI) Figure 14.12 shows an example of communication among processors using the multiprocessor format. Transmitting station Serial communications circuit Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial...
Page 452: Figure 14.13 Sample Flowchart For Transmitting Multiprocessor Serial Data
Section 14 Serial Communication Interface (SCI) Transmitting Multiprocessor Serial Data: Figure 14.13 shows a sample flowchart for transmitting multiprocessor serial data. Transmission of multiprocessor serial data should be carried out in the following procedure after setting the SCI in a transmission-enabled state. Start transmission Read TDRE bit in SCSSR SCI status check and transmit...
Page 453 Section 14 Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes that the SCTDR contains new data, and loads this data from the SCTDR into the SCTSR. 2.
Page 454: Figure 14.14 Sci Multiprocessor Transmit Operation
Section 14 Serial Communication Interface (SCI) Multi- Multi- processor processor Start Stop Stop Start Data Data Serial Idling data (marking) TDRE TEND TXI interrupt Writes data to TXI interrupt TEI interrupt request TDR with the TXI request request generated interrupt pro- generated generated cessing routine and...
Page 455: Figure 14.15 Sample Flowchart For Receiving Multiprocessor Serial Data
Section 14 Serial Communication Interface (SCI) Receiving Multiprocessor Serial Data: Figure 14.15 shows a sample flowchart for receiving multiprocessor serial data. Reception of multiprocessor serial data should be carried out in the following procedure after setting the SCI in a reception-enabled state. Start reception Set MPIE bit in SCSCR to 1 Read ORER and FER...
Page 456 Section 14 Serial Communication Interface (SCI) Error processing ORER = 1? Overrun error processing FER = 1? Break? Framing error processing Clear RE bit in SCSCR to 0 Clear ORER and FER bits in SCSSR to 0 Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data (cont) Rev.
Page 457: Figure 14.16 Example Of Sci Receive Operation
Section 14 Serial Communication Interface (SCI) Figure 14.16 shows an example of SCI receive operation using a multiprocessor format. Data Data Start Stop Start Stop (ID1) (data 1) Serial Idling data (marking) MPIE RDRF value RXI interrupt request Reads RDR data with ID is not station's No RXI interrupt, (multiprocessor interrupt)
Page 458: Clock Synchronous Operation
Section 14 Serial Communication Interface (SCI) 14.4.3 Clock Synchronous Operation In the clock synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock.
Page 459: Figure 14.18 Sample Flowchart For Sci Initialization
Section 14 Serial Communication Interface (SCI) Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK0 pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SCSMR and bits CKE1 and CKE0 in the SCSCR. See table 14.9. When the SCI operates on an internal clock, it outputs the clock signal at the SCK0 pin.
Page 460: Figure 14.19 Sample Flowchart For Serial Transmitting
Section 14 Serial Communication Interface (SCI) Transmitting Serial Data (Clock Synchronous Mode): Figure 14.19 shows a sample flowchart for transmitting serial data. Transmission of serial data should be carried out in the following procedure after setting the SCI in a transmission-enabled state. Start transmission Read TDRE bit in SCSSR SCI status check and transmit data...
Page 461: Figure 14.20 Example Of Sci Transmit Operation
Section 14 Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes that the SCTDR contains new data and loads this data from the SCTDR into the SCTSR. 2.
Page 462: Figure 14.21 Sample Flowchart For Serial Data Receiving
Section 14 Serial Communication Interface (SCI) Receiving Serial Data (Clock Synchronous Mode): Figure 14.21 shows a sample flowchart for receiving serial data. Serial data reception should be carried out in the procedure described below after setting the SCI in a reception-enabled state. When switching from the asynchronous mode to the clock synchronous mode, make sure that ORER, PER, and FER are cleared to 0.
Page 463: Figure 14.22 Example Of Sci Receive Operation
Section 14 Serial Communication Interface (SCI) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is stored into the SCRSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from the SCRSR into the SCRDR.
Page 464: Figure 14.23 Sample Flowchart For Serial Data Transmitting/Receiving
Section 14 Serial Communication Interface (SCI) Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode): Figure 14.23 shows a sample flowchart for transmitting and receiving serial data simultaneously. Simultaneous transmission and reception of serial data should be carried out in the following procedure after setting the SCI in a transmission/reception-enabled state.
Page 465: Sci Interrupt Sources
Section 14 Serial Communication Interface (SCI) 14.5 SCI Interrupt Sources The SCI has four interrupt sources in each channel: Transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 14.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in SCSCR.
Page 466: Usage Note
Section 14 Serial Communication Interface (SCI) 14.6 Usage Note Note the following points when using the SCI. SCTDR Writing to and TDRE Flag: The TDRE bit in SCSSR is a status flag indicating loading of transmit data from the SCTDR into the SCTSR. The SCI sets TDRE to 1 when it transfers data from the SCTDR to the SCTSR.
Page 467: Figure 14.24 Receive Data Sampling Timing In Asynchronous Mode
Section 14 Serial Communication Interface (SCI) cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD0 pin. TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data.
Page 468 Section 14 Serial Communication Interface (SCI) The receive margin in the asynchronous mode can therefore be expressed as in equation 1. Equation 1: D – 0.5 (1 + F) × 100% M = 0.5 – – (L – 0.5)F – Where: M = Receive margin (%) N = Ratio of clock frequency to bit rate (N = 16) D = Clock duty cycle (D = 0 to 1.0)
Page 469: Section 15 Smart Card Interface
Section 15 Smart Card Interface Section 15 Smart Card Interface As an added serial communications interface function, the SCI supports an IC card (smart card) interface that conforms to the data transfer protocol (asynchronous half-duplex character transmission protocol) of the ISO/IEC standard 7816-3 for identification of cards. Register settings are used to switch between the ordinary serial communication interface and the smart card interface.
Page 470: Figure 15.1 Smart Card Interface Block Diagram
Section 15 Smart Card Interface Internal Module data bus data bus SCBRR SCRDR SCTDR SCSCMR SCSSR SCSCR SCSMR Baud rate Pφ generator Pφ/4 RxD0 SCRSR SCTSR Transmit/ receive Pφ/16 control Pφ/64 TxD0 Clock Parity generation Parity check External clock SCK0 Legend: SCSCMR: Smart card mode register...
Page 471: Input/Output Pin
Section 15 Smart Card Interface 15.2 Input/Output Pin Table 15.1 summarizes the smart card interface pins. Table 15.1 Pin Configuration Pin Name Abbreviation I/O Function Serial clock pin SCK0 Output Clock output Receive data pin RxD0 Input Receive data input Transmit data pin TxD0 Output...
Page 472: Smart Card Mode Register (Scscmr)
Section 15 Smart Card Interface 15.3.1 Smart Card Mode Register (SCSCMR) The smart card mode register (SCSCMR) is an 8-bit read/write register that selects smart card interface functions. Bit Name Initial Value Description 7 to 4 — — Reserved An undefined value are read from these bits. SDIR Smart Card Data Transfer Direction Selects the serial/parallel conversion format.
Page 473: Serial Status Register (Scssr)
Section 15 Smart Card Interface 15.3.2 Serial Status Register (SCSSR) In the smart card interface mode, the function of bit 4 in SCSSR of the SCI is changed as shown blow. Relating to this, the setting conditions for bit 2, the TEND bit, are also changed. Bit Name Initial Value Description...
Page 474 Section 15 Smart Card Interface Bit Name Initial Value Description R/(W) * Parity error TEND Transmission end Multiprocessor bit MPBT Multiprocessor bit transfer These bits have the same function as in the ordinary SCI. See section 14, Serial Communication Interface (SCI), for more information.
Page 475: Operation
Section 15 Smart Card Interface 15.4 Operation 15.4.1 Overview The primary functions of the smart card interface are described below. 1. Each frame consists of 8-bit data and a parity bit. 2. During transmission, the card leaves a guard time of at least 2 etu (elementary time units: the period for 1 bit to transfer) from the end of the parity bit to the start of the next frame.
Page 476: Data Format
Section 15 Smart Card Interface TxD0 Data line RxD0 SCK0 Clock line Px (port) Reset line IC card Connected device Figure 15.2 Pin Connection Diagram for the Smart Card Interface 15.4.3 Data Format Figure 15.3 shows the data format for the smart card interface. In this mode, parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re-transmitted.
Page 477: Register Settings
Section 15 Smart Card Interface The operating sequence is: 1. The data line is high impedance when not in use and is fixed high with a pull-up resistor. 2. The transmitting side starts one frame of data transmission. The data frame starts with a start bit (Ds, low level).
Page 478: Figure 15.4 Waveform Of Start Character
Section 15 Smart Card Interface 2. Setting the bit rate register (SCBRR): Set the bit rate. See section 15.4.5, Clock, to see how to calculate the set value. 3. Setting the serial control register (SCSCR): The TIE, RIE, TE and RE bits function as they do for the ordinary SCI.
Page 479: Clock
Section 15 Smart Card Interface 15.4.5 Clock Only the internal clock generated by the on-chip baud rate generator can be used as the communication clock in the smart card interface. The bit rate for the clock is set by the SCBRR and the CKS1 and CKS0 bits in the SCSMR, and is calculated using the equation below.
Page 480: Table 15.5 Examples Of Scbrr Settings For Bit Rate B (Bit/S) (N = 0)
Section 15 Smart Card Interface Table 15.5 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = = = = 0) φ φ φ φ (MHz) (9600 Bits/s) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 Error Error Error Error Error Error Error...
Page 481: Data Transmission And Reception
Section 15 Smart Card Interface Table 15.7 Register Set Values and SCKφ φ φ φ Pin Register Value SCK Pin C/A A A A Setting SMIF CKE1 CKE0 Output State Port Determined by setting of port register SCP1MD1 and SCP1MD0 bits SCK0 (serial clock) output state Low output Low output state...
Page 482: Figure 15.5 Initialization Flowchart (Example)
Section 15 Smart Card Interface Initialize Clear TE and RE bits in SCSCR to 0 Clear SCSSR's FER/ERS, PER and ORER flags to 0 Set SCSMR's O/E bit to parity, set CKS1 and CKS0 bits to the clock and set C/A Set SCSMR's SMIF, SDIR, and SINV bits Set value in SCBRR...
Page 483: Figure 15.6 Transmission Flowchart
Section 15 Smart Card Interface This processing can be interrupted. When the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) will be requested when the TEND flag is set to 1 at the end of the transmission.
Page 484: Figure 15.7 Reception Flowchart (Example)
Section 15 Smart Card Interface 1. Initialize the smart card interface mode as described above in Initialization and in figure 15.5. 2. Check that the ORER and PER flags in SCSSR are cleared to 0. If either flag is set, clear both to 0 after performing the appropriate error processing procedures.
Page 485: Usage Note
Section 15 Smart Card Interface Switching Modes: When switching from receive mode to transmit mode, check that the receive operation is completed before starting initialization and setting RE to 0 and TE to 1. The RDRF, PER, and ORER flags can be used to check if reception is completed. When switching from transmit mode to receive mode, check that the transmit operation is completed before starting initialization and setting TE to 0 and RE to 1.
Page 486: Figure 15.8 Receive Data Sampling Timing In Smart Card Mode
Section 15 Smart Card Interface 372 clock cycles 186 clock cycles 371 0 371 0 Base clock Start Receive data (RxD) Synchronization sampling timing Data sampling timing Figure 15.8 Receive Data Sampling Timing in Smart Card Mode The receive margin is found from the following equation: For smart card mode: D –...
Page 487: Figure 15.9 Retransmission In Sci Receive Mode
Section 15 Smart Card Interface Retransmission (Receive and Transmit Modes): Retransmission by the SCI in Receive Mode: Figure 15.9 shows the retransmission operation in the SCI receive mode. 1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is automatically set to 1.
Page 488: Figure 15.10 Retransmission In Sci Transmit Mode
Section 15 Smart Card Interface Retransmission by the SCI in Transmit Mode: Figure 15.10 shows the retransmission operation in the SCI transmit mode. 1. After transmission of one frame is completed, the FER/ERS bit in SCSSR is set to 1 when a error signal is returned from the receiving side.
Page 489: Section 16 Serial Communication Interface With Fifo (Scif)
Section 16 Serial Communication Interface with FIFO (SCIF) Section 16 Serial Communication Interface with FIFO (SCIF) This LSI has single-channel serial communication interface with FIFO (SCIF) that supports asynchronous serial communication. It also has 16-stage FIFO registers for both transfer and receive that enables this LSI efficient high-speed continuous communication.
Page 490: Figure 16.1 Scif Block Diagram
Section 16 Serial Communication Interface with FIFO (SCIF) • The quantity of data in the transmit and receive FIFO registers and the number of receive errors of the receive data in the receive FIFO register can be known. • The time-out error (DR) can be detected in receiving. Internal Module data bus data bus...
Page 491: Figure 16.2 Scpt[3]/Sck2 Pin
Section 16 Serial Communication Interface with FIFO (SCIF) Reset SCP3MD0 Internal data bus PCRW Reset SCP3MD1 SCIF PCRW Clock input enable Reset SCPT[3]/SCK2 SCP3DT1 PDRW Output enable Serial clock output PDRR * Serial clock input Legend: PDRW: SCPDR write PDRR: SCPDR read PCRW: SCPCR write Note: * When reading the SCK2 pin, clear the CKE1 and CKE0 bits in SCSCR to 0, and set the SCP3MD1 bit in SCSPR to 1.
Page 492: Figure 16.3 Scpt[2]/Txd2 Pin
Section 16 Serial Communication Interface with FIFO (SCIF) Reset SCP2MD0 Internal data bus PCRW Reset SCP2MD1 PCRW Reset SCPT[2]/TxD2 SCP2DT1 SCIF PDRW Output enable Serial transmission Legend: output PCRW: SCPCR write PDRW: SCPDR write Figure 16.3 SCPT[2]/TxD2 Pin SCIF SCPT[2]/RxD2 Serial receive data...
Page 493: Input/Output Pin
Section 16 Serial Communication Interface with FIFO (SCIF) 16.2 Input/Output Pin The SCIF has the I/O pins summarized in table 16.1. Table 16.1 SCIF Pins Pin Name Abbreviation Function Serial clock pin SCK2 Clock I/O Receive data pin RxD2 Input Receive data input Transmit data pin TxD2...
Page 494: Receive Shift Register 2 (Scrsr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.1 Receive Shift Register 2 (SCRSR2) The receive shift register 2 (SCRSR2) is an eight-bit register taht receives serial data. The CPU cannot read from or write to the SCRSR2 directly. Data input at the RxD pin is loaded into the SCRSR2 in the order received, LSB (bit 0) first, converting the data to parallel form.
Page 495: Serial Mode Register 2 (Scsmr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.5 Serial Mode Register 2 (SCSMR2) The serial mode register2 (SCSMR2) is an eight-bit register that specifies the SCIF serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write the SCSMR2.
Page 496 Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description Parity Mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only when the PE is set to 1 to enable parity addition and check. The O/E setting is ignored when parity addition and check is disabled.
Page 497: Serial Control Register 2 (Scscr2)
Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description CKS1 Clock Select 1 and 0 CKS0 These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16 and Pφ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 16.3.8, Bit Rate Register 2 (SCBRR2).
Page 498 Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description Receive Interrupt Enable Enables or disables the receive-data-full (RXI) and receive- error (ERI) interrupts requested when the serial receive data is transferred from the SCRSR2 to SCFRDR2, when the quantity of data in the SCFRDR2 becomes more than the specified number of receive triggers, and when the RDRF flag of SCSSR2 is set to1.
Page 499 Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description 3, 2 — All 0 Reserved These bits are always read as 0. The write value should always be 0. CKE1 Clock Enable CKE0 These bits select the SCIF clock source and enable or disable clock output from the SCK2 pin.
Page 500: Serial Status Register 2 (Scssr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.7 Serial Status Register 2 (SCSSR2) The serial status register 2 (SCSSR2) is a 16-bit register. The upper 8 bits indicate the number of receive errors in the data of the SCFRDR2, and the lower 8 bits indicate SCIF operating state. The CPU can always read and write the SCSSR2, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, OPER, and DR).
Page 501 Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description R/(W) * Receive error Indicates that a framing error or a parity error, when receiving data containing parity bits, has occurred. 0: Receive is in progress, or receive is normally completed.
Page 502 Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description R/(W) * Transmit End TEND Indicates that when the last bit of a serial character was transmitted, the SCFTDR2 did not contain valid data, so transmission has ended. 0: Transmission is in progress.
Page 503 Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description R/(W) * Transmit FIFO Data Empty TDFE Indicates that data is transferred from SCFTDR2 to SCTSR2, the quantity of data in SCFTDR2 becomes less than the number of transmission triggers specified by the TTRG1 and TTRG0 bits in SCFCR2, and writing the transmit data to SCFTDR is enabled.
Page 504 Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description R/(W) * Break Detection Indicates that a break signal is detected in received data. 0: No break signal is being received. [Clearing conditions] 1. The chip is power-on reset or enters standby mode. 2.
Page 505 Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description Parity Error Indicates a parity error in the data read from the SCFRDR2. 0: No parity error occurred in the data read from SCFRDR2. [Clearing conditions] 1. The chip is power-on reset or enters standby mode. 2.
Page 506 Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description R/(W) * Receive FIFO Data Full Indicates that received data is transferred to the SCFRDR2, the quantity of data in SCFRDR becomes more than the number of receive triggers specified by the RTRG1 and RTRG0 bits in SCFCR2.
Page 507 Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description R/(W) * Receive Data Ready Indicates that the SCFRDR2 stores the data which is less than the specified number of receive triggers, and that next data is not yet received after 15 etu has elapsed from the last stop bit.
Page 508: Bit Rate Register 2 (Scbrr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.8 Bit Rate Register 2 (SCBRR2) The bit rate register 2 (SCBRR2) is an eight-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the SCSMR2, determines the serial transmit/receive bit rate.
Page 509: Table 16.3 Bit Rates And Scbrr2 Settings
Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.3 lists examples of SCBRR2 settings. Table 16.3 Bit Rates and SCBRR2 Settings Pφ φ φ φ (MHz) 7.3728 9.8304 Error (% % % % ) n Error (% % % % ) n Error (% % % % ) Bit Rate (bit/s) –0.07...
Page 510 Section 16 Serial Communication Interface with FIFO (SCIF) Pφ φ φ φ (MHz) 14.7456 19.6608 Bit Rate Error Error Error Error (% % % % ) (% % % % ) (% % % % ) (% % % % ) (bit/s) 0.70 0.03...
Page 511 Section 16 Serial Communication Interface with FIFO (SCIF) Pφ φ φ φ (MHz) 24.576 28.7 Bit Rate Error Error Error Error (% % % % ) (% % % % ) (% % % % ) (% % % % ) (bit/s) –0.44 3 0.08...
Page 512 Section 16 Serial Communication Interface with FIFO (SCIF) Pφ φ φ φ (MHz) 33.34 Bit Rate Error (% % % % ) (bit/s) 0.00 –0.43 0.03 –0.43 1200 0.03 2400 –0.43 4800 0.03 9600 –0.43 19200 0.49 31250 1.03 38400 0.49 11520 0.49...
Page 513: Table 16.4 Maximum Bit Rates For Various Frequencies With Baud Rate Generator
Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.4 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ φ φ φ (MHz) Maximum Bit Rate (bit/s) 250000 9.8304 307200 375000 14.7456 460800 500000 19.6608 614400 625000 750000...
Page 514: Fifo Control Register 2 (Scfcr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.9 FIFO Control Register 2 (SCFCR2) The FIFO control register 2 (SCFCR2) resets the number of data in the SCFTDR2 and SCFRDR2, sets the number of trigger data, and contains an enable bit for the loop back test. The SCFCR2 is always read and written by the CPU.
Page 515 Section 16 Serial Communication Interface with FIFO (SCIF) Initial Bit Name Value Description TFRST Transmit FIFO Data Register Reset Cancels the transmit data in the SCFTDR2 and resets the data to the empty state. 0: Disables reset operation * 1: Enables reset operation Note: * The reset is executed in a hardware reset or the standby mode.
Page 516: Fifo Data Count Set Register 2 (Scfdr2)
Section 16 Serial Communication Interface with FIFO (SCIF) 16.3.10 FIFO Data Count Set Register 2 (SCFDR2) The SCFDR2 is a 16-bit register which indicates the number of data stored in the SCFTDR2 and SCFRDR2. The SCFDR2 is always read from the CPU. The upper eight bits of this register indicate the number of transmit data items stored in the SCFTDR2 that have not yet been transmitted.
Page 517: Operation
Section 16 Serial Communication Interface with FIFO (SCIF) 16.4 Operation For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually. Refer to section 14.4.1, Operation in Asynchronous Mode (SCI). The SCIF has the 16-byte FIFO buffer for both transmit and receive, reduces an overhead of the CPU, and enables continuous high-speed communication.
Page 518: Serial Operation
Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.7 SCSCR2 and SCSCR2 Settings and SCIF Clock Source Selection SCSCR2 Settings SCIF Transmit/Receive Clock Bit 1 Bit 0 Clock Mode CKE1 CKE0 Source SCK2 Pin Function Asynchronous Internal SCIF does not use the SCK2 pin mode Outputs a clock with a frequency 16 times the bit rate...
Page 519 Section 16 Serial Communication Interface with FIFO (SCIF) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK2 pin can be selected as the SCIF transmit/receive clock. The clock source is selected by bits CKE1 and CKE0 in the serial control register (SCSCR2) (table 16.7).
Page 520: Figure 16.5 Sample Scif Initialization Flowchart
Section 16 Serial Communication Interface with FIFO (SCIF) Initialization 1. Set the clock selection in SCSCR2. Be sure to clear bits RIE TIE, TE, and RE to 0. Clear TE and RE bits in SCSCR2 to 0 When clock output is selected, it is output immediately after SCSCR2 settings are made.
Page 521: Figure 16.6 Sample Serial Transmission Flowchart
Section 16 Serial Communication Interface with FIFO (SCIF) Serial data transmission: Figure 16.6 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start transmission 1. SCIF status check and transmit data write: Read SCSSR2 and check that the TDFE flag is set to 1, then write transmit data to Read TDFE bit in SCSSR2...
Page 522 Section 16 Serial Communication Interface with FIFO (SCIF) In serial transmission, the SCIF operates as described below. 1. When data is written into the SCFTDR2, the SCIF transfers the data from SCFTDR2 to the transmit shift register (SCTSR2) and starts transmitting. Confirm that the TDFE flag in SCSSR2 is set to 1 before writing transmit data to SCFTDR2.
Page 523: Figure 16.7 Example Of Transmit Operation (Example With 8-Bit Data, Parity, One Stop Bit)
Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.7 shows an example of the operation for transmission. Start Parity Stop Parity Stop Start Data Data Serial Idling data (marking) TDFE TEND TXI interrupt Data written to TXI interrupt request SCFTDR2 and TDFE request flag read as 1 then...
Page 524: Figure 16.9 Sample Serial Reception Flowchart (1)
Section 16 Serial Communication Interface with FIFO (SCIF) Serial data reception: Figure 16.9 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. 1. Receive error handling and break detection: Start reception Read the DR, ER, and BRK flags in SCSSR2 to identify any error, perform the appropriate...
Page 525: Figure 16.10 Sample Serial Reception Flowchart (2)
Section 16 Serial Communication Interface with FIFO (SCIF) 1. Whether a framing error or parity error has Error processing occurred in the receive data read from SCFRDR2 can be ascertained from the FER and PER bits in SCSSR2. ER = 1? 2.
Page 526 Section 16 Serial Communication Interface with FIFO (SCIF) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR2 in LSB-to-MSB order. 3.
Page 527: Figure 16.11 Example Of Scif Receive Operation (Example With 8-Bit Data, Parity, One Stop Bit)
Section 16 Serial Communication Interface with FIFO (SCIF) Start Parity Stop Parity Stop Start Data Data Serial Idling data (marking) RXI interrupt request One frame Data read and RDF ERI interrupt flag read as 1 then request generated cleared to 0 by by receive error RXI interrupt handler Figure 16.11 Example of SCIF Receive Operation...
Page 528: Scif Interrupts
Section 16 Serial Communication Interface with FIFO (SCIF) 16.4.2 SCIF Interrupts The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive-data-full (RXI), and break (BRI). Table 16.9 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE and RIE bits in SCSCR2.
Page 529: Usage Notes
Section 16 Serial Communication Interface with FIFO (SCIF) 16.5 Usage Notes Note the following when using the SCIF. SCFTDR2 Writing and the TDFE Flag The TDFE flag in SCSSR2 is set when the number of transmit data bytes written in the SCFTDR2 has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the SCFCR2.
Page 530: Figure 16.13 Receive Data Sampling Timing In Asynchronous Mode
Section 16 Serial Communication Interface with FIFO (SCIF) TEND Flag and TE Bit Processing The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally.
Page 531 Section 16 Serial Communication Interface with FIFO (SCIF) From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: M = (0.5 – 1/(2 × 16)) × 100% = 46.875% This is a theoretical value.
Page 532 Section 16 Serial Communication Interface with FIFO (SCIF) Rev. 5.00 May 29, 2006 page 484 of 698 REJ09B0146-0500...
Page 533: Section 17 Pin Function Controller (Pfc)
Section 17 Pin Function Controller (PFC) Section 17 Pin Function Controller (PFC) The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. The pin function and I/O direction can be selected for each pin individually without regard to the operating mode of the LSI.
Page 534 Section 17 Pin Function Controller (PFC) Port Function Other Function Port (Related Module) (Related Module) CS6 output (BSC) / CE1B output (BSC) PTC7 I/O (port) CS5 output 9BSC) / CE1A output (BSC) PTC6 I/O (port) CS4 output (BSC) PTC5 I/O (port) CS3 output (BSC) PTC4 I/O (port) CS2 output (BSC)
Page 535 Section 17 Pin Function Controller (PFC) Port Function Other Function Port (Related Module) (Related Module) ASEBRKAK output (AUD) PTF6 I/O (port) PTF5 I/O (port) TDO output (H-UDI) PTF4 I/O (port) AUDSYNC output (AUD) PTF3 I/O (port) AUDATA[3] I/O (AUD) PTF2 I/O (port) AUDATA[2] I/O (AUD) PTF1 input (port) AUDATA[1] I/O (AUD)
Page 536: Register Description
Section 17 Pin Function Controller (PFC) Port Function Other Function Port (Related Module) (Related Module) CTS2 input (SCIF)/ IRQ5 input (INTC) SCPT SCPT5 input (port) RTS2 output (SCIF) SCPT SCPT4 I/O (port) SCPT SCPT3 I/O (port) SCK2 I/O (SCIF) SCPT SCPT2 input (port) RxD2 input (SCIF) SCPT2 output (port)
Page 537: Port A Control Register (Pacr)
Section 17 Pin Function Controller (PFC) 17.1.1 Port A Control Register (PACR) Port A Control Register (PACR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. Bit Name Initial Value Description PA7MD1 PA7 Mode PA7MD0 00: Other function (See table 17.1) 01: Port output...
Page 538: Port B Control Register (Pbcr)
Section 17 Pin Function Controller (PFC) Bit Name Initial Value Description PA2MD1 PA2 Mode PA2MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) PA1MD1 PA1 Mode PA1MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on)
Page 539 Section 17 Pin Function Controller (PFC) Bit Name Initial Value Description PB5MD1 PB5 Mode PB5MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) PB4MD1 PB4 Mode PB4MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on)
Page 540: Port C Control Register (Pccr)
Section 17 Pin Function Controller (PFC) 17.1.3 Port C Control Register (PCCR) Port C Control Register (PCCR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. Bit Name Initial Value Description PC7MD1 PC7 Mode PC7MD0 00: Other function (See table 17.1) 01: Port output...
Page 541: Port D Control Register (Pdcr)
Section 17 Pin Function Controller (PFC) Bit Name Initial Value Description PC2MD1 PC2 Mode PC2MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) PC1MD1 PC1 Mode PC1MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on)
Page 542 Section 17 Pin Function Controller (PFC) Bit Name Initial Value Description PD5MD1 PD5 Mode PD5MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) PD4MD1 PD4 Mode PD4MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on)
Page 543: Port E Control Register (Pecr)
Section 17 Pin Function Controller (PFC) 17.1.5 Port E Control Register (PECR) Port E Control Register (PECR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. Bit Name Initial Value Description PE7MD1 PE7 Mode PE7MD0 00: Other function (See table 17.1) 01: Port output...
Page 544 Section 17 Pin Function Controller (PFC) Bit Name Initial Value Description PE2MD1 PE2 Mode PE2MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) PE1MD1 PE1 Mode PE1MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on)
Page 545: Port F Control Register (Pfcr)
Section 17 Pin Function Controller (PFC) 17.1.6 Port F Control Register (PFCR) Port F Control Register (PFCR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. PFCR is initialized to H'AAAA (in case of ASEMD0 = 1) or H'0000 (in case of ASEMD0 = 0) by power-on resets;...
Page 546 Section 17 Pin Function Controller (PFC) Bit Name Initial Value Description PF3MD1 PF3 Mode PF3MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) PF2MD1 PF2 Mode PF2MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on)
Page 547: Port G Control Register
Section 17 Pin Function Controller (PFC) 17.1.7 Port G Control Register (PGCR) Port G Control Register (PGCR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. PGCR is initialized to H'AAAA (in case of ASEMD0 = 1) or H'A800 (in case of ASEMD0 = 0) by power-on resets;...
Page 548: Port H Control Register (Phcr)
Section 17 Pin Function Controller (PFC) Bit Name Initial Value Description PG1MD1 PG1 Mode PG1MD0 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) PG0MD1 PG0 Mode PG0MD0 00: Other function (See table 17.1) 01: Reserved (Setting prohibited)
Page 549 Section 17 Pin Function Controller (PFC) Bit Name Initial Value Description PH4MD1 PH4 Mode PH4MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) PH3MD1 PH3 Mode PH3MD0 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on)
Page 550: Port J Control Register (Pjcr)
Section 17 Pin Function Controller (PFC) 17.1.9 Port J Control Register (PJCR) Port J Control Register (PJCR) is a 16-bit read/write register that selects the pin functions. When D/A output is enabled, port input settings should not be made in PJCR. When selecting port input, confirm that D/A output is disabled in DACR before making port input settings in PJCR.
Page 551: Sc Port Control Register (Scpcr)
Section 17 Pin Function Controller (PFC) 17.1.10 SC Port Control Register (SCPCR) SC Port Control Register (SCPCR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. The setting of SCPCR is valid only when the transmit/receive operation is disabled in the setting of the SCSCR register.
Page 552 Section 17 Pin Function Controller (PFC) Bit Name Initial Value Description SCP2MD1 SCP2 Mode SCP2MD0 00: Transmit data output 1 (TxD2) Receive data input 1 (RxD2) 01: General output (SCPT[2] output pin) Receive data input 1 (RxD2) 10: SCPT[2] input pin pull-up (input pin) Transmit data output 1 (TxD2) 11: General input (SCPT[2] input pin) Transmit data output 1 (TxD2)
Page 553 Section 17 Pin Function Controller (PFC) Bit Name Initial Value Description SCP0MD1 SCP0 Mode SCP0MD0 00: Transmit data output 0 (TxD0) Receive data input 0 (RxD0) 01: General output (SCPT[0] output pin) Receive data input 0 (RxD0) 10: SCPT[0] input pin pull-up (input pin) Transmit data output 0 (TxD0) 11: General input (SCPT[0] input pin) Transmit data output 0 (TxD0)
Page 554 Section 17 Pin Function Controller (PFC) Rev. 5.00 May 29, 2006 page 506 of 698 REJ09B0146-0500...
Page 555: Section 18 I/O Ports
Section 18 I/O Ports Section 18 I/O Ports This LSI has 10 ports (ports A to J and SC). All port pins are multiplexed with other pin functions (Pin Function Controller (PFC) maintains the selection of the pin functions and pull-up MOS control).
Page 556: Port A Data Register (Padr)
Section 18 I/O Ports 18.1.2 Port A Data Register (PADR) Port A data Register (PADR) is an 8-bit read/write register that stores data for pins PTA7 to PTA0. PA7DT to PA0DT bit corresponds to PTA7 to PTA0 pin. When the pin function is general output port, if the port is read the value of the corresponding PADR bit is returned directly.
Page 557: Port B
Section 18 I/O Ports 18.2 Port B Port B is an 8-bit I/O port with the pin configuration shown in figure 18.2. Each pin has an input pull-up MOS, which is controlled by Port B Control Register (PBCR) in PFC. PTB7 (I/O) / D31 (I/O) PTB6 (I/O) / D30 (I/O) PTB5 (I/O) / D29 (I/O)
Page 558: Port B Data Register (Pbdr)
Section 18 I/O Ports 18.2.2 Port B Data Register (PBDR) Port B data register (PBDR) is an 8-bit read/write register that stores data for pins PTB7 to PTB0. PB7DT to PB0DT bit corresponds to PTB7 to PTB0 pin. When the pin function is general output port, if the port is read the value of the corresponding PBDR bit is returned directly.
Page 559: Port C
Section 18 I/O Ports 18.3 Port C Port C is an 8-bit I/O port with the pin configuration shown in figure 18.3. Each pin has an input pull-up MOS, which is controlled by Port C Control Register (PCCR) in PFC. PTC7 (I/O) / CS6 (output) / CE1B (output) PTC6 (I/O) / CS5 (output) / CE1A (output) PTC5 (I/O) / CS4 (output)
Page 560: Port C Data Register (Pcdr)
Section 18 I/O Ports 18.3.2 Port C Data Register (PCDR) Port C data register (PCDR) is an 8-bit read/write register that stores data for pins PTC7 to PTC0. PC7DT to PC0DT bit corresponds to PTC7 to PTC0 pin. When the pin function is general output port, if the port is read, the value of the corresponding PCDR bit is returned directly.
Page 561: Port D
Section 18 I/O Ports 18.4 Port D Port D is an 8-bit I/O port with the pin configuration shown in figure 18.4. Each pin has an input pull-up MOS, which is controlled by Port D Control Register (PDCR) in PFC. PTD7 (I/O) / CE2B (output) PTD6 (I/O) / CE2A (output) PTD5 (I/O) / IOIS16 (input)
Page 562: Port D Data Register (Pddr)
Section 18 I/O Ports 18.4.2 Port D Data Register (PDDR) Port D data register (PDDR) is an 8-bit read/write register that stores data for pins PTD7 to PTD0. PD7DT to PD0DT bit corresponds to PTD7 to PTD0 pin. When the pin function is general output port, if the port is read, the value of the corresponding PDDR bit is returned directly.
Page 563: Port E
Section 18 I/O Ports 18.5 Port E Port E is an 8-bit I/O port with the pin configuration shown in figure 18.5. Each pin has an input pull-up MOS, which is controlled by Port E Control Register (PECR) in PFC. PTE7 (I/O) / IRQOUT (output) PTE6 (I/O) / TCLK (I/O) PTE5 (I/O) / STATUS1 (output)
Page 564: Port E Data Register (Pedr)
Section 18 I/O Ports 18.5.2 Port E Data Register (PEDR) Port E data register (PEDR) is an 8-bit read/write register that stores data for pins PTE7 to PTE0. PE7DT to PE0DT bit corresponds to PTE7 to PTE0 pin. When the pin function is general output port, if the port is read the value of the corresponding PEDR bit is returned directly.
Page 565: Port F
Section 18 I/O Ports 18.6 Port F Port F is a 7-bit input/output port with the pin configuration shown in figure 18.6. Each pin has an input pull-up MOS, which is controlled by Port F Control Register (PFCR) in PFC. PTF6 (I/O) / ASEBRKAK (output) PTF5 (I/O) / TDO (output) PTF4 (I/O) / AUDSYNC (output)
Page 566: Port F Data Register (Pfdr)
Section 18 I/O Ports 18.6.2 Port F Data Register (PFDR) Port F data register (PFDR) is an 8-bit register composed of a 1-bit readable register and a 7-bit readable/writable register. This register stores data for pins PTF6 to PTF0. PF6DT to PF0DT bit corresponds to PTF6 to PTF0 pin.
Page 567: Port G
Section 18 I/O Ports 18.7 Port G Port G is a 6-bit input port with the pin configuration shown in figure 18.7. Each pin has an input pull-up MOS, which is controlled by Port G Control Register (PGCR) in PFC. PTG5 (input) / ADTRG (input) PTG4 (input) / AUDCK (input) PTG3 (input) / TRST (input)
Page 568: Port G Data Register
Section 18 I/O Ports 18.7.2 Port G Data Register (PGDR) Port G data register (PGDR) is an 8-bit read register that stores data for pins PTG5 to PTG0. PG5DT to PG0DT bit corresponds to PTG5 to PTG0 pin. When the function is general input port, if the port is read the corresponding pin level is read.
Page 569: Port H
Section 18 I/O Ports 18.8 Port H Port H is a 7-bit I/O and port with the pin configuration shown in figure 18.8. Each pin has an input pull-up MOS, which is controlled by Port H Control Register (PHCR) in PFC. PTH6 (I/O) / DREQ1 (input) PTH5 (I/O) / DREQ0 (input) PTH4 (I/O) / IRQ4 (input)
Page 570: Port H Data Register (Phdr)
Section 18 I/O Ports 18.8.2 Port H Data Register (PHDR) Port H data register (PHDR) is a 7-bit read/write and 1-bit read register that stores data for pins PTH6 to PTH0. PH6DT to PH0DT bit corresponds to PTH6 to PTH0 pin. When the pin function is general output port, if the port is read, the value of the corresponding PHDR bit is returned directly.
Page 571: Port J
Section 18 I/O Ports 18.9 Port J Port J is a 4-bit input port with the pin configuration shown in figure 18.9. PTJ3 (input) / AN3 (input) / DA0 (output) PTJ2 (input) / AN2 (input) / DA1 (output) Port J PTJ1 (input) / AN1 (input) PTJ0 (input) / AN0 (input) Figure 18.9 Port J...
Page 572: Port J Data Register (Pjdr)
Section 18 I/O Ports 18.9.2 Port J Data Register (PJDR) Port J data register (PJDR) is an 8-bit read register that stores data for pins PTJ7 to PTJ0. PJ3DT to PJ0DT bit corresponds to PTJ3 to PTJ0 pin. When the pin function is general output port, if the port is read the value of the corresponding PJDR bit is returned directly.
Page 573: Sc Port
Section 18 I/O Ports 18.10 SC Port SC port is a 3-bit I/O, 2-bit output and 4-bit input port with the pin configuration shown in figure 18.10. Each pin has an input pull-up MOS, which is controlled by SC port Control Register (SCPCR) in PFC.
Page 574: Sc Port Data Register (Scpdr)
Section 18 I/O Ports 18.10.2 SC Port Data Register (SCPDR) SC Port data register (SCPDR) is a 5-bit read/write and 3-bit read register that stores data for pins SCPT5 to SCPT0. SCP5DT to SCP0DT bit corresponds to SCPT5 to SCPT0 pin. When the pin function is general output port, if the port is read, the value of the corresponding SCPDR bit is returned directly.
Page 575: Table 18.10 Read/Write Operation Of The Sc Port Data Register (Scpdr)
Section 18 I/O Ports Table 18.10 Read/Write Operation of the SC Port Data Register (SCPDR) • For SCP4DT to SCP0DT SCPnMD1 SCPnMD0 Pin State Read Write Other function SCPDR value Value is written to SCPDR, but does not affect pin state. Output SCPDR value Write value is output from pin.
Page 576 Section 18 I/O Ports Rev. 5.00 May 29, 2006 page 528 of 698 REJ09B0146-0500...
Page 577: Section 19 A/D Converter (Adc)
Section 19 A/D Converter (ADC) Section 19 A/D Converter (ADC) This LSI includes a 10-bit successive-approximation A/D converter with a selection of up to four analog input channels. Figure 19.1 shows the block diagram of the A/D converter. 19.1 Features A/D converter features are listed below.
Page 578: Figure 19.1 A/D Converter Block Diagram
Section 19 A/D Converter (ADC) Internal Peripheral data bus data bus 10-bit φ/4 – Analog φ/8 Control circuit multi- Comparator plexer Sample-and- hold circuit interrupt signal ADTRG A/D converter Legend: ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D...
Page 579: Input/Output Pin
Section 19 A/D Converter (ADC) 19.2 Input/Output Pin Table 19.1 summarizes the A/D converter's input pins. AV and AV are the power supply for the analog circuits in the A/D converter. AVcc also functions as the A/D converter reference voltage. Table 19.1 A/D Converter Pins Pin Name Abbreviation...
Page 580: A/D Data Registers A To D (Addra To Addrd)
Section 19 A/D Converter (ADC) 19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel.
Page 581: A/D Control/Status Register (Adcsr)
Section 19 A/D Converter (ADC) 19.3.2 A/D Control/Status Register (ADCSR) ADCSR is an 8-bit read/write register that selects the mode and controls the A/D converter. Bit Name Initial Value Description R/(W) * A/D End Flag Indicates the end of A/D conversion. 0: [Clearing conditions] 1.
Page 582 Section 19 A/D Converter (ADC) Bit Name Initial Value Description ADST A/D Start Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.
Page 583 Section 19 A/D Converter (ADC) Bit Name Initial Value Description Channel Select These bits and the MULTI bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Single Mode Multi Mode and Scan (MULTI = 0) Mode (MULTI = 1) 000: AN0...
Page 584: A/D Control Register (Adcr)
Section 19 A/D Converter (ADC) 19.3.3 A/D Control Register (ADCR) ADCR is an 8-bit read/write register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'07 by a reset and in standby mode. Bit Name Initial Value Description TRGE1 Trigger Enable...
Page 585: Figure 19.2 A/D Data Register Access Operation (Reading H'aa40)
Section 19 A/D Converter (ADC) Figure 19.2 shows the data flow for access to an A/D data register. Upper byte read Module internal data bus interface (H'AA) TEMP (H'40) Upper byte of Lower byte of A/D data register A/D data register (H'AA) (H'40) Lower byte read...
Page 586: Access Size Of A/D Data Register
Section 19 A/D Converter (ADC) 19.5 Access Size of A/D Data Register 19.5.1 Word Access When A/D data registers (ADDRA to ADDRD) are read in word, A/D data register values are read from bits 15 to 8, and invalid data is read from bits 7 to 0. Figure 19.3 shows an example of reading ADDRAH.
Page 587: Operation
Section 19 A/D Converter (ADC) 19.6 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 19.6.1 Single Mode (MULTI = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit in ADCSR is set to 1 by software, or by external trigger input.
Page 588: Multi Mode (Multi = 1, Scn = 0)
Section 19 A/D Converter (ADC) Set * ADIE Set * Set * A/D conversion starts ADST Clear * Clear Channel 0 (AN0) Waiting operating Channel 1 (AN1) Waiting Waiting Waiting operating A/D conversion 1 A/D conversion result 2 Channel 2 (AN2) Waiting operating Channel 3 (AN3)
Page 589: Figure 19.6 Example Of A/D Converter Operation (Multi Mode, Channels An0 To An2 Selected)
Section 19 A/D Converter (ADC) Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are described next. Figure 19.6 shows a timing diagram for this example. 1. Multi mode is selected (MULTI = 1, SCN = 0), channel group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
Page 590: Scan Mode (Multi = 1, Scn = 1)
Section 19 A/D Converter (ADC) 19.6.3 Scan Mode (MULTI = 1, SCN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit in the ADCSR is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0).
Page 591: Input Sampling And A/D Conversion Time
Section 19 A/D Converter (ADC) Continuous A/D conversion Clear * Set * ADST Clear * Channel 0 (AN Waiting Waiting Waiting operating A/D conversion 1 A/D conversion 4 Channel 1 (AN Waiting Waiting Waiting operating A/D conversion 2 A/D conversion 5 Channel 2 (AN Waiting Waiting...
Page 592: Figure 19.8 A/D Conversion Timing
Section 19 A/D Converter (ADC) Pφ Address Write signal Input sampling timing CONV Legend: : A/D conversion start delay : Input sampling time : A/D conversion time CONV Notes: 1. ADCSR write cycle 2. ADCSR address Figure 19.8 A/D Conversion Timing Table 19.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1...
Page 593: External Trigger Input Timing
Section 19 A/D Converter (ADC) 19.6.5 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE1, TRGE0 bits in ADCR are set to 1. external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the ADST bit in ADCSR to 1, starting A/D conversion.
Page 594: Usage Note
Section 19 A/D Converter (ADC) Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (000 in the figure) to 000000001 (001 in the figure) (figure 19.10, item (1)). Full-scale error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the 1111111110 (110 in the figure) to the maximum 1111111111 (111 in the figure) (figure 19.10, item (2)).
Page 595: Processing Of Analog Input Pins
Section 19 A/D Converter (ADC) 19.9.2 Processing of Analog Input Pins To prevent damage from voltage surges at the analog input pins (AN0 to AN3), connect an input protection circuit like the one shown in figure 19.11. The circuit shown also includes an RC filter to suppress noise.
Page 596: Access Size And Read Data
Section 19 A/D Converter (ADC) 19.9.3 Access Size and Read Data Table 19.5 shows the relationship between access size and read data. Note the read data obtained with different access sizes, bus widths, and endian modes. The case is shown here in which H'3FF is obtained when AV is input as an analog input.
Page 597: Section 20 D/A Converter (Dac)
Section 20 D/A Converter (DAC) Section 20 D/A Converter (DAC) This LSI includes a D/A converter with two channels. Figure 20.1 shows a block diagram of the D/A converter. On-chip data bus Module data bus 8-bit D/A Control circuit Legend: DACR: D/A control register DADR0:...
Page 598: Input/Output Pin
Section 20 D/A Converter (DAC) 20.2 Input/Output Pin Table 20.1 summarizes the D/A converter's input and output pins. Table 20.1 D/A Converter Pins Pin Name Abbreviation Function Analog power-supply pin AVcc Input Analog power supply Analog ground pin AVss Input Analog ground and reference voltage Analog output pin 0 Output...
Page 599 Section 20 D/A Converter (DAC) Bit Name Initial Value Description DAOE1 D/A Output Enable 1 Controls D/A conversion and analog output. 0: DA1 analog output is disabled 1: Channel-1 D/A conversion and DA1 analog output are enabled DAOE0 D/A Output Enable 0 Controls D/A conversion and analog output.
Page 600: Operation
Section 20 D/A Converter (DAC) 20.4 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1.
Page 601: Section 21 User Debugging Interface (H-Udi)
Section 21 User Debugging Interface (H-UDI) Section 21 User Debugging Interface (H-UDI) The H-UDI (user debugging interface) performs on-chip debugging which is supported by the SH7706. The H-UDI described here is a serial interface which is pi-compatible with JTAG (Joint Test Action Group, IEEE Standard 1149.1 and IEEE Standard Test Access Port and Boundary- Scan Architecture) specifications.
Page 602: Feature
Section 21 User Debugging Interface (H-UDI) 21.1 Feature The H-UDI has the following features. • Support of the E10A emulator • Standard pin arrangement of JTAG • Real-time branch trace • 1-kbyte on-chip RAM for running the high-speed emulation program 21.2 Input/Output Pin Table 21.1 lists the pin configuration of the H-UDI.
Page 603: Register Description
Section 21 User Debugging Interface (H-UDI) 21.3 Register Description The H-UDI has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. • Bypass register (SDBPR) • Instruction register (SDIR) • Boundary register (SDBSR) 21.3.1 Bypass Register (SDBPR) The bypass register is a 1-bit register that cannot be accessed by the CPU.
Page 604: Boundary Scan Register (Sdbsr)
Section 21 User Debugging Interface (H-UDI) 21.3.3 Boundary Scan Register (SDBSR) The boundary scan register (SDBSR) is a shift register, located on the PAD, for controlling the input/output pins of this LSI. Using the EXTEST and SAMPLE/PRELOAD commands, a boundary scan test conforming to the JTAG standard can be carried out.
Page 605 Section 21 User Debugging Interface (H-UDI) Pin Name Pin Name Control Control Control Control Control Control Control Control Control Control Control BS/PTC[0] WE2/DQMUL/ICIORD/PTC[1] WE3/DQMUU/ICIOWR/PTC[2] D31/PTB[7] Control CS2/PTC[3] D30/PTB[6] Control CS3/PTC[4] D29/PTB[5] Control D28/PTB[4] Control D27/PTB[3] Control D26/PTB[2] Control D25/PTB[1] Control D24/PTB[0] Control D23/PTA[7]...
Page 606 Section 21 User Debugging Interface (H-UDI) Pin Name Pin Name Control Control Control Control Control Control Control Control BS/PTC[0] Control Control WE0/DQMLL Control WE1/DQMLU/WE Control WE2/DQMUL/ICIORD/PTC[1] Control WE3/DQMUU/ICIOWR/PTC[2] Control BS/PTC[0] RD/WR Control Control CS2/PTC[3] WE0/DQMLL Control CS3/PTC[4] WE1/DQMLU/WE Control WE2/DQMUL/ICIORD/PTC[1] Control Control WE3/DQMUU/ICIOWR/PTC[2]...
Page 607 Section 21 User Debugging Interface (H-UDI) Pin Name Pin Name RASU/PTD[1] DACK0/PTE[0] CASL/PTD[2] DACK1/PTE[1] CASU/PTD[3] DRAK0/PTE[2] CKE/PTD[4] DRAK1/PTTE[3] IOIS16/PTD[5] AUDATA[0]/PTF[0] BREQ AUDATA[1]/PTF[1] WAIT AUDATA[2]/PTF[2] DACK0/PTE[0] AUDATA[3]/PTF[3] AUDSYNC/PTF[4] DACK1/PTE[1] ASEBRKAK/PTF[6] DRAK0/PTE[2] CS4/PTC[5] DRAK1/PTE[3] Control CS5/CE1A/PTC[6] AUDATA[0]/PTF[0] Control CS6/CE1B/PTC[7] AUDATA[1]/PTF[1] Control CE2A/PTD[6] AUDATA[2]/PTF[2] Control CE2B/PTD[7]...
Page 608 Section 21 User Debugging Interface (H-UDI) Pin Name Pin Name AUDSYNC/PTF[4] IRQOUT/PTE[7] Control ASEBRKAK/PTF[6] Control TxD0/SCPT[0] STATUS0/PTE[4] SCK0/SCPT[1] STATUS1/PTE[5] TxD2/SCPT[2] TCLK/PTE[6] SCK2/SCPT[3] IRQOUT/PTE[7] RTS2/SCPT[4] SCK0/SCPT[1] IRQ0/IRL0/PTH[0] SCK2/SCPT[3] IRQ1/IRL1/PTH[1] RTS2/SCPT[4] IRQ2/IRL2/PTH[2] RxD0/SCPT[0] IRQ3/IRL3/PTH[3] RxD2/SCPT[2] IRQ4/PTH[4] CTS2/IRQ5/SCPT[5] DREQ0/PTH[5] DREQ1/PTH[6] IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] STATUS0/PTE[4] Control IRQ2/IRL2/PTH[2] STATUS1/PTE[5]...
Page 609: H-Udi Operations
Section 21 User Debugging Interface (H-UDI) 21.4 H-UDI Operations 21.4.1 TAP Controller Figure 21.2 shows the internal states of TAP controller. State transitions basically conform with the JTAG standard. Test-logic-reset Run-test/idle Select-DR-scan Select-IR-scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR...
Page 610: Reset Configuration
Section 21 User Debugging Interface (H-UDI) 21.4.2 Reset Configuration Table 21.3 Reset Configuration ASDMD0 ASDMD0 * RESETP RESETP TRST TRST ASDMD0 ASDMD0 RESETP RESETP TRST TRST Chip State Normal reset and H-UDI reset Normal reset H-UDI reset only Normal operation Reset hold * During ASE user mode * : Normal reset...
Page 611: H-Udi Reset
Section 21 User Debugging Interface (H-UDI) 21.4.3 H-UDI Reset An H-UDI reset is executed by setting an H-UDI reset assert command in SDIR. An H-UDI reset is of the same kind as a power-on reset. An H-UDI reset is released by inputting an H-UDI reset negate command.
Page 612: Boundary Scan
Section 21 User Debugging Interface (H-UDI) 21.5 Boundary Scan A command can be set in SDIR by the H-UDI to place the H-UDI pins in the boundary scan mode stipulated by JTAG. 21.5.1 Supported Instructions This LSI supports the three essential instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST).
Page 613: Notes For Boundary Scan
Section 21 User Debugging Interface (H-UDI) Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The instruction code is 0000. 21.5.2 Notes for Boundary Scan 1.
Page 614 Section 21 User Debugging Interface (H-UDI) Rev. 5.00 May 29, 2006 page 566 of 698 REJ09B0146-0500...
Page 615: Section 22 Power-Down Modes
Section 22 Power-Down Modes Section 22 Power-Down Modes In the power-down modes, all CPU and some on-chip supporting module functions are halted. This lowers power consumption. The SH7706 has four power-down modes: 1. Sleep mode 2. Software standby mode 3. Module standby function (TMU, RTC, SCI, UBC, DMAC, DAC, ADC, and SCIF on-chip supporting modules) 4.
Page 616: Table 22.1 Power-Down Modes
Section 22 Power-Down Modes Table 22.1 Power-Down Modes State On-Chip Transition Reg- On-Chip Peripheral External Canceling Mode Conditions ister Memory Modules Pins Memory Procedure Sleep Execute SLEEP Runs Halts Held Held Runs Held Refresh 1. Interrupt mode instruction with 2. Reset STBY bit cleared to 0 in STBCR Halts *...
Page 617: Input/Output Pin
Section 22 Power-Down Modes 22.1 Input/Output Pin Table 22.2 lists the pins used for the power-down modes. Table 22.2 Pin Configuration Pin Name Symbol Description Processing state 1 STATUS1 Operating state of the processor. STATUS1 STATUS0 state Processing state 0 STATUS0 High-level High-level Reset...
Page 618 Section 22 Power-Down Modes Bit Name Initial Value Description STBXTL Standby Crystal Specifies whether the crystal oscillator halts or oscillates in standby mode. 0: Halts the oscillation of the crystal oscillator in standby mode. 1: Continues the oscillation of the crystal oscillator even in standby mode.
Page 619: Standby Control Register 2 (Stbcr2)
Section 22 Power-Down Modes 22.2.2 Standby Control Register 2 (STBCR2) The standby control register 2 (STBCR2) is a read/write 8-bit register that sets the power-down mode. Bit Name Initial Value Description — Reserved This bit is always read as 0. The write value should always be 0.
Page 620 Section 22 Power-Down Modes Bit Name Initial Value Description MSTP6 Module Stop 6 Specifies halting of clock supply to the DAC (an on-chip peripheral module). When the MSTP6 bit is set to 1, the supply of the clock to the DAC is halted.
Page 621: Operation
Section 22 Power-Down Modes 22.3 Operation 22.3.1 Sleep Mode Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged.
Page 622: Software Standby Mode
Section 22 Power-Down Modes 22.3.2 Software Standby Mode Transition to Software Standby Mode To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The chip moves from the program execution state to software standby mode. In software standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock and on- chip supporting modules as well.
Page 623: Figure 22.1 Canceling Software Standby Mode With Stbcr.stby
Section 22 Power-Down Modes Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRL * , IRQ * , or on-chip supporting module (except the interval timer) * interrupt, the clock will be supplied to the entire chip and software standby mode canceled after the time set in the WDT's timer control/status register has elapsed.
Page 624: Module Standby Function
Section 22 Power-Down Modes Clock Pause Function In software standby mode, the clock input from the EXTAL pin or CKIO pin can be halted and the frequency can be changed. This function is used as follows: 1. Enter software standby mode using the appropriate procedures. 2.
Page 625 Section 22 Power-Down Modes Value Description MSTP8 UBC runs. Supply of clock to UBC halted. MSTP7 DMAC runs. Supply of clock to DMAC halted. MSTP6 DAC runs. Supply of clock to DAC halted. MSTP5 ADC runs. Supply of clock to ADC halted, and all registers initialized. MSTP4 SCIF runs.
Page 626: Timing Of Status Pin Changes
Section 22 Power-Down Modes 22.3.4 Timing of STATUS Pin Changes The timing of STATUS1 and STATUS0 pin changes is shown in figures 22.2 through 22.9 Timing for Resets Power-On Reset: CKIO PLL settling time RESETP Reset * Normal * Normal* STATUS 0 to 5 Bcyc * 0 to 30 Bcyc *...
Page 627: Figure 22.4 Software Standby To Interrupt Status Output
Section 22 Power-Down Modes Timing for Canceling Software Standbys Software Standby to Interrupt: Oscillation stops Interrupt request WDT overflow CKIO WDT count Normal * Standby * Normal * STATUS Notes: 1. Standby: LH (STATUS1 low, STATUS0 high) 2. Normal: LL (STATUS1 low, STATUS0 low) Figure 22.4 Software Standby to Interrupt STATUS Output Software Standby to Power-On Reset: Oscillation stops...
Page 628: Figure 22.6 Software Standby To Manual Reset Status Output
Section 22 Power-Down Modes Software Standby to Manual Reset: Oscillation stops Reset CKIO RESETM * Normal * Standby * Reset * Normal * STATUS 0 to 20 Bcyc * Notes: 1. When software standby mode is cleared with a manual reset, the WDT does not count. Keep RESETM low during the PLL’s oscillation settling time.
Page 629: Figure 22.8 Sleep To Power-On Reset Status Output
Section 22 Power-Down Modes Sleep to Power-On Reset: Reset CKIO RESETP * Normal * Sleep * Reset * Normal * STATUS 0 to 10 Bcyc * 0 to 30 Bcyc * Notes: 1. When the PLL1’s multiplication ratio is changed by a power-on reset, keep RESETP low during the PLL’s oscillation settling time.
Page 630: Hardware Standby Function
Section 22 Power-Down Modes 22.3.5 Hardware Standby Function Transition to Hardware Standby Mode Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode, all modules except those operating on an RTC clock are halted, as in the software standby mode entered on execution of a SLEEP instruction ((software) standby mode).
Page 631: Figure 22.10 Hardware Standby Mode (When Ca Goes Low In Normal Operation)
Section 22 Power-Down Modes Hardware Standby Mode Timing Figures 22.10 and 22.11 show examples of pin timing in hardware standby mode. The CA pin is sampled using EXTAL2 (32.768 kHz), and a hardware standby request is only recognized when the pin is low for two consecutive clock cycles. The CA pin must be held low while the chip is in hardware standby mode.
Page 632: Figure 22.11 Hardware Standby Mode Timing (When Ca Goes Low During Wdt Operation On Standby Mode Cancellation)
Section 22 Power-Down Modes CKIO RESETP Standby * Normal * Standby * Reset * STATUS Undefined 0 to 10 Bcyc* WDT operation 2 Rcyc or more * Notes: 1. Reset: HH (STATUS1 high, STATUS0 high) 2. Standby: LH (STATUS1 low, STATUS0 high) 3.
Page 633: Section 23 List Of Registers
Section 23 List of Registers Section 23 List of Registers 23.1 Register Address Map Module * Bus * Access Size (Bits) * Control Register Address Size (Bits) PTEH H'FFFFFFF0 PTEL H'FFFFFFF4 H'FFFFFFF8 H'FFFFFFFC MMUCR H'FFFFFFE0 BASRA H'FFFFFFE4 BASRB H'FFFFFFE8 H'FFFFFFEC CCR2 H'A40000B0 H'FFFFFFD0...
Page 634 Section 23 List of Registers Module * Bus * Access Size (Bits) * Control Register Address Size (Bits) BCR1 H'FFFFFF60 BCR2 H'FFFFFF62 WCR1 H'FFFFFF64 WCR2 H'FFFFFF66 H'FFFFFF68 H'FFFFFF6C RTCSR H'FFFFFF6E RTCNT H'FFFFFF70 RTCOR H'FFFFFF72 RFCR H'FFFFFF74 SDMR H'FFFFD000 to — H'FFFFEFFF R64CNT H'FFFFFEC0...
Page 635 Section 23 List of Registers Module * Bus * Access Size (Bits) * Control Register Address Size (Bits) TOCR H'FFFFFE90 TSTR H'FFFFFE92 TCOR_0 H'FFFFFE94 TCNT_0 H'FFFFFE98 TCR_0 H'FFFFFE9C TCOR_1 H'FFFFFEA0 TCNT_1 H'FFFFFEA4 TCR_1 H'FFFFFEA8 TCOR_2 H'FFFFFEAC TCNT_2 H'FFFFFEB0 TCR_2 H'FFFFFEB4 TCPR_2 H'FFFFFEB8 SCSMR...
Page 636 Section 23 List of Registers Module * Bus * Access Size (Bits) * Control Register Address Size (Bits) SAR_1 DMAC H'A4000030 16, 32 DAR_1 H'A4000034 16, 32 DMATCR_1 H'A4000038 16, 32 CHCR_1 H'A400003C 8, 16, 32 SAR_2 H'A4000040 16, 32 DAR_2 H'A4000044 16, 32...
Page 637 Section 23 List of Registers Module * Bus * Access Size (Bits) * Control Register Address Size (Bits) PACR PORT H'A4000100 PBCR H'A4000102 PCCR H'A4000104 PDCR H'A4000106 PECR H'A4000108 PFCR H'A400010A PGCR H'A400010C PHCR H'A400010E PJCR H'A4000110 SCPCR H'A4000116 PADR H'A4000120 PBDR H'A4000122...
Page 638 Section 23 List of Registers Notes: 1. Modules: CCN: Cache controller UBC: User break controller CPG: Clock pulse generator BSC: Bus state controller RTC: Realtime clock INTC: Interrupt controller TMU: Timer unit SCI: Serial communication interface 2. Internal buses: L: CPU, CCN, cache, and TLB connected I: BSC, cache, DMAC, INTC, CPG, and H-UDI connected P: BSC and peripheral modules (RTC, TMU, SCI, SCIF, A/D, D/A, DMAC, ports, CMT) connected...
Page 639: Register Bits
Section 23 List of Registers 23.2 Register Bits The following are the bit-name of each registers. The 16-bit and 32-bit registers are shown by two and four 8-bit rows, respectively. Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 640 Section 23 List of Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCOR_1 TCNT_1 TCR_1 — — — — — — — — — UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TCOR_2 TCNT_2...
Page 641 Section 23 List of Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RYRCNT 10 years 1 year RSECAR 10 sec 1 sec RMINAR 10 min 1 min RHRAR — 10 hours 1 hour RWKAR...
Page 642 Section 23 List of Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module RTCOR — — — — — — — — RFCR — — — — — — — —...
Page 643 Section 23 List of Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BBRB — — — — — — — — CDB1 CDB0 IDB1 IDB0 RWB1 RWB0 SZB1 SZB0 BARA BAA31 BAA30...
Page 644 Section 23 List of Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INTEVT — — — — — — — — — — — — — — — — —...
Page 645 Section 23 List of Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INTEVT2 — — — — — — — — INTC — — — — — — — —...
Page 646 Section 23 List of Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SAR_1 DMAC DAR_1 DMATCR_1 — — — — — — — — CHCR_1 — — — — —...
Page 647 Section 23 List of Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SAR_3 DMAC DAR_3 DMATCR_3 — — — — — — — — CHCR_3 — — — — —...
Page 648 Section 23 List of Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADDRAH ADDRAL — — — — — — ADDRBH ADDRBL — — — — — — ADDRCH ADDRCL —...
Page 649 Section 23 List of Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SCPCR — — — — SCP5MD1 SCP5MD0 SCP4MD1 SCP4MD0 PORT SCP3MD1 SCP3MD0 SCP2MD1 SCP2MD0 SCP1MD1 SCP1MD0 SCP0MD1 SCP0MD0 PADR PA7DT PA6DT...
Page 650: Register States In Processing Mode
Section 23 List of Registers 23.3 Register States in Processing Mode Register Power-on Manual Hardware Software Module Name Reset Reset Standby Standby Standby Sleep Module PTEH Undefined Undefined Held Held Held Held PTEL Undefined Undefined Held Held Held Held Undefined Undefined Held Held...
Page 651 Section 23 List of Registers Register Power-on Manual Hardware Software Module Name Reset Reset Standby Standby Standby Sleep Module BCR1 Initialized Held Held Held Held Held BCR2 Initialized Held Held Held Held Held WCR1 Initialized Held Held Held Held Held WCR2 Initialized Held...
Page 652 Section 23 List of Registers Register Power-on Manual Hardware Software Module Name Reset Reset Standby Standby Standby Sleep Module TCNT_0 Initialized Initialized Held Held Held Held TCR_0 Initialized Initialized Held Held Held Held TCOR_1 Initialized Initialized Held Held Held Held TCNT_1 Initialized Initialized...
Page 653 Section 23 List of Registers Register Power-on Manual Hardware Software Module Name Reset Reset Standby Standby Standby Sleep Module SAR_2 Undefined Undefined Held Held Held Held DMAC DAR_2 Undefined Undefined Held Held Held Held DMATCR_2 Undefined Undefined Held Held Held Held CHCR_2 Initialized...
Page 654 Section 23 List of Registers Register Power-on Manual Hardware Software Module Name Reset Reset Standby Standby Standby Sleep Module PGCR Initialized Held Held Held Held Held PORT PHCR Initialized Held Held Held Held Held PJCR Initialized Held Held Held Held Held SCPCR Initialized...
Page 655: Section 24 Electrical Characteristics
Section 24 Electrical Characteristics Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 shows the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Symbol Rating Unit Power supply voltage (I/O) VccQ –0.3 to +4.2 Power supply voltage (internal) Vcc –0.3 to +2.5 Vcc –...
Page 656 Section 24 Electrical Characteristics Waveforms at power-on are shown in the following figure. (Max. 1 ms) 3.3 V 3.3 V power 1.9 V 1.9 V power RESETP Pin states undefined All other pins * Pin states undefined Power-on reset state Note: * Except power/GND, clock related, and analog pins Power-On Sequence Rev.
Page 657: Dc Characteristics
Section 24 Electrical Characteristics 24.2 DC Characteristics Table 24.2 lists DC characteristics. Table 24.2 DC Characteristics Condition: Ta = –20 to +75°C Item Symbol Unit Measurement Conditions Power VccQ supply Vcc, 1.75 1.90 2.05 voltage Vcc-PLL1, Vcc-PLL2, Vcc-RTC Icc * Current Normal —...
Page 658 Section 24 Electrical Characteristics Item Symbol Unit Measurement Conditions RESETP, VccQ × Input low –0.3 — RESETM, voltage NMI, IRQ5 to IRQ0, MD5 to MD0, ASEMD0, CA, TRST, ADTRG, EXTAL, CKIO AVcc × Port J –0.3 — VccQ × Other –0.3 —...
Page 659: Table 24.3 Permitted Output Current Values
Section 24 Electrical Characteristics Item Symbol Unit Measurement Conditions Analog During A/D AIcc — power- conversion supply During A/D — current and D/A conversion Idle — 0.01 µA Ta = 25°C Notes: Regardless of whether PLL or RTC is used, connect Vcc – PLL and Vcc – RTC to Vcc, and Vss –...
Page 660: Ac Characteristics
Section 24 Electrical Characteristics 24.3 AC Characteristics In general, inputting for this LSI should be clock synchronous. Keep the setup and hold times for each input signal unless otherwise specified. Operating conditons are as follows: VccQ = 3.3 ± 0.3V Vcc = 1.9 ±...
Page 661 Section 24 Electrical Characteristics Item Symbol Unit Figure CKIO clock input frequency 66.67 24.2 CKIO clock input cycle time CKIcyc CKIO clock input low pulse width — CKIL CKIO clock input high pulse width — CKIH CKIO clock input rise time —...
Page 662: Figure 24.1 Extal Clock Input Timing
Section 24 Electrical Characteristics EXcyc EXTAL * (input) 1/2 V 1/2 V Note: * The clock input from the EXTAL pin. Figure 24.1 EXTAL Clock Input Timing CKIcyc CKIH CKIL CKIO (input) 1/2 V 1/2 V CKIR CKIF Figure 24.2 CKIO Clock Input Timing CKOH CKOL CKIO...
Page 663: Figure 24.4 Power-On Oscillation Settling Time
Section 24 Electrical Characteristics Stable oscillation CKIO, internal clock – RTC – PLL1 RESPW RESPS – PLL2 OSC1 RESETP Note: Oscillation settling time in clock mode 2. (min. 100 µs) except in clock mode 2. Oscillation settling time becomes t OSC1 PLL1 Figure 24.4 Power-On Oscillation Settling Time...
Page 664: Figure 24.6 Oscillation Settling Time At Standby Return (Return By Nmi)
Section 24 Electrical Characteristics Standby Stable oscillation CKIO, internal clock OSC3 Note: Oscillation settling time in the Clock-mode-2 and Oscillation-halt-mode Figure 24.6 Oscillation Settling Time at Standby Return (Return by NMI) Standby Stable oscillation CKIO, internal clock OSC4 IRQ4 to IRQ0 Note: Oscillation settling time in the Clock-mode-2 and Oscillation-halt-mode Figure 24.7 Oscillation Settling Time at Standby Return (Return by IRQ or IRL)
Page 665: Figure 24.8 Pll Synchronization Settling Time By Reset Or Nmi At The Returning From Standby Mode (Return By Reset Or Nmi)
Section 24 Electrical Characteristics Reset or NMI interrupt request Stable input clock Stable input clock EXTAL input or CKIO input PLL synchronization PLL synchronization PLL1 PLL output, CKIO output Internal clock STATUS 0 Normal Standby Normal STATUS 1 Note: Oscillation settling time in the Clock-mode-0, 1, 7 and Oscillation-halt-mode Figure 24.8 PLL Synchronization Settling Time by Reset or NMI at the Returning from Standby Mode (Return by Reset or NMI) IRQ4 to IRQ0/IRL3 to IRL0 interrupt request...
Page 666: Figure 24.10 Pll Synchronization Settling Time When Frequency Multiplication Rate Modified
Section 24 Electrical Characteristics Multiplication rate modified EXTAL input * PLL2 PLL output, CKIO output * Internal clock Notes: 1. CKIO input in clock mode 7 2. PLL output in clock mode 7 Figure 24.10 PLL Synchronization Settling Time when Frequency Multiplication Rate Modified Rev.
Page 667: Control Signal Timing
Section 24 Electrical Characteristics 24.3.2 Control Signal Timing Table 24.6 Control Signal Timing Item Symbol Unit Figure RESETP pulse width 20 * — tcyc 24.11, RESPW RESETP setup time * 24.12 — RESPS RESETP hold time — RESPH RESETM pulse width 12 * —...
Page 668: Figure 24.11 Reset Input Timing
Section 24 Electrical Characteristics CKIO RESPS/MS RESPS/MS RESPW/MW RESETP, RESETM Figure 24.11 Reset Input Timing CKIO RESPH/MH RESPS/MS RESETP, RESETM NMIH NMIS IRQH IRQS IRQ5 to IRQ0 Figure 24.12 Interrupt Signal Input Timing CKIO IRQOD IRQOD IRQOUT Figure 24.13 IRQOUT IRQOUT Timing IRQOUT IRQOUT...
Page 669: Figure 24.14 Bus Release Timing
Section 24 Electrical Characteristics CKIO BREQH BREQS BREQH BREQS BREQ BACKD BACKD BACK BON2 BOFF2 RD, RD/WR, CAS, CAS, CSn, WEn, BS BON1 BOFF1 A25 to A0, D31 to D0 Figure 24.14 Bus Release Timing Normal mode Standby mode Normal mode CKIO STATUS 0, STATUS 1...
Page 670: Ac Bus Timing
Section 24 Electrical Characteristics 24.3.3 AC Bus Timing Table 24.7 Bus Timing (Clock Modes 0/1/2/7) Item Symbol Unit Figure Address delay time 24.16 to 24.36, 24.39 to 24.46 Address setup time — 24.16 to 24.18 Address hold time — 24.16 to 24.21 BS delay time —...
Page 671 Section 24 Electrical Characteristics Item Symbol Unit Figure CKE delay time 24.38 CKED ICIORD delay time — 24.44 to 24.46 ICRSD ICIOWR delay time — 24.44 to 24.46 ICWSD IOIS16 setup time — 24.45, 24.46 IO16S IOIS16 hold time — 24.45, 24.46 IO16H DACK delay time 1...
Page 672: Basic Timing
Section 24 Electrical Characteristics 24.3.4 Basic Timing CKIO A25 to A0 CSD1 CSD2 RDH1 RD/WR (read) RDH1 RDS1 D31 to D0 (read) (write) WDH3 WDD1 WDH1 D31 to D0 (write) DAKD2 DAKD1 DACKn Note: tRDH1: Stipulated from the faster negate timing of CSn or RD tAH: Stipulated from the slower negate timing of CSn, RD, or WEn Figure 24.16 Basic Bus Cycle (No Wait) Rev.
Page 673: Figure 24.17 Basic Bus Cycle (One Wait)
Section 24 Electrical Characteristics CKIO A25 to A0 CSD2 CSD1 RDH1 RD/WR (read) RDH1 RDS1 D31 to D0 (read) (write) WDH3 WDD1 WDH1 D31 to D0 (write) DAKD2 DAKD1 DACKn WAIT Figure 24.17 Basic Bus Cycle (One Wait) Rev. 5.00 May 29, 2006 page 625 of 698 REJ09B0146-0500...
Page 674: Figure 24.18 Basic Bus Cycle (External Wait)
Section 24 Electrical Characteristics CKIO A25 to A0 CSD1 CSD2 RDH1 RD/WR (read) RDH1 RDS1 D31 to D0 (read) (write) WDH3 WDD1 WDH1 D31 to D0 (write) DAKD2 DAKD1 DACKn WAIT Note: tRDH1: Stipulated from the faster negate timing of CSn or RD tAH: Stipulated from the slower negate timing of CSn, RD, or WEn Figure 24.18 Basic Bus Cycle (External Wait) Rev.
Page 675: Burst Rom Timing
Section 24 Electrical Characteristics 24.3.5 Burst ROM Timing CKIO A25 to A4 A3 to A0 CSD2 CSD1 RDH1 RD/WR RDH1 RDH1 RDS1 D31 to D0 DAKD1 DAKD2 DACKn WAIT Note: In the write cycle, the basic bus cycle, the basic bus cycle is performed. tRDH1: Stipulated from the faster negate timing of CSn or RD tAH: Stipulated from the slower negate timing of CSn, RD, or WEn Figure 24.19 Burst ROM Bus Cycle (No Wait)
Page 676: Figure 24.20 Burst Rom Bus Cycle (Two Waits)
Section 24 Electrical Characteristics CKIO A25 to A4 A3 to A0 CSD2 CSD1 RDH1 RD/WR RDH1 RDH1 RDH1 RDS1 RDS1 D31 to D0 DAKD1 DAKD2 DACKn WAIT Note: In the write cycle, the basic bus cycle is performed. Figure 24.20 Burst ROM Bus Cycle (Two Waits) Rev.
Page 677: Figure 24.21 Burst Rom Bus Cycle (External Wait)
Section 24 Electrical Characteristics CKIO A25 to A4 A3 to A0 CSD2 CSD1 RDH1 RD/WR RSD1 RSD1 RDH1 RDH1 RDS1 D31 to D0 DAKD2 DAKD1 DACKn WAIT Note: In the write cycle, the basec bus cycle is performed. tRDH1: Stipulated from the faster negate timing of CSn or RD tAH: Stipulated from the slower negate timing of CSn, RD, or WEn Figure 24.21 Burst ROM Bus Cycle (External Wait) Rev.
Page 678: Synchronous Dram Timing
Section 24 Electrical Characteristics 24.3.6 Synchronous DRAM Timing (Tpc) CKIO Row address A25 to A16 Read A A12 or A11 Row address command A15 to A0 Column address Row address CSD3 CSD3 RD/WR RASD RASD CASD CASD DQMD DQMD DQMxx RDS2 RDH2 D31 to D0...
Page 679: Figure 24.23 Synchronous Dram Read Bus Cycle (Rcd = 2, Cas Latency = 2, Tpc = 1)
Section 24 Electrical Characteristics (Tpc) (Tpc) CKIO A25 to A16 Row address Read A A12 or A11 Row address command Row address Column address A15 to A0 CSD3 CSD3 RD/WR RASD RASD CASD CASD DQMD DQMD DQMxx RDS2 RDH2 D31 to D0 (High) DAKD1 DAKD1...
Page 680: Figure 24.24 Synchronous Dram Read Bus Cycle
Section 24 Electrical Characteristics Tc2/Td1 Tc3/Td2 Tc4/Td3 (Tpc) (Tpc) CKIO Row address A25 to A16 Read command Read A A12 or A11 address command Column address (1-4) A15 to A0 address CSD3 CSD3 RD/WR RASD RASD CASD CASD DQMD DQMD DQMxx RDS2 RDH2...
Page 681: Figure 24.25 Synchronous Dram Read Bus Cycle
Section 24 Electrical Characteristics Tc3 Tc4/Td1 Td2 (Tpc) CKIO A25 to A16 Row address A12 or A11 Read command address A15 to A0 Column address (1-4) address CSD3 CSD3 RD/WR RASD RASD CASD CASD DQMD DQMD DQMxx RDS2 RDH2 RDS2 RDH2 D31 to D0 (read)
Page 682: Figure 24.26 Synchronous Dram Write Bus Cycle (Rcd = 0, Tpc = 0, Trwl = 0)
Section 24 Electrical Characteristics (Trwl) (Tpc) CKIO A25 to A16 Row address Write A A12 or A11 Row address command Column A15 to A0 Row address address CSD3 CSD3 RD/WR RASD RASD CASD CASD DQMD DQMD DQMxx WDH2 WDD2 D31 to D0 (High) DAKD1 DAKD1...
Page 683: Figure 24.27 Synchronous Dram Write Bus Cycle (Rcd = 2, Tpc = 1, Trwl = 1)
Section 24 Electrical Characteristics (Trwl) (Trwl) (Tpc) (Tpc) CKIO A25 to A16 Row address Write A A12 or A11 address command Column A15 to A0 address address CSD3 CSD3 RD/WR RASD RASD CASD CASD DQMD DQMD DQMxx WDH2 WDD2 D31 to D0 (High) DAKD1 DAKD1...
Page 684: Figure 24.28 Synchronous Dram Write Bus Cycle
Section 24 Electrical Characteristics (Trwl) (Tpc) (Tpc) CKIO A25 to A16 Row address A12 or A11 Write A Write command address command Column address (1-4) A15 to A0 address CSD3 CSD3 RD/WR RASD RASD CASD CASD DQMD DQMD DQMxx WDD2 WDD2 WDH2 D31 to D0...
Page 685: Figure 24.29 Synchronous Dram Write Bus Cycle
Section 24 Electrical Characteristics (Trwl) (Tpc) CKIO Row address A25 to A16 Write A A12 or A11 Write command command address Column address (1-4) A15 to A0 address CSD3 CSD3 RD/WR RASD RASD CASD CASD DQMD DQMD DQMxx WDD2 WDD2 WDH2 D31 to D0 (High)
Page 686: Figure 24.30 Synchronous Dram Burst Read Bus Cycle (Ras Down, Same Row Address, Cas Latency = 1)
Section 24 Electrical Characteristics Tnop Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO A25 to A16 Row address Read command A12 or A11 Column address A15 to A0 CSD3 CSD3 RD/WR RASD2 CASD2 CASD2 DQMD DQMD DQMxx RDS2 RDH2 RDS2 RDH2 D31 to D0 (High) DAKD1 DAKD1...
Page 687: Figure 24.31 Synchronous Dram Burst Read Bus Cycle (Ras Down, Same Row Address, Cas Latency = 2)
Section 24 Electrical Characteristics Tc3/Td1 Tc4/Td2 CKIO A25 to A16 Row address A12 or A11 Read command A15 to A0 Column address CSD3 CSD3 RD/WR RASD CASD CASD DQMD DQMD DQMxx RDS2 RDH2 RDS2 RDH2 D31 to D0 (High) DAKD1 DAKD1 DACKn Figure 24.31 Synchronous DRAM Burst Read Bus Cycle...
Page 688: Figure 24.32 Synchronous Dram Burst Read Bus Cycle (Ras Down, Different Row Address, Tpc = 0, Rcd = 0, Cas Latency = 1)
Section 24 Electrical Characteristics Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO Row address A25 to A16 Read command A12 or A11 address Column address address A15 to A0 CSD3 CSD3 RD/WR RASD RASD CASD CASD DQMD DQMD DQMD DQMxx RDS2 RDH2 RDS2 RDH2 D31 to D0 (HIGH) DAKD1...
Page 689: Figure 24.33 Synchronous Dram Burst Read Bus Cycle (Ras Down, Different Row Address, Tpc = 1, Rcd = 0, Cas Latency = 1)
Section 24 Electrical Characteristics Tc2/Td1 Tc3/Td2 Tc4/Td3 CKIO Row address A25 to A16 Read command A12 or A11 address Column address address A15 to A0 CSD3 CSD3 RD/WR RASD RASD RASD RASD CASD CASD DQMD DQMD DQMD DQMxx RDS2 RDH2 RDS2 RDH2 (HIGH)
Page 690: Figure 24.34 Synchronous Dram Burst Write Bus Cycle (Ras Down, Same Row Address)
Section 24 Electrical Characteristics CKIO Row address A25 to A16 Write command A12 or A11 Column address A15 to A0 CSD3 CSD3 RD/WR RASD RASD CASD CASD DQMD DQMD DQMxx WDD2 WDD2 D31 to D0 (HIGH) t DAKD1 t DAKD1 DACKn Figure 24.34 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Same Row Address)
Page 691: Figure 24.35 Synchronous Dram Burst Write Bus Cycle (Ras Down, Different Row Address, Tpc = 0, Rcd = 0)
Section 24 Electrical Characteristics CKIO Row address A25 to A16 Write command A12 or A11 address Column address address A15 to A0 CSD3 CSD3 RD/WR RASD RASD CASD CASD DQMD DQMD DQMD DQMxx WDD2 WDD2 D31 to D0 (HIGH) t DAKD1 t DAKD1 DACKn Figure 24.35 Synchronous DRAM Burst Write Bus Cycle...
Page 692: Figure 24.36 Synchronous Dram Burst Write Bus Cycle (Ras Down, Different Row Address, Tpc = 1, Rcd = 1)
Section 24 Electrical Characteristics CKIO Row address A25 to A16 Write command A12 or A11 address Column address address A15 to A0 CSD3 CSD3 RD/WR RASD RASD RASD RASD CASD CASD DQMD DQMD DQMD DQMxx WDD2 WDD2 D31 to D0 (HIGH) t DAKD1 t DAKD1...
Page 693: Figure 24.37 Synchronous Dram Auto-Refresh Timing (Tras = 1, Tpc = 1)
Section 24 Electrical Characteristics TRrw TRrw TRrw (Tpc) (Tpc) CKIO (High) CSD3 CSD3 RASD RASD RASD RASD CASD CASD RD/WR Figure 24.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) TRa1 (TRs2) (TRs2) TRs3 (Tpc) (Tpc) CKIO CKED CKED CSD3 CSD3...
Page 694: Figure 24.39 Synchronous Dram Mode Register Write Cycle
Section 24 Electrical Characteristics TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 CKIO A11 (A10) * A12 (A11) * A10 to A2 (A9 to A1) * CSD3 CSD3 RD/WR RASD RASD RASD RASD CASD CASD CASxx D31 to D0 (High) DAKD1 DAKD1 DACKn...
Page 695: Pcmcia Timing
Section 24 Electrical Characteristics 24.3.7 PCMCIA Timing pcm1 pcm2 CKIO A25 to A0 CSD1 CSD1 CExx RD/WR (read) RDH1 RDS1 D15 to D0 (read) (write) WDH4 WDD1 WDH1 D15 to D0 (write) DAKD1 DAKD1 DACKn Figure 24.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) Rev.
Page 696: Figure 24.41 Pcmcia Memory Bus Cycle (Ted = 2, Teh = 1, One Wait, External Wait)
Section 24 Electrical Characteristics pcm0 pcm0w pcm1 pcm1w pcm1w pcm2 pcm2w CKIO A25 to A0 CSD1 CSD1 CExx RD/WR (read) RDH1 RDS1 D15 to D0 (read) (write) WDH4 WDH1 WDD1 D15 to D0 (write) DAKD1 DAKD1 DACKn WAIT Figure 24.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait) Rev.
Page 697: Figure 24.42 Pcmcia Memory Bus Cycle (Burst Read, Ted = 0, Teh = 0, No Wait)
Section 24 Electrical Characteristics pcm1 pcm2 pcm1 pcm2 pcm1 pcm2 pcm1 pcm2 CKIO A25 to A4 A3 to A0 CSD1 CSD1 CExx RD/WR (read) RDH1 RDH1 RDS1 RDS1 D15 to D0 (read) DAKD1 DAKD1 DACKn Note: Even though burst mode is set, write cycle operation is the same as in normal mode. Figure 24.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait) Rev.
Page 698: Figure 24.43 Pcmcia Memory Bus Cycle (Burst Read, Ted = 1, Teh = 1, Two Waits, Burst Pitch = 3)
Section 24 Electrical Characteristics pcm0 pcm1 pcm1w pcm1w pcm1w pcm2 pcm1 pcm1w pcm2 pcm2w CKIO A25 to A4 A3 to A0 CSD1 CSD1 CExx RD/WR (read) RDH1 RDH1 RDS1 RDS1 D15 to D0 (read) DAKD1 DAKD1 DACKn WAIT Note: Even though burst mode is set, the write cycle operation is the same as in normal mode. Figure 24.43 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3) Rev.
Page 699: Figure 24.44 Pcmcia I/O Bus Cycle (Ted = 0, Teh = 0, No Wait)
Section 24 Electrical Characteristics pci1 pci2 CKIO A25 to A0 CSD1 CSD1 CExx RD/WR ICRSD ICRSD ICIORD (read) RDH1 RDS1 D15 to D0 (read) ICWSD ICWSD ICIOWR (write) WDH4 WDD1 WDH1 D15 to D0 (write) DAKD1 DAKD1 DACKn Figure 24.44 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait) Rev.
Page 700: Figure 24.45 Pcmcia I/O Bus Cycle (Ted = 2, Teh = 1, One Wait, External Wait)
Section 24 Electrical Characteristics pci0 pci0w pci1 pci1w pci1w pci2 pci2w CKIO A25 to A0 CSD1 CSD1 CExx RD/WR ICRSD ICRSD ICIORD (read) RDH1 RDS1 D15 to D0 (read) ICWSD ICWSD ICIOWR (write) WDH4 WDH1 WDD1 D15 to D0 (write) DAKD1 DAKD1 DACKn...
Page 701: Figure 24.46 Pcmcia I/O Bus Cycle (Ted = 1, Teh = 1, One Wait, Bus Sizing)
Section 24 Electrical Characteristics pci0 pci1 pci1w pci2 pci1 pci1w pci2 pci2w CKIO A25 to A4 CSD1 CSD1 CSD1 CExx RD/WR ICRSD ICRSD ICRSD ICRSD ICIORD (read) RDH1 RDH1 RDS1 RDS1 D15 to D0 (read) ICWSD ICWSD ICWSD ICWSD ICIOWR (write) WDH3 WDH4...
Page 702: Peripheral Module Signal Timing
Section 24 Electrical Characteristics 24.3.8 Peripheral Module Signal Timing Table 24.8 Peripheral Module Signal Timing Module Item Symbol Min Unit Figure TMU, Timer input setup time — 24.47 TCLKS Timer clock input setup time — 24.48 TCKS Timer clock Edge specification —...
Page 703: Figure 24.47 Tclk Input Timing
Section 24 Electrical Characteristics CKIO TCLKS TCLK (input) Figure 24.47 TCLK Input Timing TCKS CKIO TCKS TCLK (input) TCKWL TCKWH Figure 24.48 TCLK Clock Input Timing Stable oscillation RTC crystal oscillator ROSC Figure 24.49 Oscillation Settling Time at RTC Crystal Oscillator Power-on SCKW SCKR SCKF...
Page 704: Figure 24.51 Sci I/O Timing In Clock Synchronous Mode
Section 24 Electrical Characteristics Scyc (data trans- missiion) (data reception) RTSD CTSS CTSH Figure 24.51 SCI I/O Timing in Clock Synchronous Mode CKIO PORTS1 PORTH1 PORT 7 to 0 (read) (B:P clock ratio = 1:1) PORTS2 PORTH2 PORT 7 to 0 (read) (B:P clock ratio = 2:1) PORTS3...
Page 705: Figure 24.53 Dreq Input Timing
Section 24 Electrical Characteristics CKIO DRQS DRQH DREQn Figure 24.53 DREQ DREQ Input Timing DREQ DREQ CKIO DRAKD DRAKD DRAK0/1 Figure 24.54 DRAK Output Timing Rev. 5.00 May 29, 2006 page 657 of 698 REJ09B0146-0500...
Page 706: H-Udi, Aud Related Pin Timing
Section 24 Electrical Characteristics 24.3.9 H-UDI, AUD Related Pin Timing Table 24.9 H-UDI, AUD Related Pin Timing Item Symbol Unit Figure TCK cycle time — 24.55 TCKcyc TCK high pulse width — TCKH TCK low pulse width — TCKL TCK rise/fall time —...
Page 707: Figure 24.56 Trst Input Timing (Reset Hold)
Section 24 Electrical Characteristics RESETP TRSTS TRSTH TRST Figure 24.56 TRST Input Timing (Reset Hold) TCKcyc TDIS TDIH TMSS TMSH TDOD Figure 24.57 H-UDI Data Transfer Timing RESETP ASEMDOS ASEMDOH ASEMD0 Figure 24.58 ASEMD0 ASEMD0 ASEMD0 ASEMD0 Input Timing Rev. 5.00 May 29, 2006 page 659 of 698 REJ09B0146-0500...
Page 708: 24.3.10 A/D Converter Timing
Section 24 Electrical Characteristics AUDCYC AUDCK AUDD AUDD AUDATA AUSYD AUDSYNC Figure 24.59 AUD Timing 24.3.10 A/D Converter Timing Table 24.10 A/D Converter Timing Item Symbol Unit Figure External trigger input pulse width — — tcyc 24.60 TRGW External trigger input start delay time —...
Page 709: Figure 24.60 External Trigger Input Timing
Section 24 Electrical Characteristics 1 state TRGW ADTRG input TRGS ADCR Figure 24.60 External Trigger Input Timing Pφ Address Write signal Input sampling timing CONV Legend: : A/D conversion start delay : Input sampling time : A/D conversion time CONV Notes: 1.
Page 710: 24.3.11 Ac Characteristics Measurement Conditions
Section 24 Electrical Characteristics 24.3.11 AC Characteristics Measurement Conditions • I/O signal reference level: VccQ/2 (VccQ = 3.3 ± 0.3 V, Vcc = 1.9 ± 0.15 V) • Input pulse level: VssQ to 3.0 V (where RESETP, RESETM, ASEMD0, ADTRG, TRST, CA, NMI, IRQ5 to IRQ0, CKIO, and MD5 to MD0 are within VssQ to VccQ) •...
Page 711: 24.3.12 Delay Time Variation Due To Load Capacitance
Section 24 Electrical Characteristics 24.3.12 Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 pF) is connected to this LSI's pins is shown below. The graph shown in figure 24.63 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device.
Page 712: A/D Converter Characteristics
Section 24 Electrical Characteristics 24.4 A/D Converter Characteristics Table 24.11 lists the A/D converter characteristics. Table 24.11 A/D Converter Characteristics Conditions: VccQ = 3.3 ± 0.3 V, Vcc = 1.9 ± 0.15 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to+75°C Item Unit Resolution...
Page 713: Appendix
Appendix Appendix Equivalent Circuits of I/O Buffer for Each Pin Circuit Function Pin Name WAIT Input with enable BREQ Input data Input enable Input with enable RxD0/SCPT[0] VccQ Pull-up with enable RxD2/SCPT[2] Pull-up enable AUDCK/PTG[4] Input data Input enable ASEMD0 Schmitt trigger input Input data MD[5:0]...
Page 714 Appendix Circuit Function Pin Name Input with enable AN[1:0]/PTJ[1:0] Input data Analog input with enable Input enable Input enable Input analog data Input with enable AN[3:2]/DA[0:1]/PTJ[3:2] Input data Analog input with enable Input enable Analog output with Input enable enable Input analog data Output enable...
Page 715 Appendix Circuit Function Pin Name 3-state output D[31:24]/PTB[7:0] VccQ Input with enable D[23:16]/PTA[7:0] Pull-up with enable D[15:0] Output enable A[11:0] Output data BS/PTC[0] VccQ VssQ WE2/DQMUL/ICIORD/PTC[1] Pull-up enable WE3/DQMUU/ICIOWR/PTC[2] Input data CS[4:2]/PTC[5:3] Input enable CS5/CE1A/PTC[6] CS6/CE1B/PTC[7] CE2A/PTD[6] CE2B/PTD[7] RASL/PTD[0] RASU/PTD[1] CASL/PTD[2] CASU/PTD[3] CKE/PTD[4]...
Page 716 Appendix Circuit Function Pin Name 3-state output RD/WR VccQ Input with enable CKIO Output enable Output data VssQ Input data Input enable TDI/PTG[0] 3-state output VccQ TCK/PTG[1] Input with enable Output enable TMS/PTG[2] Schmitt trigger input Output data TRST/PTG[3] Pull-up with enable IRQ[3:0]/IRL[3:0]/PTH[3:0] VccQ VssQ...
Page 717: Pin Functions
Appendix Pin Functions Pin Functions Table B.1 shows pin states during resets, power-down states, and the bus-released states. Table B.1 Pin States during Resets, Power-Down States, and Bus-Released State Reset Power-Down Power-On Manual Category Reset Reset Standby Sleep Released Clock EXTAL XTAL IO *...
Page 718 Appendix Reset Power-Down Power-On Manual Category Reset Reset Standby Sleep Released ZH * Bus control CS[2:4]/PTC[5:3] OP * ZH * OP * ZP * CS5/CE1A/PTC[6] OP * ZH * OP * ZP * CS6/CE1B/PTC[7] OP * ZH * OP * ZP * BS/PTC[0] OP *...
Page 719 Appendix Reset Power-Down Power-On Manual Category Reset Reset Standby Sleep Released ZI * IZ * IZ * SCIF with RxD2/SCPT[2] FIFO ZO * ZK * OZ * OZ * TxD2/SCPT[2] ZP * ZK * IOP * IOP * SCK2/SCPT[3] RTS2/SCPT[4] OP * ZK * OP *...
Page 720 Appendix Notes: 1. Depending on the clock mode (MD2 to MD0 setting) 2. 0 when DA output is enabled: otheruise Z. 3. K or P when the port function is used. 4. K or P when the port function is used. Z or O when the port function is not used depending on register setting.
Page 721: Pin Specifications
Appendix Pin Specifications Table B.2 shows the pin specifications. Table B.2 Pin Specifications Number of Pins FP-176C TBP-208A Function Clock mode setting Clock mode setting Clock mode setting Area 0 bus width setting Area 0 bus width setting Endian setting D31 to D24/ 5, 6, 7, 8, 9, 10, F4, F3, F2, F1,...
Page 722 Appendix Number of Pins FP-176C TBP-208A Function CS2/PTC[3] O / I/O Chip select 2 / input/output port C CS3/PTC[4] O / I/O Chip select 3 / input/output port C CS4/PTC[5] O / I/O Chip select 4 / input/output port C CS5/CE1A/PTC[6] O / O / I/O Chip select 5 / CE1 (area 5 PCMCIA) / input/output...
Page 723 Appendix Number of Pins FP-176C TBP-208A Function ASEBRKAK/PTF[6] O / I/O ASE break acknowledge (H-UDI) / input/output port F ASEMDO ASE mode (H-UDI) CAP1 — PLL1 external capacitance pin CAP2 — PLL2 external capacitance pin XTAL Clock oscillator pin EXTAL External clock / crystal oscillator pin XTAL On-chip RTC crystal oscillator pin...
Page 724 Appendix Number of Pins FP-176C TBP-208A Function ADTRG/PTG[5] Analog trigger / input port G DREQ0/PTH[5] I / I/O DMA request / input/output port H DREQ1/PTH[6] I / I/O DMA request / input/output port H 13, 27, 39, H4, L3, P3, Power Input/output power supply (3.3 V) 51, 63, 86,...
Page 725: Processing Of Unused Pins
Appendix Processing of Unused Pins • When RTC is not used  EXTAL2: Pull up to (V -RTC)  XTAL2: Leave unconnected  V – RTC: Power supply (1.9)  V – RTC: Power supply (0 V) • When PLL1 is not used ...
Page 726: Pin States In Access To Each Address Space
Appendix Pin States in Access to Each Address Space Table B.3 Pin States (Normal Memory/Little Endian) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/ Byte Access Byte Access Word/Longword Longword Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled Enabled...
Page 727 Appendix 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access Longword Access (Address (Address (Address (Address (Address (Address 4n + 1) 4n + 2) 4n + 3) 4n + 2) CS6 to CS2, CS0 Enabled Enabled Enabled...
Page 728: Table B.4 Pin States (Normal Memory/Big Endian)
Appendix Table B.4 Pin States (Normal Memory/Big Endian) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/ Byte Access Byte Access Word/Longword Longword Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled Enabled Enabled High High High High RD/WR High...
Page 729 Appendix 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access Longword Access (Address (Address (Address (Address (Address (Address 4n + 1) 4n + 2) 4n + 3) 4n + 2) CS6 to CS2, CS0 Enabled Enabled Enabled...
Page 730: Table B.5 Pin States (Burst Rom/Little Endian)
Appendix Table B.5 Pin States (Burst ROM/Little Endian) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/ Byte Access Byte Access Word/Longword Longword Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled Enabled Enabled — — — —...
Page 731 Appendix 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access Longword Access (Address (Address (Address (Address (Address (Address 4n + 1) 4n + 2) 4n + 3) 4n + 2) CS6 to CS2, CS0 Enabled Enabled Enabled...
Page 732: Table B.6 Pin States (Burst Rom/Big Endian)
Appendix Table B.6 Pin States (Burst ROM/Big Endian) 8-Bit Bus Width 16-Bit Bus Width Byte/Word/ Byte Access Byte Access Word/Longword Longword Access (Address 2n) (Address 2n + 1) Access CS6 to CS2, CS0 Enabled Enabled Enabled Enabled — — — —...
Page 733 Appendix 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access Longword Access (Address (Address (Address (Address (Address (Address 4n + 1) 4n + 2) 4n + 3) 4n + 2) CS6 to CS2, CS0 Enabled Enabled Enabled...
Page 734: Table B.7 Pin States (Synchronous Dram/Little Endian)
Appendix Table B.7 Pin States (Synchronous DRAM/Little Endian) 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access Longword Access (Address (Address (Address (Address (Address (Address 4n + 1) 4n + 2) 4n + 3) 4n + 2) CS6 to CS2, CS0 Enabled...
Page 735: Table B.8 Pin States (Synchronous Dram/Big Endian)
Appendix Table B.8 Pin States (Synchronous DRAM/Big Endian) 32-Bit Bus Width Byte Byte Byte Byte Word Word Access Access Access Access Access Access Longword Access (Address (Address (Address (Address (Address (Address 4n + 1) 4n + 2) 4n + 3) 4n + 2) CS6 to CS2, CS0 Enabled...
Page 736: Table B.9 Pin States (Pcmcia/Little Endian)
Appendix Table B.9 Pin States (PCMCIA/Little Endian) PCMCIA Memory Interface (Area 5) PCMCIA/IO Interface (Area 5) 8-Bit Bus 8-Bit Bus 16-Bit Bus Width 16-Bit Bus Width Width Width Byte/ Byte Byte Byte/ Byte Byte Word/ Word/ Word/ Access Access Word/ Access Access Longword...
Page 737 Appendix PCMCIA Memory Interface PCMCIA/IO Interface (Area 6) (Area 6) 8-Bit 8-Bit 16-Bit Bus Width 16-Bit Bus Width Width Width Byte/ Byte Byte Byte/ Byte Byte Word/ Word/ Word/ Access Access Word/ Access Access Longword Longword Longword (Address (Address Longword (Address (Address Access...
Page 738: Table B.10 Pin States (Pcmcia/Big Endian)
Appendix Table B.10 Pin States (PCMCIA/Big Endian) PCMCIA Memory Interface (Area 5) PCMCIA/IO Interface (Area 5) 8-Bit Bus 8-Bit Bus 16-Bit Bus Width 16-Bit Bus Width Width Width Byte/ Byte Byte Byte/ Byte Byte Word/ Word/ Word/ Access Access Word/ Access Access Longword...
Page 739 Appendix PCMCIA Memory Interface PCMCIA/IO Interface (Area 6) (Area 6) 8-Bit 8-Bit 16-Bit Bus Width 16-Bit Bus Width Width Width Byte/ Byte Byte Byte/ Byte Byte Word/ Word/ Word/ Access Access Word/ Access Access Longword Longword Longword (Address (Address Longword (Address (Address Access...
Page 740: Product Lineup
Appendix Product Lineup Model Marking Package HD6417706F133 176-pin plastic LQFP (FP-176C/PLQP0176KD-A) HD6417706BP133 208-pin TFBGA (TBP-208A/TTBG0208JA-A) Rev. 5.00 May 29, 2006 page 692 of 698 REJ09B0146-0500...
Page 741: Package Dimensions
Appendix Package Dimensions Figures D.1 and D.2 show the SH7706 package dimensions. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP176-24x24-0.50 PLQP0176KD-A FP-176C/FP-176CV 1.9g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Terminal cross section...
Page 742: Figure D.2 Package Dimensions (Tbp-208A)
Appendix JEITA Package Code RENESAS Code Previous Code MASS[Typ.] T-TFBGA208-12x12-0.65 TTBG0208JA-A TBP-208A/TBP-208AV 0.26g × Dimension in Millimeters Reference Symbol 12.00 12.00 0.15 0.20 1.20 0.26 0.31 0.36 0.65 0.35 0.40 0.45 9 10 11 12 13 14 15 16 17 0.08...
Page 743: Index
Index Index ADCR ......536, 588, 600, 605 BDRB......144, 585, 594, 602 ADCSR ......533, 588, 600, 605 BETR ......150, 585, 595, 602 ADDRA ..........532 Big-endian..........20 ADDRAH ....... 531, 588, 600, 605 BRCR......147, 585, 594, 602 ADDRAL......
Page 744 Index DMATCR_1 ....256, 588, 598, 604 Mode 1 ............ 307 DMATCR_2 ....256, 588, 598, 605 Mode 2 ............ 307 DMATCR_3 ....256, 588, 599, 605 Mode 7 ............ 307 Dual Address Mode ........ 273 Multiple Virtual Memory Mode....55 Exception Codes ........
Page 745 Index RHRAR......348, 586, 593, 603 SCTSR2 ..........446 RHRCNT ......344, 586, 592, 603 SDBPR............555 RMINAR ......347, 586, 593, 603 SDBSR............556 RMINCNT ...... 343, 586, 592, 603 SDIR ....... 555, 589, 601, 606 RMONAR....... 351, 586, 593, 603 SDMR ........193, 586, 594 RMONCNT ....
Page 746 Index Rev. 5.00 May 29, 2006 page 698 of 698 REJ09B0146-0500...
Page 747 Publication Date: 1st Edition, September 2001 Rev.5.00, May 29, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 748 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 749 SH7706 Group Hardware Manual...

Renesas SH7706 Series Hardware Manual

Configuration of this Manual

Table of Contents

Section 1 Overview

Section 2 CPU

Appendix

Quick Links

Chapters

Related Manuals for Renesas SH7706 Series

Summary of Contents for Renesas SH7706 Series